JPH11122484A - Picture data processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a processing for converting only picture signal components corresponding to input light quantity from an output signal divided into two systems for each picture element into digital data with a small number of parts and at low costs while a high speed and highly precise processing can be ensured. SOLUTION: An integrated circuit is constituted as a processing circuit 16 including sample/hold circuits 4a and 4b, variable gain amplifiers 5a and 5b, DC potential normalizing circuits 8a, 8b, 9a, and 9b, peak hold circuit 12, reference voltage switching circuit 13, A/D converters 7a and 7b, and driving circuit 11. Thus, a necessary function as a picture data processing circuit can be realized by a timing generating circuit and the processing circuit 16 in the integrated circuit constitution, and the reduction of the number of parts and costs can be easily realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention deals with image data read using a photoelectric conversion element such as a CCD line sensor, and converts an image signal corresponding to an input light amount from an output signal divided into two systems from the photoelectric conversion element. The present invention relates to an image data processing circuit for converting only a signal component into digital data.

[0002]

2. Description of the Related Art In image reading apparatuses used in image scanners, digital copying machines, facsimile machines, etc., CCD line sensors (CCD linear image sensors) are frequently used as reading elements. For example, in digital copiers, middle- and low-speed machines have become widespread, and are shifting to high-speed machines in order to respond to recent demands for high-speed processing. In any case, CC
Basically, the output of the D-line sensor is divided into two systems of even-numbered pixels and odd-numbered pixels and output.

Here, as the image data processing circuit, 2
A sample-and-hold circuit divided into two systems in accordance with the divided image data, a multiplex circuit that combines the outputs of these sample-and-hold circuits into a single-system output voltage in time series, and an external input A variable gain amplifier whose amplification factor is varied according to a voltage value to be supplied, a drive circuit for outputting an analog signal to drive the A / D converter, and detecting a peak value of an output signal of the drive circuit. Voltage selection circuit for selecting one of an output voltage of the peak hold circuit and two kinds of voltages supplied from the outside and outputting as a reference voltage of an A / D converter connected to the outside A circuit provided with a circuit in an IC circuit configuration has been proposed.

[0004]

However, according to such a conventional example, an A / D for converting into digital data is used.
Since a D converter is not built in, an A / D converter is separately required, resulting in an increase in the number of parts and an increase in cost. Further, since the A / D converter is not built in, a buffer for driving the data bus is required separately after the A / D converter which is separately provided, which also increases the number of parts and the cost. Providing the A / D converter and the buffer externally in this way causes a shift in data timing, and makes high-speed operation difficult.

In addition, in order to output an analog signal to the outside of the IC circuit, it is necessary to drive an external load (such as a stray capacitance or an input capacitance of an A / D converter), thereby ensuring high speed and high accuracy. Hateful. Also, since there is only one variable gain amplifier, it is not possible to correct the variation in the amplitude of the input signals of the two systems and the variation in the gain of the sample-and-hold circuit, and it is difficult to convert the data into digital data with high accuracy. is there. Further, a D / A converter for generating an analog signal for setting the gain of the variable gain amplifier is required, resulting in an increase in the number of parts and an increase in cost.

Further, a timing signal for each functional block must be individually supplied to each functional block, and a complicated timing signal generating circuit is required.

Further, since there is no communication function with the external controller, control by the external controller cannot be performed, and automation such as adjustment cannot be achieved.

Therefore, the present invention provides a method for converting 1
The process of converting only the image signal component corresponding to the input light amount into digital data from the output signal divided into two systems for each pixel is realized at low cost with few parts while ensuring high speed and high accuracy. It is an object of the present invention to provide an image data processing circuit which can be obtained.

An object of the present invention is to provide an image data processing circuit capable of simplifying an external timing generation circuit.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image data processing circuit which can freely set a gain and the like from the outside and can achieve automatic adjustment.

An object of the present invention is to provide an image data processing circuit capable of high-speed operation with a small timing shift.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image data processing circuit capable of fine-tuning the timing and transferring data with a clock on the data processing side.

It is an object of the present invention to provide an image data processing circuit capable of transmitting high-speed image data over a long distance.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image data processing circuit which can be designed under advantageous conditions without increasing power consumption and without having to increase the operating frequency of a peak detection circuit.

The present invention focuses on the fact that the resolution of the A / D converter used in most of the current systems is 8 bits, and the A / D converter having a resolution of 9 bits or more is used. An object of the present invention is to provide an image data processing circuit capable of preventing the influence of noise.

[0016]

According to the first aspect of the present invention,
Two input terminals to which signals divided into two systems are input for each pixel, two sample and hold circuits for individually sampling signals input from each input terminal, and a DC potential of each input signal individually Two first direct-current potential regulating circuits for defining, and individually amplifying, at a set amplification factor, signals sampled by the respective sample-and-hold circuits.
Two variable gain amplifiers, two drive circuits for individually increasing the drive capability of the output of each variable gain amplifier, two second DC potential defining circuits for individually defining the DC potential of the output signal of each drive circuit, Two A / D converters for individually converting the output signals of the respective drive circuits into digital signals;
A data synthesizing circuit for selecting a digital signal output from the converter for each pixel, synthesizing the digital signal in a time series as one digital signal, and outputting the digital signal, and a driving capability of the digital signal output from the data synthesizing circuit. A data drive circuit for increasing the power, a peak hold circuit for detecting a peak value of an input signal to two A / D converters, and a peak voltage detected by the peak hold circuit and an externally applied input voltage set in advance. A reference voltage switching circuit for selecting one of the fixed voltages and setting it as a reference voltage for the two A / D converters as an integrated processing circuit.

Accordingly, an integrated circuit is formed as a processing circuit including an A / D converter and a driving circuit as well as a sample and hold circuit, a variable gain amplifier, a DC potential regulating circuit, a peak hold circuit, and a reference voltage switching circuit. Therefore, the function required as an image data processing circuit can be realized by the timing generation circuit and the processing circuit having the integrated circuit configuration. Therefore, reduction of the number of parts and cost reduction can be easily realized.

According to a second aspect of the present invention, there is provided the image data processing circuit according to the first aspect, further comprising a timing generating circuit for defining an operation timing of the processing circuit based on a timing signal supplied from the outside. Therefore, the timing required inside the integrated processing circuit is generated based on the timing generation circuit in the processing circuit, so that the external timing generation circuit itself can be very simple.

According to a third aspect of the present invention, in the image data processing circuit of the first aspect, there is further provided communication means for externally controlling the operation state of the integrated processing circuit. Therefore, since the processing circuit has communication means with the external controller, the setting of the gain and the offset can be set more freely than the external controller, so that the adjustment can be automated and the assembly cost can be greatly reduced. Can also be reduced.

According to a fourth aspect of the present invention, in the image data processing circuit according to the first, second or third aspect, the processing circuit outputs image data by a digital signal and simultaneously outputs a clock signal for the image data latch. Output.
Therefore, since the latch clock is output simultaneously with the original image data, the timing deviation can be extremely reduced, and high-speed operation can be performed.

According to a fifth aspect of the present invention, in the image data processing circuit of the first, second or third aspect, the processing circuit outputs the image data based on the digital signal in synchronization with a clock signal supplied from the outside. . Therefore, the final image data is output in synchronization with an external clock signal, so that the timing can be finely adjusted and the data can be transferred in accordance with the clock on the data processing side.

According to a sixth aspect of the present invention, in the image data processing circuit according to the first, second, or third aspect, the processing circuit outputs image data by a digital signal, and outputs image data of an even number of the two systems. A latch clock signal and a clock signal for odd-numbered image data latch are simultaneously output. Therefore, a latch circuit is provided outside the processing circuit as needed, and the digital data combined into one system can be divided into two systems of digital data for the even system and the odd system, so that high speed can be achieved. Even so, the frequency can be halved, and long-distance data transmission can be easily realized.

The invention according to claim 7 is the invention according to claims 1 to 6
In the image data processing circuit according to any one of the above, continuous output of only the even-numbered image data of the two systems, continuous output of only the odd-numbered image data of the two systems, A signal form switching circuit for selecting either the continuous H level output or the continuous L level output is added. Therefore, when determining the gain of the variable gain amplifier, it is possible to output only the image data of the even-numbered system or to output only the image data of the odd-numbered system, so that substantially one pixel data continues for two pixels. Driving can be performed with the frequency kept low, the power consumption does not increase, and the operating frequency of the peak detection circuit can be half that in the case described above.

[0024] The invention described in claim 8 is the invention according to claims 1 to 7.
A / D in the image data processing circuit according to any one of
The converter has a resolution of 9 bits or more, only the upper 8 bits are valid, and the remaining lower bits are regarded as L level or H level. Therefore, the resolution of the A / D converter used in most current systems is 8 bits, and when using an A / D converter having a resolution of 10 bits or 12 bits in such a system, In a situation where only the upper 8 bits are valid and the remaining lower bits are unused, the unused lower bits are forcibly fixed at the L level or the H level. Can be prevented.

[0025]

FIG. 1 shows a first embodiment of the present invention.
It will be described based on. The image data processing circuit according to the present embodiment includes, for example, an even pixel (Even) and an odd pixel (Odd).
This is a circuit for converting only an image signal component corresponding to an input light amount from an output signal of a CCD line sensor having two systems of outputs into a digital signal. First, signals EIN and OIN divided into two systems are Two input terminals 1a,
1b is provided. An even-numbered channel circuit (Ech) 3a is connected to an input terminal 1a to which the signal EIN is input via an AC coupling capacitor 2a, and an input terminal 1b to which the signal OIN is input via an AC coupling capacitor 2b. The odd channel circuit (Och) 3b is connected.

The even-numbered channel circuit 3a includes a sample-and-hold circuit (S & H) 4a, a variable gain amplifier (GCA) 5a, a drive circuit (DRV) 6a, and an A-series circuit connected in series.
A first clamp circuit (CLMPIN) 8 that is connected between the input and output of the sample hold circuit 4a and functions as a first DC potential defining circuit, together with the / D converter (ADC) 7a.
a and a second clamp circuit (CLMPAD) 9a connected between the input and output of the variable gain amplifier (GCA) 5a and functioning as a second DC potential regulating circuit.

The same applies to the odd channel circuit 3b side.
Sample and hold circuit (S & H) 4 connected in series
b, variable gain amplifier (GCA) 5b, drive circuit (DR
V) A first clamp circuit (C), which is connected between the input and output of the sample hold circuit 4b and functions as a first DC potential defining circuit, together with the 6b and the A / D converter (ADC) 7b.
LMPIN) 8b and a second clamp circuit (CLMPAD) 9b connected between the input and output of the variable gain amplifier (GCA) 5b and functioning as a second DC potential regulating circuit.

Here, the sample and hold circuits 4a and 4b
The one which can be switched by setting between normal sample hold and correlated double sampling (DOS) is used.

On the output side of the A / D converters 7a and 7b, digital signals output from the A / D converters 7a and 7b are selected for each pixel, and one system is provided in time series. A multiplexing circuit (MPX) 10 functioning as a data synthesizing circuit for synthesizing and outputting as a digital signal is connected, and a data driving circuit (BUF) on the output side of the multiplexing circuit 10 for enhancing the driving capability of the digital signal.
11 are connected. The output of the data drive circuit 11 is digital data DO to be output to the outside.

Further, a peak hold circuit that holds the peak value of the input signal to the A / D converters 7a and 7b (accordingly, the output signal of the variable gain amplifiers 5a and 5b), amplifies the signal with the set gain, and outputs the amplified signal. (P & H) 12 is provided. Further, either the peak voltage detected by the peak hold circuit 12 or a preset fixed voltage or an externally applied input voltage (RCONT) is selected and used as a reference voltage for the A / D converters 7a and 7b. A reference voltage switching circuit (REF) 13 for setting the supply is provided. The reference voltage switching circuit 13 outputs a preset fixed voltage (RDACO) to the outside in addition to the above function.

In addition, a timing generation circuit (TIMIN
G) 14 and an interface circuit (I / F) 15 functioning as a communication unit.
Reference numeral 6 denotes an IC configuration.

Here, the timing generation circuit 14 includes: a. SHCK signal that defines the operation timing of the sample and hold circuits 4a and 4b (the speed of the SHCK signal is the same as the frequency of the output pixel) b. When the input signals EIN and OIN are opposite phase signals, an E / O signal indicating whether the edge of the SHCK signal is valid in the even channel circuit 3a or valid in the odd channel circuit 3b (this E / O signal).
The signal indicates, as another function, whether or not the edge of the SHCK signal is valid when the input signals EIN and OIN are in-phase signals.) C. PCK signal that defines the sampling timing of the reference voltage in DCS operation d. Like the E / O signal for the SHCK signal, the PCK
A PE / O signal that defines the function of the signal edge e. CLMPIN signal for defining the timing of the first clamp circuits 8a and 8b f. CLMPAD signal defining timing of second clamp circuits 9a and 9b g. A PWIND signal defining a peak detection period of the peak hold circuit 12 h. The reference voltage switching circuit 13 receives an AEMODE signal and a SLEAD signal to determine which voltage is to be supplied as a reference voltage for the A / D converters 7a and 7b. Generate and supply timing signals.

The interface circuit 15 is for interfacing with an external controller (not shown), and includes a chip select signal (XCS), a read /
Write signal (R / W), serial clock (SCL
K), a serial interface operating with serial data input (SDIN) and serial data output (SDOUT). Sample hold circuits 4a, 4b
Switching of the DCS operation, and the sample and hold circuit 4a,
4b and the multiplexing circuit 10 for switching between in-phase and out-of-phase, setting the gains of the variable gain amplifiers 5a and 5b,
The setting of the clamp potential of the clamp circuits 9a and 9b, the setting of the fixed voltage (RDACO) of the reference voltage switching circuit 13, the setting of the gain of the peak hold circuit 12, and the like are performed through the interface circuit 15.

In such a configuration, the signal EIN input from the CCD line sensor to the input terminal 1a is AC-coupled through the capacitor 2a to form the sample-and-hold circuit 4
is input to a. Whether the sample-hold circuit 4a uses a normal sample-hold or correlated double sampling (DCS) is controlled by an external controller via the interface circuit 15. The output of the sample and hold circuit 4a is input to the first clamp circuit 8a, and is effective only for a predetermined time so that the DC potential at the output of the sample and hold circuit 4a becomes a constant potential. The input DC potential is defined. First clamp circuit 8a
Sample-and-hold circuit 4 with a constant DC potential
The output of a is input to the variable gain amplifier 5a and is amplified by the set gain. The output of the variable gain amplifier 5a having a sufficient amplitude by this amplification is input to a drive circuit 6a for driving the A / D converter 7a and the peak hold circuit 12. Here, the output of the drive circuit 6a is input to the second clamp circuit 9a. This second clamp circuit 9
In a, the DC voltage output from the drive circuit 6a is valid only for a predetermined time so that it becomes a set voltage. The DC voltage from the drive circuit 6a that has become the set voltage is A
The digital data (DAD) input to the
E) and output to the multiplex circuit 10 side.

Such processing is the same for the signal EIN input from the CCD line sensor to the input terminal 1b, and is processed in the odd-numbered channel circuit 3b.
The data is converted into digital data (DADO) by the D converter 7b and output to the multiplex circuit 10 side.

In the multiplex circuit 10, these A
Digital data D output from / D converters 7a and 7b
ADE, DADO DAD alternately for each pixel
E, DADO, DADE, DADO,... Are combined in a time series as one system of digital data (DOMAX). One system of digital data (DOMAX) synthesized by the multiplex circuit 10 is output to the data drive circuit 11.
As a result, the driving capability is enhanced and the digital data is output to the outside of the processing circuit 16 as final digital data (DO).

On the other hand, the outputs of the two drive circuits 6a and 6b are both input to a peak hold circuit 12, which peak-holds the higher voltage value of the two output signals and is amplified by a preset gain. Are output to the reference voltage switching circuit 13 side. In the reference voltage switching circuit 13, the peak voltage supplied from the peak hold circuit 12 and a preset fixed voltage or an externally supplied input voltage (RCON)
T) is selected on the basis of the AMODE and SLEAD signals and supplied as a reference voltage to the A / D converters 7a and 7b.

As described above, according to the present embodiment, the sample and hold circuits 4a and 4b and the variable gain amplifiers 5a. 5
b, Clamp circuits 8a, 8 capable of setting clamp potential
b, 9a, 9b, the peak hold circuit 12, the reference voltage switching circuit 13, as well as the A / D converters 7a, 7b, and the data drive circuit 11, which are integrated in the processing circuit 16, so that the timing generation circuit The functions required as an image data processing circuit can be realized by the processing circuit 14 and the processing circuit 16 having this IC configuration. Therefore, reduction of the number of parts and cost reduction can be easily realized. Further, since the necessary timing inside the IC is generated based on the timing generation circuit 14 inside the IC (inside the processing circuit 16), the external timing generation circuit itself can be very simple.
Further, since the processing circuit 16 includes the interface circuit 15 with the external controller, the gain setting,
Since the setting of the offset and the like can be set freely by the external controller, the adjustment can be automated, and the assembly cost can be greatly reduced.

A second embodiment of the present invention will be described with reference to FIG. The same parts as those described in the above embodiments are denoted by the same reference numerals, and description thereof is omitted (the same applies to the following embodiments). The A / D converters 7a, 7
The configuration up to b is the same as the configuration shown in FIG.
Illustration is also omitted. In the present embodiment, a latch circuit (LA) is provided between the multiplex circuit 10 and the data drive circuit 11.
TCH) 17 is interposed. This latch circuit 17
Latches digital data (DOMPX) synthesized by the multiplexing circuit 10 into one system at a signal timing obtained by delaying the SHCK signal by the delay circuit (DLY) 18 to secure a hold time for the SHCK signal. Plays the role of aligning timing. Note that the E / O signal and the SHCK signal are output to the multiplex circuit 10.
D-type flip-flop (DF)
F) 19 is connected. The SHCK signal is also input to the clock terminal of the data drive circuit 11, and the clock output (CKOUT) is output together with the image data (DO).
Is configured to output.

In such a configuration, the multiplex circuit 10 outputs the data DATE, D converted to digital data at a timing determined by the SHCK signal and the E / O signal.
The input of ATO is switched by a signal obtained by latching the E / O signal with the SHCK signal (switched by the output of the D-type flip-flop 19), and is synthesized as one system of digital data (DOMPX). The latch circuit 17 converts the digital data (DOMPX) synthesized by the multiplex circuit 10 into SHC
The K signal is latched by the signal delayed by the delay circuit 18,
The timing is made uniform by securing a hold time for the SHCK signal. The data drive circuit 11 receiving the output from the latch circuit 17 enhances the drive capability of the data and simultaneously outputs the SHCK signal, so that the output data (DO) and the clock output (CKOUT) are output.
Is maintained with the timing relation inside the IC (inside the processing circuit 16).

Therefore, according to the present embodiment, the latch clock is output simultaneously with the image data.
Timing deviation can be extremely reduced, and high-speed operation can be performed.

A third embodiment of the present invention will be described with reference to FIG. In the present embodiment, as compared with FIG. 2, the input of the SHCK signal to the delay circuit 18 and the data drive circuit 11 is eliminated, and the clock signal (EXTCK) supplied from the outside is input to the delay circuit 18. ing.

In such a configuration, the multiplex circuit 10 outputs the data DATE, D converted to digital data at a timing determined by the SHCK signal and the E / O signal.
The input of ATO is switched by a signal obtained by latching the E / O signal with the SHCK signal (switched by the output of the D-type flip-flop 19), and is synthesized as one system of digital data (DOMPX). The latch circuit 17 converts the digital data (DOMPX) synthesized by the multiplexing circuit 10 into a clock signal (EXTCK) supplied from the outside, and
8 and the clock signal (EX
The timing is made uniform by securing a hold time for TCK). In the data driving circuit 11 receiving the output from the latch circuit 17, the driving capability of the data is increased.

Therefore, according to the present embodiment, the output data (DO) is output in synchronization with the clock signal (EXTCK) from the outside, so that the timing can be finely adjusted and the output data (DO) can be adjusted to the clock on the data processing side. Data transfer.

A fourth embodiment of the present invention will be described with reference to FIG. In the present embodiment, as compared with FIG. 2, the direct input of the SHCK signal to the data drive circuit 11 is eliminated, and instead, the Q terminal output and the QB (Q bar) terminal output of the D-type flip-flop 19 are changed. The clock signals (ECK) for even-numbered image data latches and the clock signals (OCK) for odd-numbered image data latches are simultaneously output by being individually input to the data drive circuit 11. ing.

In such a configuration, the multiplex circuit 10 outputs the data DATE, D converted to digital data at a timing determined by the SHCK signal and the E / O signal.
The input of ATO is switched by a signal obtained by latching the E / O signal with the SHCK signal (switched by the output of the D-type flip-flop 19), and is synthesized as one system of digital data (DOMPX). The latch circuit 17 converts the digital data (DOMPX) synthesized by the multiplex circuit 10 into SHC
The K signal is latched by the signal delayed by the delay circuit 18,
The timing is made uniform by securing a hold time for the SHCK signal. In the data driving circuit 11 receiving the output from the latch circuit 17, the driving capability of the data is increased, and the even-numbered pixels (E pixels) at the rising edge.
And a clock signal (OCK) for latching odd-numbered pixels (O pixels) at the rising edge at the same time. In other words, the timing between the output data (DO) and the clock output (ECK, OCK) is maintained in the same timing relationship inside the IC (inside the processing circuit 16).

When high-speed image data is transmitted over a long distance, waveform distortion becomes large, and it is difficult to realize it. In this regard,
According to the present embodiment, a latch circuit is provided outside the processing circuit 16 as necessary, and the digital data (DOMPX) synthesized into one system is converted into two systems of digital data for an even system and an odd system. Can be divided into
Even at high speeds, the frequency can be halved,
Long distance data transmission can be easily realized.

A fifth embodiment of the present invention will be described with reference to FIG. In the present embodiment, as compared with FIG. 2, another multiplex circuit (MPX1) 20 functioning as a signal form switching circuit is added at the preceding stage of the multiplex circuit 10, and the multiplex circuit 10 and the latch circuit 17 are added. An OR circuit (OR) 21 is interposed therebetween. One input of the OR circuit 21 is the output of the multiplex circuit 10, and the other input is the EDIS signal, O
An output of an AND circuit (AND) 22 to which the DIS signal is input is provided. The multiplex circuit 20 includes two signal switching circuits (A, B, Y, and C, D, and Z).
Z is the input A of the original multiplex circuit 10 at the next stage,
B. Here, the multiplex circuit 20
Performs a switching operation according to the levels of the EDIS signal and the ODIS signal. When the EDIS signal is at the L level, Y
= DADE, H level, Y = DADO.
When the ODIS signal is at the L level, Z = DAD
When O and H levels, Z = DADE.

In such a configuration, the multiplex circuit 10 outputs the outputs YZ of the multiplex circuit 20 to E
/ O signal is switched by the signal latched by the SHCK signal (D
(Switched by the output of the type flip-flop 19) and synthesized as one system of digital data. OR circuit 21 is EDIS
The output of the AND circuit 22 and the output of the multiplex circuit 10 are obtained by calculating the logical product of the signal and the ODIS signal. For this reason, when both the EDIS signal and the ODIS signal are at the H level, an H-level output is output, but otherwise, the output from the multiplex circuit 10 is output as it is. The latch circuit 17 latches the data output from the OR circuit 21 with a signal obtained by delaying the SHCK signal by the delay circuit 18, and aligns the timing by securing a hold time for the SHCK signal. The data driving circuit 11 receiving the output from the latch circuit 17 enhances the driving capability of the data and simultaneously outputs the SHCK signal, so that the timing of the output data (DO) and the clock output (CKOUT) can be adjusted inside the IC ( The timing relationship in the processing circuit 16 is maintained.

Thus, when both the EDIS signal and the ODIS signal are at L level, the even pixel data DADE
And odd-numbered pixel data DADO are combined into one system and output. The EDIS signal = H level and the ODIS signal = L
In the case of the level, only the odd-numbered pixel data DADO is output. Conversely, the EDIS signal = L level and the ODIS signal = H
In the case of the level, only the even-numbered pixel data DADE is output, and when both the EDIS signal and the ODIS signal are in the H level, data of all H levels is output.

When determining the gains of the variable gain amplifiers 5a and 5b, it is necessary to detect the peak value in each of the even-numbered and odd-numbered image data when the reference light enters the CCD line sensor. In this case, the peak value on the target channel side can be easily detected by setting the even-numbered system image data or the odd-numbered system image data to L level. , And the image data must be driven at a frequency higher than the spatial frequency of the actual image. Therefore, power consumption is disadvantageously increased. In this regard, according to the present embodiment, it is possible to output only even-numbered image data or output only odd-numbered image data, so that substantially one pixel data continues for two pixels. Can be driven at a low frequency, the power consumption does not increase, and the operating frequency of the peak hold circuit 12 can be reduced to half that in the case described above.

A sixth embodiment of the present invention will be described with reference to FIG. In the present embodiment, when compared with FIG.
It is assumed that each of the / D converters 7a and 7b has a resolution of 9 bits or more.
Another OR circuit (OR1) 23 is interposed between the AND circuit 22 and the OR circuit 21. Here, of the two input systems to the OR circuit 21, DH represents data of the upper 8 bits, and DL represents data of the remaining lower bits. In the OR circuit 21, D
H is configured to take the logical sum with the H input from the OR circuit 23 side, and DL is configured to take the logical sum with the L input from the OR circuit 23 side. The OR circuit 23 receives the output of the AND circuit 22 and the LOWERS signal for controlling the lower bits.

In such a configuration, processing up to the multiplex circuit 10 is performed in the same manner as in the case of FIG. In the OR circuit 21 at the next stage, the data of the upper 8 bits is input to DH, and the data of the remaining lower bits is input to DL. In the OR circuit 21, the logical sum of the DH and H inputs and the logical sum of the DL and L inputs are respectively obtained. Here, the operation for the upper 8 bits of data DH is exactly the same as the case described with reference to FIG. 5, and when the EDIS signal and the ODIS signal are both at the H level, all the H level data is output from the OR circuit 21. In other combinations, the data from the multiplex circuit 10 is output from the OR circuit 21 as it is.

On the other hand, with respect to the data DL of the remaining lower bits, both the EDIS signal and the ODIS signal are at H level (the output of the AND gate 22 is at H level) or LO level.
When the WERS signal is at H level, the OR circuit 21 outputs H level.
The level is output, but in other combinations, the input from the multiplex circuit 10 is output from the OR circuit 21 as it is.

Therefore, in addition to the operation described with reference to FIG.
By using the OWERS signal, this LOWERS
If the signal is set to the H level, the remaining lower bits other than the upper 8 bits in the output data (DO) are forcibly regarded as the H level and output. If the LOWERS signal is set to the L level, EDIS is set. The signal can be output in a state determined by the signal and the ODIS signal.

A used in most current systems
The resolution of the / D converter is 8 bits, and when using an A / D converter having a resolution of 10 bits or 12 bits in such a system, only the upper 8 bits are valid,
The remaining lower bits are unused. In this case, the unused lower bits fluctuate at a higher frequency and can be a noise source. In this regard, according to the present embodiment, such unused lower bits are forcibly fixed to the L level or the H level, so that generation of noise can be prevented.

[0057]

According to the first aspect of the present invention, not only the sample and hold circuit, the variable gain amplifier, the DC potential regulating circuit, the peak hold circuit, and the reference voltage switching circuit, but also the A / A
Since the integrated circuit is configured as a processing circuit including the D converter and the driving circuit, a function required as an image data processing circuit can be realized by the timing generation circuit and the processing circuit having the integrated circuit configuration. The number of parts can be reduced and the cost can be easily reduced.

According to the second aspect of the present invention, the necessary timing inside the integrated circuit is generated based on the timing generation circuit inside the processing circuit, so that the external timing generation circuit itself is very simple. be able to.

According to the third aspect of the present invention, since the processing circuit has communication means with the external controller, the setting of the gain, the setting of the offset, and the like can be performed more freely than the external controller, so that the adjustment can be automated. You can also plan,
As a result, assembly costs can be significantly reduced.

According to the fourth aspect of the present invention, since a latch clock is output at the same time as the original image data, the timing deviation can be greatly reduced.
High speed operation is possible.

According to the fifth aspect of the present invention, the final image data is output in synchronization with an external clock signal, so that the timing can be finely adjusted and the data transfer is performed in accordance with the clock on the data processing side. Can be done.

According to the sixth aspect of the present invention, a latch circuit is provided outside the processing circuit as necessary, and the digital data combined into one system is divided into two systems of an even system and an odd system. Since it can be split into data,
Even at high speeds, the frequency can be halved,
Long distance data transmission can be easily realized.

According to the seventh aspect of the present invention, when determining the gain of the variable gain amplifier, it is possible to output only the even-numbered image data or to output only the odd-numbered image data.
Virtually one pixel of data continues for two pixels, so that the image data can be driven with the frequency kept low, the power consumption does not increase, and the operating frequency of the peak hold circuit can be half that in the case described above. be able to.

According to the present invention, the resolution of the A / D converter used in most of the current systems is 8
Bit, and such a system may require 10 bits or 12 bits.
When using an A / D converter having a bit resolution,
In a situation where only the upper 8 bits are valid and the remaining lower bits are unused, the unused lower bits are forcibly fixed at the L level or the H level. Can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 is a block diagram showing a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing a sixth embodiment of the present invention.

[Explanation of symbols]

 1a, 1b Input terminal 3a Even number system 3b Odd number system 4a, 4b Sample hold circuit 5a, 5b Variable gain amplifier 6a, 6b Drive circuit 7a, 7b A / D converter 8a, 8b First DC potential regulating circuit 9a, 9b 2 DC potential regulating circuit 10 data synthesizing circuit 11 data driving circuit 12 peak hold circuit 13 reference voltage switching circuit 14 timing generating circuit 15 communication means 16 processing circuit 20 signal form switching circuit

Claims (8)

[Claims] 1. Two input terminals to which signals divided into two systems are input for each pixel, two sample-and-hold circuits for individually sampling signals input from each input terminal, Two first DC potential defining circuits for individually defining a DC potential; two variable gain amplifiers for individually amplifying a signal sampled by the sample and hold circuit at a set amplification factor; Two drive circuits for individually increasing the output drive capability, two second DC potential defining circuits for individually defining the DC potential of the output signal of each drive circuit, and a digital signal for individually outputting the output signal of each drive circuit Two A / D converters for converting the digital signals output from the A / D converter into
A data synthesizing circuit that selects for each pixel and synthesizes and outputs a digital signal in a time series as one system; a data driving circuit that enhances the driving capability of the digital signal output from the data synthesizing circuit; A peak hold circuit for detecting a peak value of an input signal to the / D converter; selecting one of a peak voltage detected by the peak hold circuit, an externally supplied input voltage, and a preset fixed voltage; An image data processing circuit comprising, as an integrated processing circuit, a reference voltage switching circuit that sets a reference voltage for two A / D converters. 2. The image data processing circuit according to claim 1, further comprising a timing generation circuit for defining an operation timing of the processing circuit based on a timing signal supplied from outside. 3. The image data processing circuit according to claim 1, further comprising a communication unit for externally controlling an operation state of the integrated processing circuit. 4. The image data processing circuit according to claim 1, wherein the processing circuit outputs the image data based on the digital signal and simultaneously outputs the image data latch clock signal. 5. The image data processing circuit according to claim 1, wherein the processing circuit outputs the image data based on the digital signal in synchronization with a clock signal supplied from the outside. 6. A processing circuit outputs image data by a digital signal and simultaneously outputs an even-numbered image data latch clock signal and an odd-numbered image data latch clock signal of the two systems. 4. The image data processing circuit according to claim 1, wherein 7. A continuous output of only the image data of the even system of the two systems, a continuous output of only the image data of the odd system of the two systems, a continuous H level output or a continuous L level to the data synthesizing circuit. 7. The image data processing circuit according to claim 1, further comprising a signal form switching circuit for selecting any one of the outputs. 8. The A / D converter has a resolution of 9 bits or more, makes only the upper 8 bits valid, and regards the remaining lower bits as L level or H level. The image data processing circuit according to claim 1.