JPH11122076A - Signal delay circuit using serial memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fail-safe signal delay circuit, capable of highly accurately setting delay time without being affected by the dispersion of a circuit element. SOLUTION: This circuit is provided with a signal generator 11 for generating clock signals CK, a frequency divider circuit 12 for frequency dividing the clock signals CK, an AND gate 13 for ANDing input signals and frequency divided output, a serial memory 14 for storing data output from the AND gate 13 for prescribed bits every time of the input of the clock signals CK and successively sweeping out data from the data stored first at the same as with the storage of the data at the time of being saturated, a detection circuit 15 for generating output, only when alternating signals are generated from the serial memory 14 and an OR gate 16 for computing the OR of the input signals and detection output and generating delay output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a signal delay circuit, and more particularly to a signal delay circuit having a fail-safe configuration using a serial memory.

[0002]

2. Description of the Related Art As one of signal delay circuits, there is, for example, an off-delay circuit. This off-delay circuit is a signal delay circuit in which the output signal rises following the rise of the input signal, and the output signal falls with a predetermined time delay after the fall of the input signal. An off-delay circuit that satisfies the following output error characteristics 1) and 2) upon failure is called a fail-safe off-delay circuit.

1) No output occurs when no input signal is input. 2) The off-delay time (delay time) is reduced but not extended. FIG. 8 shows a configuration example of a conventional fail-safe off-delay circuit that satisfies the above conditions 1) and 2).

In FIG. 8, this off-delay circuit 1
Are two capacitors C1 and C2 and two diodes D
1 and D2, and a conventionally known fail-safe level test circuit 3 using, for example, a fail-safe window comparator. The input signal is supplied to the voltage doubler rectifier circuit 2 as an alternating signal that changes between the power supply potential V _CC and 0 V, and the voltage doubler rectifier circuit 2 rectifies the voltage. The rectified signal y of the voltage doubler rectifier circuit 2 is level-tested by the level test circuit 3, and when the rectified signal y exceeds a threshold value, an output signal is generated from the level test circuit 3, and this output signal is used as the output signal z of the off-delay circuit 1. .

In the off-delay circuit 1 having such a configuration,
As shown in FIG. 9, when an input signal is input, voltage doubler rectification is performed.
The rectified signal y of the circuit 2 is the power supply potential V_CCA higher level
You. Assuming the threshold value Vth of the level test circuit 3, the rectified signal y
Is higher than the threshold value Vth, the level test circuit 3
Output occurs and the input signal stops, then double voltage rectification
Until the rectified signal y of the circuit 2 becomes lower than the threshold value Vth
Output signal z continues to be generated and output after input signal stops
Off-delay time T until signal z stops _OFFTona
You. This off delay time T_OFFIs the level test circuit
Assuming that the input resistance of No. 3 is Ri, the smoothing of the voltage doubler rectifier circuit 2 is performed.
Between the capacitor C2 and the input resistance Ri of the level test circuit 3
Time constant (T_OFF= C2 x Ri)
You.

It is preferable that the capacitors C1 and C2 of the voltage doubler rectifier circuit 2 have a capacitance of C2≫C1. Assuming that C1 = C2, when the input signal stops at the power supply potential V _CC , both the charge stored in the capacitor C1 and the charge stored in the capacitor C2 affect the _OFF -delay time T _OFF , and the input signal is The off-delay time T _OFF is doubled compared to the case of stopping on the 0V side, and a large difference occurs in the off-delay time T _OFF depending on the stop level of the input signal.

[0007]

However, the conventional off-delay circuit 1 has the following disadvantages. That is, when the capacitance of the capacitor C2 is much larger than that of the capacitor C1, the response delay of the rising becomes large. When the capacitor C1 is made large, the input signal generating means needs to have a large driving capability. In addition, since the off-delay time is set by the time constant of the capacitance and the resistance value of the capacitor, the off-delay time varies due to manufacturing variations of the capacitor and the resistor, and it is difficult to set the off-delay time with high accuracy. In particular, when the off-delay time is set to be long, such a variation as an absolute value cannot be ignored (for example, when the off-delay time is set to 10 minutes, the variation of ± 20% is 2 minutes). Therefore, there is a problem in terms of reliability when the off-delay time is set long.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a highly accurate and fail-safe signal delay circuit that can obtain a stable delay time by using a serial memory. And

[0009]

Therefore, in the signal delay circuit according to the first aspect of the present invention, there is provided a clock signal generating means for generating a clock signal, and the clock signal generating means provided that an input signal is applied. A data output means for generating a frequency-divided output of the signal as a data output; and storing a predetermined bit of the data output of the data output means for each input of the clock signal of the clock signal generating means, and storing the predetermined bit for each data input. A serial memory that sequentially outputs data stored first, a detection unit that generates an output when an alternating signal is generated from the serial memory, and a logical sum of the input signal and an output signal of the detection unit. And OR means for generating a delayed output.

In this configuration, when an input signal is applied, the frequency output of the clock signal is input from the data output means to the serial memory as a data output. The serial memory stores input data every time a clock signal is input, and when a predetermined number of bits of data are stored and the memory capacity is saturated, the serial memory sequentially outputs the stored data at the next input of the next data. The detection means generates an output if an alternating signal is generated from the serial memory, and outputs the output to the OR means. The OR means generates an output simultaneously with the input of the input signal, and stops the output when the output signal from the detection means stops. As a result, the fall of the output is delayed from when the input signal stops until all the data in the serial memory is swept out, so that the circuit functions as an off-delay circuit.

[0011] In the invention according to the second aspect, the OR means is, specifically, a first photocoupler which performs a switching operation based on an input of an input signal, and a switching operation which is performed based on an output from the detection means. And the output terminals of the first and second photocouplers are connected in parallel to each other and connected to the delay output terminal.

With this configuration, the output is generated from the delay output terminal until the output of both the first and second photocouplers stops. In the signal delay circuit according to the third aspect of the present invention, a variable clock signal generating means for generating a clock signal and changing the frequency of the clock signal to a higher frequency than normal for a predetermined time when the input signal rises, Data output means for generating a frequency-divided output of the clock signal as a data output on the condition that the clock signal is applied; and storing a predetermined bit of the data output of the data output means for each input of the clock signal of the variable clock signal generation means. After storing a predetermined number of bits, a serial memory for sequentially outputting the data stored first for each data input, and a detecting means for generating a delayed output when an alternating signal is generated from the serial memory are provided.

In this configuration, when an input signal is applied, the frequency output of the clock signal is input from the data output means to the serial memory as a data output. The serial memory stores input data every time a clock signal is input, and when a predetermined number of bits of data are stored and the memory capacity is saturated, the serial memory sequentially outputs the stored data at the next input of the next data. The detecting means generates a delayed output if an alternating signal is generated from the serial memory. The variable clock signal generating means generates the frequency of the clock signal at a frequency higher than usual for a predetermined time when the input signal rises. For this reason, the time required for the serial memory to store the data of a predetermined bit is shortened, the time from when the input signal is applied to when the output of the detection means is generated is short, and the output from the detection means can be generated almost simultaneously with the input signal. It becomes possible. Therefore, the output of the detection means rises almost simultaneously with the input signal, and the fall of the output of the detection means is delayed until all the data in the serial memory is discharged after the input signal is stopped. Will work.

According to a fourth aspect of the present invention, the data output means includes a frequency dividing means for dividing a clock signal, and a logical product of a divided output of the frequency dividing circuit and an input signal to calculate a data output. And an AND means for generating Specifically, the AND means performs a switching operation on a voltage-doubled rectified signal obtained by voltage-double rectifying an input signal by the frequency-divided output of the frequency dividing means, as in the invention according to claim 5. A third photocoupler that converts the data into an alternating signal; and a fourth photocoupler that performs a switching operation by the alternating signal obtained by the switching operation of the third photocoupler to generate the data output as the alternating signal. You.

In this configuration, the data output is generated by the switching operation of the third and fourth photocouplers only when the frequency division output and the input signal are both input. Specifically, the detection means is configured to perform switching operation based on an alternating signal from the serial memorator, based on a fifth photocoupler, and an alternating output of the fifth photocoupler. And a capacitor for charging and discharging and outputting an alternating signal.

In this configuration, the serial memory is
Only when the alternating signal in which the low level occurs alternately is generated, the capacitor is normally charged and discharged, and the output is generated. According to a seventh aspect of the present invention, in the signal delay circuit of the first aspect, a logical AND means is provided in place of the logical OR means, and the output of the logical AND means is used as a delayed output.

In such a configuration, an output is generated from the AND means only when both the input signal and the signal of the detection means are being input. Therefore, the output from the AND means is delayed until the data in the serial memory is saturated and the output is generated from the detection means from the time when the input signal rises, and the output from the AND means is simultaneously delayed with the fall of the input signal. Will stop. As a result, the circuit functions as an on-delay circuit in which the delay time from the rise of the input signal to the generation of the output from the serial memory is set as the on-delay time.

[0018] Specifically, the logical product means is configured as follows.
And a sixth photocoupler that performs a switching operation based on an output from the detection means.
A seventh photocoupler that performs a switching operation based on a switching operation of the photocoupler to convert a voltage-doubled rectified signal obtained by voltage-double rectifying an input signal into an alternating signal, and delays the output of the seventh photocoupler. Was adopted.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a signal delay circuit having an off-delay function according to the present invention. In FIG. 1, an off-delay circuit 10 of the present embodiment is a signal generator 11 as a clock signal generating means for generating a clock signal CK at a constant cycle, and divides the frequency of the clock signal CK from the signal generator 11. Dividing circuit 1
AND which is a logical product means for calculating a logical product of the divided output of the frequency dividing circuit 12 and the input signal to generate a data output
A serial memory 14 which receives a data signal a of a D gate 13 and an AND gate 13 and stores the data every time the clock signal CK is input, and stores and holds a predetermined bit (N bit).
A detection circuit 15 as a detection means for detecting a memory output b from the serial memory 14; and a logical sum means for calculating a logical sum of an output signal c of the detection circuit 15 and an input signal to generate a delayed output d. And an OR gate 16. Here, the frequency dividing circuit 12 and the AND gate 1
3 together form data output means.

The serial memory 14 stores a data signal a
Are stored for N bits thereafter, and the stored data is sequentially output and the input data signal a is sequentially stored every time the clock signal CK is input. Next, the circuit operation of FIG. 1 will be described with reference to the time chart shown in FIG. FIG. 2 shows an example of the frequency dividing circuit 12 for dividing the frequency by two.

When the input signal rises, an output signal d is generated from the OR gate 16. After the rising of the input signal, the clock signal CK of the signal generator 11 is generated.
The frequency-divided output of the frequency １ ／ of the clock signal CK from the frequency divider 12 is input to the AND gate 13. By the input of the divided output, a data signal a, which is an alternating signal of "1" and "0", is inputted to the serial memory 14 in synchronization with the divided output from the AND gate 13 to which the input signal has already been inputted.
The serial memory 14 stores “1” and “0” data signals a that are input each time the clock signal CK is input.
Then, when N clock signals CK are inputted after the generation of the data signal a, N bits of data are stored in the serial memory 14 and the storage capacity is saturated. Thereafter, each time the clock signal CK is input, the input data signal a is sequentially stored, and at the same time, the data stored first is swept out as the data output b and input to the detection circuit 15. The detection circuit 15 outputs an output signal c to the OR gate 16 from the time when the data output b, which is an alternating signal from the serial memory 14, is input.

Thereafter, when the input signal falls, the data signal a from the AND gate 13 stops and the serial memory 14
Is fixed to the “0” side. After the serial memory 14 sequentially sweeps out the stored N-bit data by input of the clock signal CK, the output is fixed to the “0” side. Therefore, even if the input signal is stopped, the output signal c is generated from the detection circuit 15 and the delay signal d of the OR gate 16 is continuously generated until all the data stored in the serial memory 14 is output. The _OFF delay time T _OFF is a period of T _OFF in the figure from the stop of the operation until the output of the detection circuit 15 stops.

After the input signal stops, the serial memory 1
The off-delay time T _OFF , which is a delay time from the point of time 4 until the output of the alternating signal stops, is substantially equal to the product of the bit length of the serial memory 14 (N in the present embodiment) and the cycle of the clock signal CK. Therefore, the off-delay time T _OFF can be set freely by changing the bit length of the serial memory or the cycle of the clock signal CK.

Such an off-delay circuit is applicable to the following operation control in a mechanical system in which a drive system and a driven system are mechanically connected. For example, a drive system that is mechanically connected to the driven system is provided with a unit that detects the rotation speed of the drive system, and the rotation speed of the driven system follows the increase or decrease in the rotation speed of the drive system when connected. Shall change. In this case, assuming that the input signal of FIG. 1 is turned off when connected and turned on when not connected, and the signal generator is replaced with a drive system rotation speed detecting means, the drive system is turned off using the off-delay circuit of FIG. After the connection between the motor and the driven system, it is possible to generate a signal that gives an operation permission for a predetermined number of revolutions. Also, the input signal is turned on when the operation command is issued, and turned off when the command is not issued.
If such a signal is issued, it is possible to generate a signal that gives an operation permission for a predetermined number of revolutions after the operation non-command.

To make the off-delay circuit 10 shown in FIG. 1 fail-safe, at least the following conditions must be satisfied. a) No alternate signal is generated as the data signal a when there is no input signal. b) The alternation signal is not output from the memory due to the failure of the serial memory. FIG. 3 shows a specific circuit example in which the off-delay circuit of FIG. 1 is configured to have a fail-safe configuration.

In FIG. 3, in this embodiment, the input signal is converted into an alternating signal between the power supply potential V _CC and 0 V.
An input signal which is an alternating signal is applied to a base, a collector is connected to a power supply potential V _CC via a resistor R1, and an emitter is grounded. A collector output of the transistor Q1 is rectified and the rectified output is converted to a power supply potential V _{CC. A} voltage doubler rectifier circuit 21 that superimposes the output voltage on the _CC and outputs the rectified voltage is provided.

The AND gate 13 performs a switching operation by the frequency division output of the frequency dividing circuit 12 to perform the switching operation.
A photocoupler 13A as a third photocoupler for converting the rectified output of No. 1 into an alternating signal, and a fourth photo for generating a data signal a of the alternating signal by performing a switching operation by an alternating signal obtained by a switching operation of the photocoupler 13A. A photocoupler 13B is provided as a coupler.

The photocoupler 13A is composed of a light emitting diode PD1 whose anode is connected to the output terminal of the frequency dividing circuit 12 via a resistor R2 and whose cathode is grounded, and a phototransistor PT1 which receives light from the light emitting diode PD1. . The photocoupler 13B has an anode connected to the output terminal of the voltage doubler rectifier circuit 21 via a resistor R3 and a cathode connected to the collector of the phototransistor PT1 whose emitter is grounded.
And the collector is connected to the power supply potential V _CC and the emitter is
4 and a phototransistor PT2 that is grounded via the light emitting diode 4 and receives light from the light emitting diode PD2.

The detection circuit 15 includes a photocoupler 15A as a fifth photocoupler that performs a switching operation by a data signal b, which is an alternating signal from the serial memory 14,
A capacitor C11 for charging and discharging based on the alternating output from the photocoupler 15A. The photo coupler 15
A is a light emitting diode PD3 whose anode side is connected to the output terminal of the serial memory 14 and whose cathode side is grounded via a resistor R5, and whose collector is a power supply potential V _CC via a resistor R6.
And a phototransistor PT3 whose emitter is grounded and receives light from the light emitting diode PD3. The capacitor C11 has one electrode connected to the power supply potential V _CC via the resistors R7 and R6, and the other electrode connected to the power supply potential V _CC via the diode D11.

The OR gate 16 includes a photocoupler 16A that performs a switching operation based on the frequency divided output of the frequency dividing circuit 12;
A photocoupler 16B as a first photocoupler that performs a switching operation by a rectified output of the voltage doubler rectifier circuit 21 that is switched by the switching operation of the photocoupler 16A to be an alternating signal, and a second that performs a switching operation by an alternating signal of the detection circuit 15. And a photocoupler 16C as a photocoupler.

[0031] The photocoupler 16A is a light emitting diode connected to the power supply potential V _CC anode side via a resistor R8 cathode side is connected to the output of the frequency divider circuit 12 PD4
And a phototransistor PT4 that receives light from the light emitting diode PD4. The photocoupler 16B includes:
A light emitting diode PD5 the anode cathode side connected to the output terminal of the voltage doubler rectifier circuit 21 via a resistor R9 is connected to the collector of the phototransistor PT4 whose emitter is grounded, a collector resistor to the power source potential V _CC R10
And a phototransistor PT5 whose emitter is grounded and receives the light of the light emitting diode PD5. The photocoupler 16C has a resistor R on the anode side.
11, a light emitting diode P connected to the capacitor C11 of the detection circuit 15 and the cathode side connected to the power supply potential _Vcc.
And D6, consisting phototransistor PT6 Metropolitan the collector receives the light of the photo-transistor PT5 collector and emitter connected via a resistor R10 to the power supply potential V _CC in parallel is grounded light emitting diode PD6. Then, a delay output d is output using the intermediate point between the collectors of the phototransistors PT5 and PT6 and the resistor R10 as a delay output terminal.

Next, the operation will be described. An input signal, which is an alternating signal, is applied to the base of the transistor Q1 so that the power supply potential V
_It is converted into an alternating signal between _CC and 0V and is a voltage doubler rectifier circuit 2.
Input to 1 and rectified. Assuming that the rectified output is α, the output of V _CC + α is output from the voltage doubler rectifier 21 to the AND gate 13.
To the OR gate 16. The input signal input to the AND gate 13 is converted into an alternating signal by the switching operation of a photocoupler 13A that switches at the cycle of the divided signal of the frequency dividing circuit 12, and the alternating signal causes the photocoupler 13B to perform a switching operation. 13B
A data signal a is generated from the emitter side of the phototransistor PT2 and is input to the serial memory 14. The serial memory 14 sequentially stores this data signal a up to N bits for each input of the clock signal CK as described above,
Thereafter, every time the data signal a is input, the data stored in the earliest stored data is sequentially swept out, and the data output b of the alternating signal is output to the detection circuit
Enter 5

In the detection circuit 15, the photocoupler 15A performs a switching operation according to the data output b. When data output b is at H level, phototransistor PT3 is ON
Then, the capacitor C11 is charged, and when the data output b is at the L level, the phototransistor PT3 is turned off and the capacitor C11 is discharged. As described above, the charging and discharging of the capacitor C11 are repeatedly performed in accordance with the level of the data output b, and the detection output c of the alternating signal is generated and the OR gate 1
6 is input.

In the OR gate 16, the voltage doubler rectifier 21
Is converted into an alternating signal by the switching operation of the photocoupler 16A by the frequency division output of the frequency dividing circuit 12. This alternating signal causes the photocoupler 16B
Perform a switching operation, and a delayed output d of the alternating signal is generated. When the detection output c is input from the detection circuit 15,
An alternating delay output d is generated by the switching operation of the photocoupler 16C. Therefore, in the OR gate 16, when the input signal from the voltage doubler rectifier circuit 21 is input, a delay output d is generated. After the input signal stops, the delay output d is continuously held by the detection output c from the detection circuit 15, The process continues until the data output b from the serial memory 14 stops and the detection output c from the detection circuit 15 stops. Thus, an off-delay output can be obtained. still,
In the embodiment of FIG. 4, the off-delay output is an alternating signal.

The AND gate 13 shown in FIG. 3 operates when the input signal from the voltage doubler rectifier circuit 21 is not input, that is,
When the input signal is not applied to the transistor Q1, no output is generated from the photocoupler 13B, and the data signal a is not input to the serial memory 14. Further, the detection circuit 15 outputs the clock signal C from the serial memory 14.
It deals with a failure in which K is transmitted directly. That is,
When the clock signal CK is directly transmitted, the phototransistor PT3 of the photocoupler 15A performs a switching operation, but its ON time is short. Phototransistor PT
When the switch 3 is ON, the capacitor C11 is charged via the resistor R7, and when the phototransistor PT3 is turned OFF, the capacitor C11 discharges and energizes the light emitting diode PD6 of the photocoupler 16C. Therefore, the capacitor C
If the time constant of the clock signal CK is set so that the phototransistor PT3 cannot be charged during the ON time of the phototransistor PT3 when the clock signal CK is directly transmitted,
Is not directly generated from the detection circuit 15 even when is transmitted directly. On the other hand, when the negative signal of the clock signal CK is transmitted, the time during which the phototransistor PT3 of the photocoupler 15A is turned off becomes shorter. Therefore, the phototransistor PT3 should not be turned off within this time. That is, if the duty ratio of the clock signal CK is set smaller than the OFF response time of the phototransistor PT3, the photocoupler 15A does not perform the switching operation,
The detection circuit 15 does not generate an output.

If the frequency division ratio of the frequency dividing circuit is m and the bit length of the serial memory is n × m, the clock signal CK
M divided signals are stored in the serial memory for n / 2 (n is an even number). If the frequency division ratio m is set sufficiently large, the cycle of the m frequency-divided signal will be significantly larger than the cycle of the clock signal CK. In this case, the detection circuit 15
Is configured not to respond to short-period signals,
It is possible to cope with a failure in which the clock signal CK is directly transmitted regardless of the duty ratio of the clock signal CK.

FIG. 4 shows another embodiment of the off-delay circuit. Note that the same elements as those in FIG. Referring to FIG.
The delay circuit 30 omits the OR gate of FIG. 1 and provides a variable frequency signal generator 11 'as a variable clock signal generating means capable of changing the frequency of the clock signal CK as a signal generator, and detects the rising of the input signal. A rising detection circuit 31 is provided, and the output of the detection circuit 15 is used as a delayed output.

In such a configuration, when an input signal is applied, the rising detection circuit 31 detects this, and the rising detection signal is input to the frequency variable signal generator 11 '.
When the rising detection signal is input, the frequency variable signal generator 11 'receives the clock signal CK for a predetermined time from the input time.
Is a higher frequency than the normal clock frequency as shown in FIG. As a result, the time from when the input signal is applied to the time when the serial memory 14 is saturated is reduced, and the time until an output is generated from the detection circuit 15 based on the data output from the serial memory 14 is extremely short. . Accordingly, the output from the detection circuit 15 is generated immediately after the input signal is applied, and continues until all the data in the serial memory 14 is swept out after the input signal is stopped. ,
In the off-delay mode, the circuit in FIG. 5 is an off-delay circuit.

Next, FIG. 6 shows an embodiment of the on-delay circuit. Note that the same elements as those in FIG. 6, the on-delay circuit 40 according to the present embodiment includes an AND gate 16 in place of the OR gate 16 in FIG.
It is configured by providing a gate 41. In such a configuration, when an input signal is applied, as described with reference to FIG. 1, an output is generated from the detection circuit 15 after the serial memory 14 is saturated. The AND gate 41 does not generate an output until the serial memory 14 is saturated after the input signal is applied, and an output is generated when an output is generated from the detection circuit 15. The output is stopped immediately when the input signal is stopped. I do. Therefore, A
The output of the ND gate 41 is an on-delay output.

FIG. 7 shows a specific circuit example of the fail-safe AND gate 41. 7, an AND gate 41 includes a photocoupler 41A serving as a sixth photocoupler that performs a switching operation based on an output from the detection circuit 15, a switching operation based on the switching operation of the photocoupler 41A, and a voltage doubler rectifier circuit 21 that performs a switching operation based on the switching operation of the photocoupler 41A. And a photocoupler 41B as a seventh photocoupler for converting an output signal from the
Is configured to be a delayed output.

[0041] The photocoupler 41A is a light emitting diode cathode connected anode side via a resistor R11 to the output terminal of the detector circuit 15 is connected to the power supply potential V _CC PD7
And the emitter is connected to the power supply potential V _CC and the light emitting diode P
And a phototransistor PT7 that receives the light of D7. The photocoupler 41B has a resistor R1 on the anode side.
2, a light-emitting diode PD8 connected to the output terminal of the voltage doubler rectifier circuit 21 and a cathode connected to the collector of the phototransistor PT7, and a collector connected to the power supply potential V _CC.
And a phototransistor PT8 whose emitter is grounded via a resistor R13 and receives light from the light emitting diode PD8. Then, the emitter output of the phototransistor PT8 becomes a delay output.

In such a configuration, an alternating signal due to the voltage doubled rectification output is generated based on the switching operation of the photocoupler 41A only after an output is generated from the detection circuit 15, and a delayed output is generated by the switching operation of the photocoupler 41B.

[0043]

As described above, according to the first to sixth aspects of the present invention, a fail-safe off-delay having an excellent off-delay function without being affected by variations in circuit elements and the like. A circuit can be provided. Also,
According to the seventh and eighth aspects of the present invention, it is possible to provide a fail-safe on-delay circuit having an excellent on-delay function simply by replacing the logical sum means with the logical product means.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a signal delay circuit according to the present invention.

FIG. 2 is an operation time chart of the embodiment.

FIG. 3 is a specific circuit configuration diagram of FIG. 1;

FIG. 4 is a block diagram showing another embodiment.

FIG. 5 is a diagram illustrating the operation of the variable frequency signal generator according to the embodiment shown in FIG. 4;

FIG. 6 is a block diagram showing still another embodiment.

FIG. 7 is a specific circuit diagram of the AND gate of FIG. 6;

FIG. 8 is a circuit diagram of a conventional off-delay circuit.

FIG. 9 is an operation time chart of the circuit of FIG. 8;

[Explanation of symbols]

10, 30 Off-delay circuit 11 Signal generator 11 'Variable frequency signal generator 12 Divider circuit 13 AND gate 14 Serial memory 15 Detection circuit 16 OR gate 21 Voltage doubler rectifier circuit 31 Rise detection circuit 40 On-delay circuit 41 AND Gates 13A to 13C, 15A, 16A to 16C, 41A, 4
1B photo coupler

Claims (8)

[Claims] A clock signal generating means for generating a clock signal; a data output means for generating a frequency-divided output of the clock signal as a data output on condition that an input signal is applied; A serial memory that stores a predetermined bit of the data output of the data output means for each input of the clock signal and sequentially outputs the data stored first for each data input, and an alternating signal from the serial memory. A detecting means for generating an output when the signal is generated, and a logical sum means for calculating a logical sum of the input signal and an output signal of the detecting means to generate a delayed output, the serial being characterized by comprising: Signal delay circuit using memory. A second photo-coupler that performs a switching operation based on an input of an input signal; and a second photo-coupler that performs a switching operation based on an output from the detection means.
2. The signal delay circuit according to claim 1, further comprising a photocoupler, wherein the output terminals of the first photocoupler and the second photocoupler are connected in parallel to each other and connected to a delay output terminal. 3. A variable clock signal generating means for generating a clock signal and changing the frequency of the clock signal to a frequency higher than usual for a predetermined time when the input signal rises, and provided that the input signal is applied. Data output means for generating a frequency-divided output of a clock signal as a data output; and for each input of the clock signal of the variable clock signal generation means, storing a predetermined number of data outputs of the data output means and storing the predetermined bits of the data output. A serial memory for sequentially outputting data stored first for each time, and a detecting means for generating a delay output when an alternating signal is generated from the serial memory. Signal delay circuit. 4. The data output means includes: frequency dividing means for dividing a clock signal; and logical product means for calculating a logical product of a divided output of the frequency dividing circuit and an input signal to generate a data output. A signal delay circuit using the serial memory according to claim 1 or 3, comprising: 5. A third photocoupler for performing a switching operation to convert a voltage-doubled rectified signal obtained by voltage-double rectifying an input signal into a alternating signal by a frequency-divided output of the frequency-dividing means; 5. The serial memory according to claim 4, further comprising: a fourth photocoupler that performs a switching operation based on an alternating signal obtained by the switching operation of the third photocoupler to generate the data output as an alternating signal. Signal delay circuit. 6. A fifth photocoupler which performs a switching operation in response to an alternating signal from the serial memorator, a capacitor which charges and discharges based on an alternating output of the fifth photocoupler and outputs an alternating signal. A signal delay circuit using the serial memory according to claim 1 or 3, comprising: 7. A signal delay circuit using a serial memory according to claim 1, wherein a logical product means is provided in place of said logical sum means, and an output of said logical product means is a delay output. 8. The logical product means includes: a sixth photocoupler that performs a switching operation based on an output from the detection means; and a switching operation based on a switching operation of the sixth photocoupler to perform voltage doubler rectification on an input signal. 8. A signal delay using a serial memory according to claim 7, further comprising a seventh photocoupler for converting the voltage doubled rectified signal obtained by the conversion into an alternating signal, wherein the output of the seventh photocoupler is used as a delayed output. circuit.