JPH11122046A - Analog multiplication circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an analog multiplication circuit for a high frequency with less carrier signal leakage. SOLUTION: For this analog multiplication circuit, a gilbert cell type multiplication circuit is constituted of a first differential circuit by a pair of transistors 605 and 606, a second differential circuit by a pair of transistors 601 and 602 and a third differential circuit by a pair of transistors 603 and 604. Then, to a load resistor 627 of the transistor 601 and a load resistor 628 of the transistor 604, carrier signal overshoot compensation means 101 and 102 are respectively connected in parallel. Since the carrier signal overshoot compensation means 101 and 102 are operated so as to reduce an overshoot current generated, when the transistors 601 and 603 and the transistors 602 and 604 are turned on, flowing to the respective load resistors 627 and 628, the overshoot of carrier signals is reduced, and the leakage to an output terminal of the carrier signals is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog multiplying circuit for a Gilbert cell type multiplying circuit having a function of multiplying a high-frequency analog signal to reduce carrier leakage and a double wave.

[0002]

2. Description of the Related Art A Gilbert cell type multiplier has been widely known as an analog multiplier. For example, Japanese Patent Publication No. 48-20932 discloses a configuration of an analog multiplier using a Gilbert cell type multiplier.

Such a multiplication circuit multiplies a first high-frequency signal and a second high-frequency signal in a balanced form, and outputs the result of multiplication of the two high-frequency signals to an output terminal in a balanced form. Generally, this analog multiplication circuit is often used for a modulator, and a second high-frequency signal (modulated signal = carrier signal) is modulated by a first high-frequency signal (modulated signal = baseband signal or the like) to be balanced. I have a modulated signal.

A Gilbert cell type analog multiplying circuit used in a conventional high frequency modulator will be specifically described with reference to the drawings.

FIG. 8 is a circuit diagram of a conventional analog multiplication circuit.

In the figure, six transistors 601
To 606 constitute three differential amplifier circuits.

That is, the first differential amplifier includes a resistor 61
5 and 616 via two transistors 605 and 606
Are connected to each other, the connection point of the resistors 615 and 616 is grounded through a common constant current source 631, and the input terminal 6
A first high frequency signal (BB signal) in a balanced form received between 21 and 622 is applied to the bases of transistors 605 and 606.

In the second differential amplifier, the emitters of two transistors 601 and 602 are connected in common, the connection point is connected to the collector of transistor 605, and the balanced type received between input terminals 623 and 624 is connected. A second high-frequency signal (carrier signal) is applied to the bases of the transistors 601 and 602.

The third differential amplifier connects the emitters of the two transistors 603 and 604 in common, connects the connection point to the collector of the transistor 606, and applies the second high-frequency signal to the bases of the transistors 603 and 604. ing.

The transistors (transistors 601 and 60) on one side of the second and third differential amplifier circuits are used.
The collectors of 3) are commonly connected, and the connection point 62
5 is connected to a power supply 620 via a resistor 627.

The other transistors (transistors 602 and 604) of the second and third differential amplifier circuits
Are connected in common, and a connection point 626 is connected to a power supply 620 and a resistor 628.

The connection points 625 and 626 are connected to the second
Is an output terminal from which a balanced modulated signal obtained by modulating the high-frequency signal by the first high-frequency signal is generated. A predetermined bias voltage is supplied to each of the input terminals 621 to 624 from a bias supply circuit (not shown).

Next, the operation of the analog multiplication circuit shown in FIG. 8 will be described.

A first high-frequency signal is input between input terminals 621 and 622. Here, when the potential of the input terminal 621 is higher than that of the input terminal 622,
05 turns on and the transistor 606 turns off.
In this case, when the second high-frequency signal input between input terminals 623 and 624 has a positive phase (when the voltage of input terminal 623 is higher than the voltage of input terminal 624), transistors 601 and 604 are turned on. Since the collector current I605 of the transistor 605 flows from the power supply 620 through the transistor 601, the output terminal 625 becomes low level (low voltage).

On the other hand, when the second high-frequency signal has the opposite phase, the transistors 602 and 603 are turned on and the power supply 62
The collector current I605 flows from 0 through the transistors 602 and 605, and the output terminal 625 becomes high level (power supply voltage).

However, when the difference voltage of the first high-frequency signal is small, the current flowing through the transistor 605 decreases and the current also flows through the transistor 606, and thus flows through the transistors 603 and 606, and the output terminal 6
25, the voltage difference between the high level and the low level becomes small.

When the first high-frequency signal has a voltage of 0, the internal resistances of the transistors 605 and 606 become substantially equal and the same current flows. The current flowing through the transistor 605 is equal to the current flowing through the transistors 603 and 606 during the reverse phase, and the first high-frequency signal is not output to the output terminal 625.

Therefore, when either one of the first and second high-frequency signals is at zero voltage, a double balanced modulator is constructed such that the output of the output terminal 625 always becomes zero. The operation is the same as that described above except that a signal having a phase opposite to that of 625 is output to the output terminal 626, and a description thereof will be omitted.

Next, the input terminal 6 of the analog multiplication circuit
23 and 624, an ideal rectangle having a repetition period Tr is input as a second high-frequency signal (hereinafter, referred to as a carrier signal), and between the input terminals 621 and 622, for the sake of simplicity, The case where a DC potential of 0 V is applied will be described below.

FIG. 9 shows the transistor 6 under the above conditions.
FIG. 13 is a signal waveform diagram showing time changes of the collector current and the power supply current I627 of FIG.

In FIG. 9, in an ideal state, the collector current I601 of the transistor 601 and the collector current I603 of the transistor 603 have an antiphase relationship. The current I27 flowing through the resistor 627 is I601
And I603, the current I62 if the constants of the constituent elements forming a pair in the analog multiplier are balanced.
7 is a constant current. As a result, this analog multiplying circuit does not cause carrier signal leakage at output terminals 625 and 626.

[0022]

The conventional analog multiplying circuit described above ideally has no carrier leak as described above.

However, when the frequency of the carrier signal becomes high, especially when the frequency becomes a microwave signal of 1 GHz or more, variations in the transistors 601 to 606 are apt to occur, and the parasitic wiring of the wiring to each electrode connecting portion of the transistors 601 to 606 is generated. The balance of the capacity and the like will be lost.

Further, the imbalance of the high frequency signals at the input terminals 623 and 624 becomes large, causing the carrier signals to overshoot at the currents I601 and I603, and as a result, the carrier signals leak at the output terminals 625 (626). Will be.

FIG. 10 is a signal waveform diagram obtained by using the analog waveform simulation program using predetermined constants for each component of the analog multiplying circuit shown in FIG.

Specifically, the cutoff frequency and the maximum oscillation frequency of the silicon bipolar transistors 601 to 606 are set to 16 GHz, the rated collector current is set to 5.3 mA,
The constant current source 631 uses a constant current source that passes a current of 8 mA (I605 + I606). Also, resistors 627 and 6
28 uses a resistor of 200 ohms, resistors 615 and 616 use a resistor of 60 ohms, and 0V is applied between input terminals 621 and 622.
And a frequency 2 between the input terminals 623 and 624.
A second high frequency signal of GHz (cycle Tr = 500 ps) is applied.

As a result, a current I627 that is not a constant value is generated in the resistor 627. The carrier signal leak due to the current I628 is -47.0d at the output terminal 625.
Bm. If this analog multiplier is used as a modulator with the output level set to -20 dBm, D / U = 27 dB with carrier leak and an amplitude error of 0.4
There is a problem that an error of 2.6 ° is generated in the modulated wave as a dB and phase error, thereby deteriorating modulation characteristics.

As described above, the purpose of the analog multiplying circuit of the present invention is to improve the modulation characteristics by reducing carrier leakage when a modulator is configured by inputting a high-frequency carrier signal such as a microwave band. It is an object of the present invention to provide a configuration capable of performing the above.

[0029]

To solve the above-mentioned problems, an analog multiplication circuit according to the present invention is an analog multiplication circuit using a Gilbert cell type multiplication circuit having a differential circuit composed of a plurality of transistor pairs. In the circuit, a carrier signal overshoot compensating means for bypassing an overshoot current flowing through a load resistor of the multiplier circuit when a carrier signal is input is provided in parallel with the load resistor.

Further, the carrier signal overshoot compensating means has a switching means for turning on and off the connection of a grounded capacitor in synchronization with the input of the carrier signal.

Further, the switching means is provided at both ends of the capacitor, and is switched based on a differential input of the carrier signal.

Further, the carrier signal overshoot compensating horn is characterized in that a capacitor is connected to an output of a differential circuit connected to an output terminal.

[0033]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the analog multiplication circuit of the present invention.

This drawing is different from the conventional analog multiplying circuit shown in FIG. 8 in that carrier signal overshoot compensating means 101 and 102 are provided in parallel with load resistances 627 and 628 for passing bypass currents of respective load resistances. 8 is the same as that of FIG. Therefore, the description of the configuration equivalent to the conventional one is omitted.

As described above, the leakage of the carrier signal at the output terminal is caused by the overshoot of the carrier signals of the currents I601 and I603. For this reason,
The carrier signal overshoot compensating means 101 and 102 provided in the present invention are connected in parallel with the load resistors 627 and 628, respectively, and operate to reduce the overshoot current flowing through the load resistors 627 and 628. As a result, overshoot of the carrier signal can be reduced, and leakage of the carrier signal to the output terminal can be significantly reduced.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention including a specific configuration of the carrier signal overshoot compensating means 101 and 102 will be described below with reference to the drawings.

FIG. 2 is a circuit diagram showing a first embodiment of the analog multiplication circuit of the present invention.

In FIG. 2, 621 and 622 are baseband input terminals, 623 and 624 are carrier input terminals, 6
25 and 626 are output terminals. Transistors 601,
602, 603, and 604 are bi-differential transistors whose emitters are commonly connected, 605 is a transistor connected by the emitter and collector of the commonly connected transistors 601, 602, and 606 is an emitter of the commonly connected transistors 603 and 604. These are transistors connected by a collector.

The resistors 627 and 628 are load resistors and one side is connected to the power supply 620, and the other side is connected to the collectors of the commonly connected transistors 601 and 603 and the collectors of the commonly connected transistors 602 and 604, respectively. I have.

The resistors 615 and 616 are negative feedback resistors for determining the gain, 620 is a power supply terminal, and 631 is a constant current source.

Here, the carrier signal overshoot compensating means 101 described with reference to FIG.
1 and a current bypass circuit 202.

The current bypass circuit 201 is a circuit for passing a bypass current of the resistor 627 when the transistor 601 is turned on.
2 are formed. Also, the current bypass circuit 202
Is a circuit for flowing a bypass current of the resistor 627 when the transistor 603 is turned on.
4. The capacitor 15 is formed.

Since the carrier signal overshoot occurs even when the transistors 602 and 604 are on, the carrier signal overshoot compensating means 102 is required to compensate for this. In this case, the current shown in FIG. Bypass circuit 201 and current bypass circuit 202
Is connected in parallel to the resistor 628. Therefore, the description is omitted because the configuration can be easily obtained from FIG.

Further, carrier input terminals 623 and 624
The circuit for providing a DC potential to the base of the base band input terminals 621 and 622, the bases of the transistors 10, 11, 13 and 14, and the DC cut capacitor are not shown in the drawing.

The operation of the above embodiment will be described with reference to FIG.

For simplicity, transistors 605 and 606
The voltage between bases (base band voltage) is set to 0.
At this time, even if a carrier signal is input, the amplitude of the output signal is ideally zero.

When the carrier signal input to the terminal 623 changes from a low level to a high level, the transistor 601 turns on and a collector current flows. This collector current causes ringing due to the parasitic capacitance and the parasitic inductance of the carrier signal particularly at a high frequency such as the quasi-microwave band.

For example, FIG. 3 shows the collector current (I6
01). As shown in this figure, when the collector current is the frequency f of the carrier signal (Tr = 1 / 2πf), an overshoot occurs every period Tr. Therefore, the potential of the terminal 625 determined by the collector current and the load resistance 627 also causes an overshoot.

However, since the transistor 11 is turned on at the same time when the transistor 601 is turned on, the capacitor 1 is turned on.
2 is discharged.

FIG. 4 is a diagram showing the characteristics of the discharge current versus time. In this figure, since the current of the overshoot is discharged, it does not pass through the load resistor 627 but flows through the transistor 11.

FIG. 5 is a diagram showing characteristics of current flowing through the resistor 627 versus time.

As a result, it is shown that the current flowing through the resistor 627 shown in FIG. 5 has no overshoot included in the current shown in FIG. 3 and the overshoot current is completely compensated. Therefore, the current flowing through the resistor 627 does not cause overshoot, and the potential of the terminal 625 does not cause overshoot.

Next, when 623 changes from high to low and 624 changes from low to high, the transistor 11 is turned off but the transistor 604 is turned on, and electric charge is stored in the capacitor 15 through the power supply.

Since the same applies to the operation of the transistor 603, a voltage waveform without overshoot is output to the terminal 625 after all.

As described above, since the capacitors 12 and 15 compensate the overshoot current by discharging the stored charge, it is necessary to determine an appropriate capacitor constant.

FIG. 6 shows only the overshoot current among the collector currents shown in FIG.

In this figure, the frequency of the carrier signal is represented by f
If the charge amount of the overshoot current per cycle is approximated by a triangle and the flowing time is approximated by １ ／ of the cycle of the carrier signal, the following equation is obtained: 1/2 ・ ff ・ I = I / 8f (1)

Where I is the peak value of the overshoot current.

On the other hand, assuming that the capacitance value of the capacitor 12 is C, the amount of electric charge charged to this capacitor is
Where V is the power supply voltage and V _BE is the voltage between the base and emitter of the transistor 10, and (V−V _BE ) · C (2)

Since equations (1) and (2) are equal, C = I / 8f (V-V _BE ) (3).

Although the capacity of the capacitor 12 is determined as described above, the capacities of other capacitors can be determined in the same manner.

In the first embodiment described above, the transistors 10, 11, 13, and 14 are used.
It is not limited to transistors. For example, transistors 10, 11, 13, and 14 are analog switches, and FETs are
Switch means such as a switch can provide the same effect.

Further, in the above-described embodiment, the current bypass circuit in which the carrier signal overshoot compensating means 101 and 102 are constituted by a plurality of transistors and capacitors is used. However, when the carrier frequency is not as high as in the microwave band, In addition, overshoot current can be compensated without a current bypass means for switching a capacitor by a transistor.

FIG. 7 shows a second embodiment of the present invention in which the carrier signal overshoot compensating means is realized by using only a capacitor.

FIG. 7 shows a Gilbert cell type analog multiplier in which capacitors 21 to 24 are added between the collectors of transistors 601 to 604 and ground as a circuit for passing a bypass current.

Next, the operation of the second embodiment will be described.

For simplicity, transistors 605 and 606
The voltage between bases (base band voltage) is set to 0.
At this time, even if a carrier signal is input, the output signal ideally has an amplitude of 0. Now, when a signal input to the input terminal 623 changes from low to high, the transistor 601 is turned on and a collector current flows. At this time, the potential of the output terminal 625 tends to decrease due to the overshoot current. However, when the potential drops, the electric charges stored in the capacitors 21 and 23 are discharged, so that the amount of overshoot current flowing through the resistor 627 decreases. Therefore, the potential overshoot due to the overshoot current is reduced.

In this case, the capacitance of the capacitor can be obtained by the above equation (3) when no voltage V _BE exists.

Since the same operation is performed for the transistor 603, a carrier leak component and a second harmonic component appearing at the output terminal 625 can be reduced.

[0071]

As described above, in the embodiment of the present invention, the carrier signal overshoot compensating means is provided so that the overshoot current does not flow through the load resistance. The terminal voltage waveform does not overshoot. Therefore, by preventing generation of unnecessary signals of the carrier frequency component due to the overshoot, the unbalance of the input two-phase carrier signal, and the unbalance of the transistor performance, it is possible to suppress the occurrence of the carrier leak. Further, the generation of the second harmonic due to the overshoot itself can be suppressed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of an analog multiplication circuit of the present invention.

FIG. 2 is a circuit diagram of a first embodiment of the analog multiplication circuit of the present invention.

FIG. 3 is a diagram showing a time characteristic of the collector current of FIG. 2;

FIG. 4 is a diagram showing a time characteristic of the discharge current of FIG. 2;

FIG. 5 is a diagram showing a time characteristic of a current flowing through a resistor 627 in FIG. 2;

FIG. 6 is a diagram showing an overshoot current versus time characteristic of FIG. 2;

FIG. 7 is a circuit diagram of a second embodiment of the analog multiplication circuit of the present invention.

FIG. 8 is a circuit diagram of a conventional analog multiplication circuit.

9 is a diagram showing a current waveform of each part in FIG.

FIG. 10 is a diagram showing a simulated current waveform of each part in FIG. 8;

[Explanation of symbols]

10, 11, 13, 14 Transistor 12, 15, 21 to 24 Capacitor 101, 102 Carrier signal overshoot compensation means 201, 202 Current bypass circuit 601 to 606 Transistor 615, 616 Resistance 620 Power supply 621, 622 Input terminal (BB signal) 623,624 Input terminal (carrier signal) 625,626 Output terminal 627,628 Resistance 631 Current source

Claims (7)

[Claims] 1. An analog multiplication circuit using a Gilbert cell type multiplication circuit having a differential circuit composed of a plurality of transistor pairs, wherein when a carrier signal is input, an overcurrent flowing through a load resistance of the multiplication circuit is provided. An analog multiplying circuit, wherein a carrier signal overshoot compensating means for bypassing a shoot current is provided in parallel with the load resistor. 2. An analog multiplying circuit according to claim 1, wherein said carrier signal overshoot compensating means has a switching means for turning on / off a connection of a grounded capacitor in synchronization with input of said carrier signal. . 3. The analog multiplication circuit according to claim 2, wherein said switching means is provided at both ends of said capacitor, and is switched based on a differential input of said carrier signal. 4. The analog multiplication circuit according to claim 1, wherein said carrier signal overshoot compensation means horn connects a capacitor to an output of a differential circuit connected to an output terminal. 5. The analog multiplication circuit according to claim 1, wherein the frequency of the carrier signal is a high frequency signal in a microwave band. 6. A first input terminal for receiving a first high-frequency signal between two terminals, a second input terminal for receiving a second high-frequency signal between the two terminals, and the first and the second terminals. An output terminal for generating a multiplied signal obtained by multiplying the two high frequency signals between the two terminals, each base being connected to one of the first input terminals, and each emitter being supplied from a common constant current source And a first differential circuit including first and second transistor circuits respectively receiving a current supplied from a collector of the first transistor circuit and a collector connected to one of the output terminals. And a fourth transistor having a third transistor and an emitter receiving current supply from the collector of the first transistor circuit and having a collector connected to another one of the output terminals. A second differential circuit in which each of the bases of the third and fourth transistors is respectively connected to one of the second input terminals; an emitter receiving current from a collector of the second transistor circuit; Fifth, a collector is connected to one of the output terminals, respectively.
And a sixth transistor whose emitter receives current supply from the collector of the second transistor circuit and whose collector is connected to another one of the output terminals, the bases of the fifth and sixth transistors. And a third differential circuit respectively connected to one of the second output terminals. A Gilbert cell type analog multiplier circuit comprising: a first transistor connected to a collector of the third transistor circuit;
A first carrier signal overshoot compensating means for bypassing an overshoot current flowing through the first load resistance in parallel with the load resistance of the second, and a second carrier signal connected to a collector of the sixth transistor circuit.
And a second carrier signal overshoot compensating means for bypassing an overshoot current flowing through said second load resistor in parallel with said load resistor. 7. The apparatus according to claim 1, wherein the first and second carrier signal overshoot compensating means include a switching means for turning on and off a connection of a grounded capacitor in synchronization with the input of the carrier signal. 7. The analog multiplying circuit according to 6.