JPH11120123A - Data transfering device by bus control - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently perform data transfer through a common bus by adjusting the transfer capability of the bus in each DMAC. SOLUTION: This device consists of a bus right acquisition request minimum time setting register 6, a DMA transfer time setting register 7, counters 8 and 9, a HOLD request mask 10, a flip-flop circuit 11 and an AND gate 12. When data transfer performed by using a common bus, data transfer is performed by bus control which preliminarily sends a bus right acquisition request signal HOLD to a bus controller that is connected to the common bus and starts the data transfer after receiving a bus use permission signal HOLDACK from the bus controller. The register 7 sets DMA transfer time, and the register 6 sets the minimum time which makes the next bus right acquisition request after releasing a bus right. As a result, it is possible to adjust transfer capability of the bus in each DMAC.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device based on bus control, and more particularly, to a data transfer device based on bus control capable of adjusting the amount of data transferred by DMA transfer according to the bus usage.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram showing a conventional data transfer device. The illustrated data transfer device has a common bus 1, a CPU 2, a bus controller 3, and direct memory access controllers (hereinafter, referred to as "DMAC") 5, 6. These components are a printed wired circuit board (Printed Wired Circuit). Bord: "PWC
B ”. ) And are unitized. Such a configuration is also called a CPU-bus unit.
Under the control of the bus controller 3, the CPU 2, the DMAC 5, and the DMAC 6 acquire the right to use the bus and become the bus masters. Hereinafter, the bus master is a DMAC5, a CPU
The operation when rotating in the order of 2, DMAC 6 will be described.

[0003] From the DMAC 5 to the bus controller 3,
The bus right acquisition request signal HOLD is transmitted (FIG. 2
(3)). The HOLD is sent from the bus controller 3 to the CPU 2 (FIG. 2 (1)). The CPU 2 sends a bus use permission signal HOLDACK to the bus controller 3 (FIG. 2 (2)).

From the bus controller 3 to the DMAC 5,
HOLDACK is sent (FIG. 2 (4)), and as a result, D
MAC5 becomes a bus master and performs DMA transfer only for T2. Next, the CPU 2 becomes a bus master and performs necessary processing. In the meantime, the DMAC 5 gives the bus controller 3
The HOLD is continuously transmitted (FIG. 2 (3)). The bus right acquisition request signal is masked for the time T1 and transmitted.

[0005] From the DMAC 6 to the bus controller 3,
HOLD is sent (FIG. 2 (5)). The HOLD is sent from the bus controller 3 to the CPU (FIG. 2 (1)). HOLDACK from CPU 2 to bus controller 3
(FIG. 2 (2)). As a result, the DMAC 6 becomes the bus master and performs the DMA transfer only for T3.

A bus right acquisition request signal HOLD is sent from the bus controller 3 to the CPU 2 (FIG. 2 (1)).
HOLDACK is transmitted (FIG. 2 (2)), and HOLDACK is transmitted from the bus controller 3 to the DMAC 5 (FIG. 2).
(4)) Then, DMAC5 becomes the second bus master and D
Perform MA transfer.

[0007]

As described above, such a conventional device has a CPU 2 and a DMAC on a PWCB.
The operation status of the data transfer device in which 5 and 6 coexist depends on the unique values of the respective hardware and firmware. For example, the time until the DMAC generates the HOLD output again (T1 in FIG. 2) and the time during which the DMAC operates as a bus master (T2 and T3 in FIG. 2) have the respective hardware and firmware as described above. Depends on eigenvalues. Therefore, once the hardware design is completed, in order to change the processing capacity of the hardware or the firmware, it is necessary to improve the processing capacity in the firmware and redesign the hardware.

In the conventional bus control, a priority is given to a DMAC which is a bus master, and the order in which DMAs are executed has been changed. In the prior art, it is possible to improve the processing capability of the data transfer device by fixing or arbitrarily assigning the priority.
The MA transfer time is determined in accordance with the unique value of the hardware or firmware by the DMAC that is the bus master (for example, the DMAC does not stop until all data is transferred,
Or the data is divided and transferred in a certain amount), so that even the bus controller 3 cannot control the bus until the operation of another DMAC is completed.

Further, since all the bus control logics are performed only by hardware, it has been impossible to externally change the bus control settings. The present invention solves the problems of the prior art described above, and determines the maximum data transfer time that can be performed by one bus use permission and the minimum time until the next bus right acquisition request after data transfer, by using a bus right acquisition request signal. An object of the present invention is to enable data transfer via a common bus so that the data can be changed for each DMAC to be transmitted.

[0010]

FIG. 3 is a diagram for explaining the principle of the present invention. This shows a state in which a certain DMAC outputs a bus right acquisition request signal HOLD, and the bus controller returns a bus use permission signal HOLDACK in response to the signal. In the figure, (A) shows the DMA transfer time during which the DMAC acquires the bus use right and can execute the DMA transfer, and (B) shows the time until the bus right acquisition request signal is output again after the end of the DMA transfer. is there.

According to the present invention, the DMA transfer time (A)
It can be changed arbitrarily for each C, and time (B)
Is the minimum time during which the bus right acquisition request can be output again after the DMA transfer, and this minimum time can be arbitrarily changed for each DMAC. Hereinafter, the minimum time (B) is referred to as a bus right acquisition request minimum time. The time (A),
In order to make (B) adjustable, the present invention has the following configuration.

According to the first aspect of the present invention, a central processing unit (2) or a direct memory access controller DMAC (5, 6) connected to a common bus (1) transfers data using the common bus (1). Is performed, a bus right acquisition request signal HOLD is sent in advance to the bus controller (3) connected to the common bus (1), and after receiving the bus use permission signal HOLDACK from the bus controller (3), In the data transfer device by bus control for starting transfer, the central processing unit (2) or the direct memory access controller DMAC (5, 6)
Is a DMA transfer time setting means (set in a register such as a basic register (DBRR)) for setting a maximum data transfer time which can be performed by one bus use permission. Bus right acquisition request minimum time setting means (set in a register such as a basic register (DBRR)) for setting the minimum time until a bus right acquisition request, and the DMA transfer time setting means and the bus right acquisition request minimum time setting means And a setting value changing means for changing the set value. This allows
By adjusting the transfer capacity of the bus for each DMAC, C
An appropriate amount of bus transfer without affecting the PU processing can be enabled.

According to a second aspect of the present invention, there is provided the data transfer device by bus control according to the first aspect, wherein the DM
The A transfer time setting means sets the number of bus cycles (the number of bus cycles) corresponding to the data transfer time. Thus, the DMA transfer time can be set in accordance with the data transfer cycle. According to a third aspect of the present invention, in the data transfer device based on the bus control according to the first aspect, the bus right acquisition request minimum time setting means sets the number of clocks of the central processing unit corresponding to the minimum time.
(HOLD wait value). As a result, it is possible to finely set the minimum bus request acquisition time.

According to a fourth aspect of the present invention, in the bus-controlled data transfer device according to any one of the first to third aspects, the setting value changing means is firmware of a central processing unit. Accordingly, the setting can be changed easily and easily. According to a fifth aspect of the present invention, in the data transfer device under bus control according to any one of the first to third aspects, the setting value changing means receives an external change instruction directly via a dedicated line. DMA transfer time setting means and the bus right acquisition request minimum time setting means are transmitted. This allows
The condition of the common bus is measured externally, and the setting can be easily changed from the outside based on the result.

According to a sixth aspect of the present invention, in the data transfer device under bus control according to any one of the first to third aspects, the setting value changing means sends a change instruction from outside via a common bus. The data is transmitted to the DMA transfer time setting means and the bus right acquisition request minimum time setting means. This makes it possible to externally measure the status of the common bus and change the setting easily from the outside based on the result.

According to a seventh aspect of the present invention, in the data transfer apparatus based on the bus control according to any one of the first to third aspects, the setting value changing means dynamically changes based on a use state of a common bus. , The setting value is changed. This allows the central processing unit or the OS to automatically change the setting by giving a processing capability parameter from the outside.

According to an eighth aspect of the present invention, in the data transfer apparatus according to any one of the first to eighth aspects, the DMA transfer time setting means and the bus right acquisition request minimum time setting means each include: It has a register provided inside or outside the direct memory access controller DMAC, and sets the DMA transfer time and the minimum bus request acquisition time in the register. Since the setting is made in the register, the setting can be made easily and easily. Further, since the register may be provided anywhere, the degree of freedom in design increases.

According to a ninth aspect of the present invention, in the data transfer device by bus control according to any one of the first to eighth aspects, the bus right acquisition request minimum time setting means includes:
Bus right acquisition request signal HOLD or bus use permission signal HO
It is characterized in that the lapse of time is measured from the time when the LDACK is turned off. As a result, the minimum time for a bus right acquisition request can be reliably set.

According to a tenth aspect of the present invention, in the direct memory access controller DMAC, there is provided a bus right acquisition request signal generating means for obtaining a bus right, and the bus right acquisition request signal generating means is provided with a DMA transfer time. Setting means and bus right acquisition request minimum time setting means;
The MA transfer time setting means sets the maximum data transfer time which can be performed by one bus use permission. The bus right acquisition request minimum time setting means sets the next bus right after the data transfer performed with the bus use permission. A direct memory access controller DMAC which sets a minimum time until an acquisition request. This claim is directed to a direct memory access controller DMAC used in the data transfer of claims 1 to 9.

[0020]

FIG. 4 is a block diagram showing the configuration of the present invention based on the principle of FIG. The illustrated configuration is provided in, for example, a direct memory access controller DMAC, and sets a minimum time until a next bus right acquisition request is set after a data transfer performed with a bus use permission. Register 6, DMA transfer time setting register 7 for setting the maximum data transfer time that can be performed by permitting one bus use, counters 8, 9HO
An LD request mask 10, a flip-flop circuit 11, and an AND gate 12 are provided. The values of the bus right acquisition request minimum time setting register 6 and the DMA transfer time setting register 7 are set and changed by a common bus or a dedicated line (not shown). The frequency of the setting is arbitrary, for example, DMA
It is assumed that C becomes a bus master. Also, register 6
And 7 may be provided outside the DMAC instead of inside the DMAC.

The counter 8 counts the number of clocks of a CPU (not shown), and when the count reaches the setting value (HOLD wait value) of the bus right acquisition request minimum time setting register 6, the counter 8 goes to H level.
A high level signal is output to the OLD request mask 10. The counter 8 detects the end (negation) of the bus right acquisition request signal HOLD or the bus use permission signal HOLDACK, and the value is cleared by the detection signal. HO
The LD request mask 10 receives the output of the counter 8 and, when the output of the counter 8 is a low-level signal, inhibits the continuous output of the bus right acquisition request signal HOLD after the DMA transfer. A signal for closing the gate of the AND gate 12 is applied to the AND gate 12 for a certain period.

On the other hand, the counter 9 counts the number of ready signals (RDY signal) indicating the end of the bus cycle or the number of DADS signals indicating the start of the bus cycle, and sets the value of the DMA transfer time setting register 7 (bus cycle value). , A high-level signal is output, and the flip-flop circuit 11
Is applied to the reset terminal R. This counter 9 receives a bus right acquisition request signal HOLD or a bus use permission signal HOL.
The start (assertion) of DACK is detected, and the value is cleared by the detection signal. Flip-flop circuit 1
No. 1 set terminal S has a HOLD ON condition (D
MAC sends at least HOLD signal and HOLDA
CK signal is applied to the set terminal. The output signal of the HOLD request mask 10 and the output signal of the flip-flop circuit 11 are ANDed by the AND gate 12 and output as a bus right acquisition request signal HOLD (when the AND gate 12 is open, the flip-flop circuit 11 Is output as the bus right acquisition request signal HOLD.)

Next, the operation of the configuration shown in FIG. 1 will be described.
Initially, the value of the counter 8 is cleared by the negation of the bus right acquisition request signal HOLD or the bus use permission signal HOLDACK.
When transmitting D, the signal is normally a high level signal.
A high level signal is applied to the LD request mask 10, and the gate of the AND gate 12 is open. The counter 9 is also reset at the same time as the flip-flop circuit 11, and its output is a low-level signal, and does not output a reset signal to the flip-flop circuit 11.

On the other hand, the flip-flop circuit 11
The high level signal of the flip-flop circuit 11 is set by the LD ON condition signal and the AND gate 12
Is applied to Since the AND gate 12 is opened by the signal of the HOLD request mask 10 as described above, the high level signal of the flip-flop circuit 11 becomes the output of the AND gate 12 as it is. This high level signal is sent to the bus controller as the bus right acquisition request signal HOLD.

Thereafter, when the counter 9 counts the ready signal and reaches the value (bus cycle value) of the DMA transfer time setting register 7, the counter 9 outputs a high-level signal. This high level signal is applied to the reset terminal R of the flip-flop circuit 11 to reset the flip-flop circuit 11. As a result, the bus right acquisition request signal HOLD becomes a low level signal, and the transmission of the bus right acquisition request signal HOLD to the bus controller is stopped. At this time, the bus acquisition request signal HOLD ends, and the counter 6 is cleared by the output of the circuit that detects the end.

Then, as a result of the counter 6 being cleared,
Its output is a low level signal. Thereafter, the counter 6 starts counting, and the number of clocks of the CPU becomes equal to the value of the bus right acquisition request minimum time setting register (HOLD wait).
Until the value), the output of the counter 6 is a low-level signal. When the output of the counter 6 is a low level signal, the gate of the AND gate 12 is closed by the output of the HOLD request mask 10. Meanwhile, HOLD
Even if the ON condition signal is applied to the set terminal of the flip-flop circuit 11 and the output of the flip-flop circuit 11 is set to a high level signal, the AND gate 12 remains a low level signal, and
A high-level signal (HOLD signal) cannot be obtained. Thereafter, when the count value of the counter 8 reaches the value (HOLD wait value) of the bus right acquisition request minimum time setting register, the counter 8 outputs a high-level signal,
The output of the OLD request mask 10 allows the AND gate 12
, The high-level signal of the flip-flop circuit 11 is output by the AND gate 12. That is, after the bus right is released, the next bus right acquisition request signal HOLD
Is not allowed unless the counter 8 exceeds the value of the bus right acquisition request minimum time setting register 6.

FIG. 5 shows a time setting procedure according to the present invention. As a result, an optimal bus transfer amount suitable for the common bus situation can be obtained. Step 101 Start time setting Step 102 By setting a register of the central processing unit or executing a program described later, the DMA transfer time setting (setting of the number of cycles executed by one HOLD request) and the minimum bus request acquisition time ( Initial setting of HOLD request minimum time) Step 103 Investigate the usage status of the common bus by measuring the time during which HOLD is transmitted or the ratio of transmitting HOLDACK, etc. Step 104 Judgment of hardware processing capacity Step 105 Hardware If the processing capacity is insufficient, shorten the DMA transfer time (reduce the number of bus cycles) and change the setting to a longer minimum bus request acquisition time. Step 106 If the hardware processing capacity is not insufficient, change the DMA transfer time. Increase the transfer time (increase the number of bus cycles) and shorten the minimum bus request request time. Next, the configuration of a DMAC having the configuration of FIG. 4 will be described with reference to FIG. The DMAC 40 includes a HOLD generation unit 41 having the configuration shown in FIG.
DADS generation unit 44 for generating S, HOLD arbitration unit 45 for adjusting a plurality of HOLDs when they are generated, D
DMA for generating addresses required when executing MA
The address generation unit 46, the DM holding the address
A address holding unit 47, DMA sequencer DMASEQ
49 and the like. DMA sequencer DMAS
The EQ 49 includes a counter 42 and a decoder 43. The DMAC 40 receives a DMA event and a ready signal (RDY) from the outside.
ASEQ49, the output of the decoder 43 is RA
It is applied to the DS generation unit 44, the HOLD generation unit 41, and the DMA address generation unit 46. Minimum bus request acquisition time (H
HOLD wa for setting OLD request minimum time)
A bus cycle value for setting the it value and the DMA transfer time (DMA transfer time) is applied to the HOLD generation unit 41. The output of the HOLD generation unit 41 is applied from the HOLD generation unit 41 to the RADS generation unit 44 and the HOLD arbitration unit 45. The HOLD arbitration unit 45 receives another D from the outside.
The MAC bus right acquisition request signal HOLDREQ signal is applied. HOLDACK signal from outside and the HO
It is enabled by the AND signal of the LD signal, and the DMA address is output from the DMA address generator 46. Note that the position of the HOLD arbitration unit 45 is
Among them, before or even inside the DMAC, it may be configured as a separate block.

Next, details of the HOLD generation unit 41 will be described with reference to FIG. First, the OR circuit 54 has another DMAS
It is assumed that there is no REQ from the EQ (that is, the input of the OR circuit is only REQ1, and signals from other DMA sequencers are ignored). In this case, the control circuit 53, the control circuit 56, the counter 8, and the counter 9 in FIG. 7 correspond to the DMA transfer time setting register 7, the bus right acquisition request minimum time setting register 6, the counter 55, and the counter 50 in FIG. .

The control circuit 53 and the control circuit 56 are enabled by the output of the control circuit 52. Control circuit 53
Include AND output of a bus right acquisition request signal HOLD and a bus use permission signal HOLDACK (that is, a signal indicating that the DMAC has become a bus master), HOLD wai
The t value setting signal and the bus cycle value setting signal are applied. Basically, the control circuit 53 and the control circuit 56
The output of the control circuit 52 enables the DMAC when the DMAC is a bus master.

A bus cycle value setting signal is applied to the counter 50, and the value is set in the counter 50. Also, a HOLD wait value setting signal is applied to the counter 55, and the value of the counter 55 is set. The control circuit 53 receives a bus right acquisition request signal, a ready signal (RDY signal), and a count value of the counter 50 from the DMA sequencer. When the control circuit 53 is enabled by the output of the control circuit 52, it outputs a bus right acquisition request signal HOLD to the control circuit 56. On the other hand, the ready signal (RD
Y signal), and when the counter reaches the set value, the output of the bus right acquisition request signal HOLD to the control circuit 56 is stopped. The control circuit 56 includes a bus right acquisition request signal HOLD from the control circuit 53 and a clock signal (CP
UCK) and the count value of the counter 55 are input.
When the control circuit 56 is enabled by the output of the control circuit 52, it outputs a bus right acquisition request signal HOLD to the control circuit 56. On the other hand, the control circuit 56 stops outputting the bus right acquisition request signal HOLD from the control circuit 56 by negating the bus right acquisition request signal HOLD, and the CPU clock signal (CPUCK) by negating the bus right acquisition request signal HOLD. Of the bus right acquisition request signal HO to the control circuit 56 when the set value of the counter 55 is reached.
Release the LD output stop.

As a trigger of the counter 55, it is performed by negating the bus right acquisition request signal HOLD (FIG. 8).
(1)), it may be performed by negating the bus use permission signal HOLDACK ((2) in FIG. 8) The bus right acquisition request signal HOLD is negated in the bus right acquisition request signal HO.
From the falling time of LD, the bus right acquisition request signal HO
The rise time of the LD is set to HOLD wait. The bus use permission signal HOLDACK negation method sets the rise time of the bus right acquisition request signal HOLD from the fall time of the bus use permission signal HOLDACK. And any may be used. In the bus use permission signal HOLDACK negation method, as shown in FIG. 9, the bus use permission signal HOLDACK is applied to the control circuit 56 so that the control circuit 56
Must be able to detect the negation of the bus use permission signal HOLDACK.

The minimum bus request acquisition time and the DMA transfer time can be set by the following method. Part 1: Time setting by firmware setting After measurement of PWCB19 processing capacity, operation is changed by firmware setting. That is, the external monitor measures the ratio of the time during which the bus right acquisition request signal HOLD is transmitted or the time during which the bus use permission signal HOLDACK is transmitted to the entire time, and determines the state of the common bus. Measure. As a result, when the usage status of the common bus exceeds a predetermined level, the firmware is set with respect to the change of the setting values of the DMAC bus right acquisition request minimum time setting register and the DMA transfer time setting register. As a result, the setting values of the DMAC bus request acquisition minimum time setting register and the DMA transfer time setting register are changed.

[0033] If necessary, a program may be prepared, and the program may be executed to change the contents of the register. Part 2: Setting from outside via common bus After processing capacity is measured outside PWCB, setting is done from outside via common bus and operation is changed.

That is, the state of the common bus is measured by the external monitor as described above. As a result, when the usage status of the common bus exceeds a predetermined level, the DMAC bus right acquisition request minimum time setting register and the DMA transfer time setting register are accessed from outside via the common bus, and Make changes. Third: Direct setting from outside After measuring the processing capacity outside the PWCB, the DMAC is set directly from outside to change the operation.

That is, the state of the common bus is measured by the external monitor as described above. As a result, when the usage status of the common bus exceeds a predetermined level, the DMAC directly accesses the DMAC bus right acquisition request minimum time setting register and the DMA transfer time setting register to change the setting value. . Part 4: Autonomous setting The operation of the PWCB is changed autonomously.

That is, a program or the like stored in advance is started periodically, and the status of the common bus is measured using statistical information of the CPU or the OS that can know the use status of the bus. As a result, the usage status of the common bus
If the predetermined level is exceeded, the DMAC bus access request minimum time setting register and the DMA transfer time setting register are accessed to dynamically change the set value. Part 5: Example of setting by dedicated line The setting by “Part 2: Setting from outside via common bus” and “Part 3: Setting directly from outside” is the setting of register from outside. FIG. 11 shows an example of setting using a dedicated line.

(1) Direct setting using a dedicated line The HOLD generation unit 41 stores a HOLD wait value and a bus cycle value in another HOLD wait value holding unit 61 and a bus cycle value holding unit 62 from outside using a dedicated line. Set directly. The values of the HOLD wait value holding unit 61 and the bus cycle value holding unit 62 are set by a write enable signal.

(2) Direct setting without holding unit The HOLD wait value and the bus cycle value are set by a common bus or a dedicated line to the DMAC bus right acquisition request minimum time setting register and DMA transfer time setting of the DMAC of the HOLD generation unit 41. Register Access the register and set directly.

In this case, the write enable signal is not always necessary. Fifth: Setting by external register In the first to fourth, the time setting is set in the register in the DMAC, but the time setting is not necessarily set in the register in the DMAC. And may be referred to at the time of the bus master.

A cycle for reading the register is required, and the timing is as follows: DMAC pre-loads the data. ・ Reads every time the bus master reads. ・ Reads when the bus master reads, but uses the previous value. There are forms such as

With respect to the setting of the bus right acquisition request minimum time and the DMA transfer time, the following settings can be made by these changing means. It is possible to set such that the common bus is constantly measured and the processing capacity determined from the outside is maintained. When a large amount of data processing is temporarily required for the PWCB, the processing capacity can be dynamically changed.

It is possible to temporarily suppress the data processing of the PWCB and make a change so as not to hinder the other PWCB capability. Next, an example of a setting register used in the present invention will be described with reference to FIG. Although the description so far has been made without distinction between transmission and reception, here is an example in which a DMAC bus right acquisition request minimum time setting register and a DMA transfer time setting register are separately provided for transmission and reception.

FIG. 12A shows an example of the "basic register (DBRR)" which is the DMAC bus request acquisition minimum time setting register and the DMA transfer time setting register of the DMAC. The register is transmitted for the channel (bits 0 to 15)
And reception (bits 16 to 31).
Each of the registers has a portion for storing the number of times of bus suspension and a portion for storing the number of times of bus occupation. A HOLD wait value is set in a portion where the number of times of bus suspension is stored, and a bus cycle value is set in a portion where the number of times of bus occupancy is stored. The setting range of the bus stop count is, for example, 0 to FH (1 to 16).
The setting range of the bus occupation count is 1 to 3FH (1 to 6FH).
3).

The "bus right acquisition request minimum time guarantee register (HRQR)" guarantees the minimum time of the bus right acquisition request between transmission and reception. That is, even if the transmission and the reception operate as set in the register of the DBRR, the transmission and the reception are basically asynchronous. Therefore, considering the case of reception after transmission, reception after transmission is defined as reception by the basic register (DB
RR), the transmission of the bus acquisition request signal HOLD for reception may be issued almost immediately after the end of the transmission bus use permission signal HOLDACK. Therefore, even in such a case, the "bus right acquisition request minimum time guarantee register (HRQR)" is used to guarantee the minimum time of the bus right acquisition request.
Is provided. Due to this register, the bus right acquisition request signal HOLD can be transmitted not only by its own bus right acquisition request signal HOLD but also by the other person's bus right acquisition request signal HOLD even in asynchronous transmission and reception. Due to the relationship, the transmission is prohibited for a minimum time and will not be transmitted continuously.

A functional block using the "bus right acquisition request minimum time guarantee register (HRQR)" will be described with reference to FIG. The block 30 and the block 31 include a HOLD request mask 10 and a flip-flop circuit 11 respectively.
And a functional block of FIG. However, if the content is the block 30, the HOLD w set in the transmission basic register (DBRR)
The ait value and the bus cycle value are set, and block 31
If, the HOLD wait value and the bus cycle value set in the reception basic register (DBRR) are set.

Each of the OR circuits 32 transmits a bus right acquisition request signal HOLD according to each basic register (DBRR) without being aware of transmission of another bus right acquisition request signal HOLD. On the other hand, a HOLD request mask time setting register (HOLD mask) in accordance with the bus right acquisition request minimum time guarantee register (HRQR) is provided with a gate circuit 34 for guaranteeing the minimum time of the bus right acquisition request regardless of transmission or reception. Is applied with a mask signal.

In the above, two internal requests of transmission and reception have been described as internal requests of the DMAC (for example, transmission priority, transmission non-priority, reception non-priority, reception priority, etc.). Next, the operation in the case of three internal requests will be further generalized with reference to FIG. 7 and FIG.
REQ from other DMA sequencer DMASEQ in FIG. 7
Are three internal requests (REQA, REQB, DEQC)
It will be described as. Each internal request is an output of another DMA sequencer DMASEQ and is a signal passed through the control circuit 53. Therefore, the DMA transfer time (DMA
The transfer time is a bus right acquisition request signal HOLD controlled as set in the basic register (DBRR).

Since three internal requests are handled, each is A,
B and C are added to distinguish them. One internal request REQ
(A) is REQ (A) in REQ1 as described above.
(FIG. 14 (5)) is generated. In other words, Unta 50
A bus cycle value setting signal of REQ (A) (bus cycle value A: FIG. 14 (9)) is applied to (A), and the value is set in the counter 50 (A). In the control circuit 53,
The bus right acquisition request signal from DMASEQ (A), the ready signal, and the count value of the counter 50 (A) are input.
When the control circuit 53 (A) is enabled by the output of the control circuit 52 (A), the bus request acquisition request signal R
EQ (A) (FIG. 14 (5)) is output.

Similarly, other internal requests REQ (B), R
Similarly, EQ (C) also has a bus cycle value A (FIG. 14 (1)
0)) and the bus cycle value C (FIG. 14 (11)) (FIG. 14 (5)) bus right acquisition request signal REQ (B)
(FIG. 14 (6)), bus right acquisition request signal REQ (C)
(FIG. 14 (7)) is generated. Also, the counter 55
The HOLD wait value setting signal (FIG. 14 (8)) is applied to the counter 55, and the value is set in the counter 55.

The control circuit 56 is controlled by a HOLD wait setting signal (FIG. 14 (8)). This HO
The LD wait setting signal is commonly used for each internal request. Now, it is assumed that the bus right acquisition request signal REQ (A) is output to the control circuit 56 via the OR circuit 54. When a bus use permission signal HOLDACK (FIG. 14 (2)) is given from the bus controller, the bus controller becomes a bus master during the bus cycle value (A) and performs data transfer. When the time of the bus cycle value (A) has passed, the bus right acquisition request signal HO
The LD (A) is negated, and the bus controller also negates the bus use permission signal HOLDACK. Then, H
Transmission of the bus right acquisition request signal is prohibited only for the time "2" of the OLD wait value (FIG. 14 (8)). Next, the bus right acquisition request signal HO of the bus right acquisition request signal REQ (B)
The LD appears on the control circuit 56 via the OR circuit 56. D
MA transfer time was initially 5 cycles, but HOLD
Since the time "2" in the wait value (FIG. 14 (8)) has already elapsed, the bus right acquisition request signal HOLD is negated when the bus cycle value is "3". As a result, the bus right acquisition request signal REQ (B) stops the data transfer at the time “3”.

As described above, the bus request acquisition request signal HOLD of the internal request is adjusted.

[0052]

According to the present invention as described above, the following effects can be obtained. The operation of the common bus master can be easily adjusted, and the most efficient operation can be performed without a large-scale change. Compared with the conventional adjustment only for bus arbitration, much more detailed setting is possible.

The setting can be changed at any time after the initial setting. The situation of the common bus can always be set to the most favorable situation, and the function of the central processing unit can be maximized. It is possible to set such that the common bus is constantly measured and the processing capacity determined from the outside is maintained.

When a large amount of data processing is temporarily required for the PWCB, the processing capacity can be dynamically changed. Data processing of PWCB is temporarily suppressed, and the other PWCB
It can be changed so as not to hinder the CB ability.

[Brief description of the drawings]

FIG. 1 is a configuration example of a CPU-bus.

FIG. 2 shows an operation example of a CPU-bus.

FIG. 3 is a diagram for explaining the principle of the present invention.

FIG. 4 is a block diagram showing the configuration of the present invention.

FIG. 5 is a time setting procedure in the present invention.

FIG. 6 is a configuration diagram of a DMAC having the configuration of FIG. 4;

FIG. 7 is a detailed diagram of a HOLD generation unit.

FIG. 8 is a diagram for explaining a trigger of a HOLD wait number counter.

FIG. 9: HOLD in the case of HOLDACK negation method
Detailed view of the generator

FIG. 10 shows an example of a time setting method.

FIG. 11 shows an example of setting using a dedicated line.

FIG. 12 shows an example of a setting register used in the present invention.

FIG. 13 is a functional block diagram using an HRQR register;

FIG. 14 is an example of a time chart.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 common bus 2 central processing unit 3 bus controller 5 direct access controller (DMAC) 6 bus right acquisition request minimum time setting register 7 DMA transfer time setting register 8, 9 counter 10 HOLD request mask 52, 53, 54 control circuit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Ryo Takamiko, Inventor 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Miji Kato, Mikada-naka-4, Nakahara-ku, Kawasaki-shi, Kanagawa Chome 1-1 Fujitsu Limited

Claims (10)

[Claims] When a central processing unit or a direct memory access controller connected to a common bus performs data transfer using a common bus, a bus right acquisition request signal is sent in advance to a bus controller connected to the common bus. ,
After receiving a bus use permission signal from the bus controller, in a data transfer device by bus control which starts data transfer, the maximum data that the central processing unit or the direct memory access controller can perform by one bus use permission. DMA transfer time setting means for setting a transfer time, bus right acquisition request minimum time setting means for setting a minimum time until a next bus right acquisition request after data transfer performed in response to a bus use permission, and the DMA transfer time A data transfer device under bus control, comprising: a setting unit and a set value changing unit that changes a set value set by the bus right acquisition request minimum time setting unit. 2. The data transfer apparatus according to claim 1, wherein said DMA transfer time setting means sets the number of bus cycles corresponding to the data transfer time. 3. The data transfer device according to claim 1, wherein said bus right acquisition request minimum time setting means sets a clock number of the central processing unit corresponding to the minimum time. 4. The data transfer apparatus according to claim 1, wherein said setting value changing means is firmware of a central processing unit. 5. The setting value changing means transmits an external change instruction to the DMA transfer time setting means and the bus right acquisition request minimum time setting means directly via a dedicated line. 4. A data transfer device by bus control according to any one of claims 1 to 3. 6. The apparatus according to claim 1, wherein said setting value changing means transmits an external change instruction to said DMA transfer time setting means and said bus right acquisition request minimum time setting means via a common bus. 4. A data transfer device by bus control according to any one of claims 3 to 3. 7. The data transfer by bus control according to claim 1, wherein said set value changing means dynamically changes the set value based on a use condition of a common bus. apparatus. 8. The DMA transfer time setting means and the bus right acquisition request minimum time setting means each have a register provided inside or outside the direct memory access controller, and the DMA transfer time and the bus right acquisition request minimum time are provided. 9. The data transfer device by bus control according to claim 1, wherein the following is set in the register. 9. The bus right acquisition request minimum time setting means measures the lapse of time from the time when a bus right acquisition request signal or a bus use permission signal is turned off. A data transfer device by bus control according to any one of the preceding claims. 10. A direct memory access controller, comprising bus right acquisition request signal generation means for obtaining a bus right, wherein said bus right acquisition request signal generation means comprises a DMA transfer time setting means and a bus right acquisition request minimum time. A DMA transfer time setting means for setting a maximum data transfer time which can be performed by a single bus use permission, and a bus right acquisition request minimum time setting means for setting a data transfer time permitted by the bus use permission. A direct memory access controller, which sets a minimum time until a next bus right acquisition request after transfer.