JPH11112337A - Frequency synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency synthesizer high in settling speed and removable in the overshooting or ringing in a frequency change transition state. SOLUTION: When a different divided frequency is inputted to a divided frequency input (e), voltage (a) is outputted from an operational amplifier 11. At the same time, a waveform whose phase is inverted is outputted from an operational amplifier 12 and voltage (b) is obtained when a capacitor C removes a DC component. Voltages (a) and (b) are synthesized by an adder 13 and the voltage (c) of the waveform without the vibration component of overshooting and ringing is obtained. A system is switched to the output frequency corresponding to the divided frequency (e) by giving the output (c) of the adder 13 to a voltage control oscillator 2 as control voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a frequency synthesizer, and more particularly, to an increase in the transient response of a frequency synthesizer using a PLL.

[0002]

2. Description of the Related Art A phase locked loop (PLL) is often used as a frequency synthesizer. Conventionally, this kind of frequency synthesizer has been used in a communication device for the purpose of obtaining a signal of an arbitrary frequency. In this case, the frequency stability is extremely good, but there is a problem that it takes time until the frequency is newly stabilized when trying to change the frequency.

Japanese Patent Application Laid-Open No. Hei 5-183435 discloses that FIG.
As shown in (1), in a frequency synthesizer, it has been proposed to control an open loop gain of an active filter used as a loop filter in order to switch an output frequency at high speed.

FIG. 4 is a block diagram showing an example of a conventional frequency synthesizer. An output section d for outputting a desired frequency, a voltage controlled oscillator (VCO) 2 for varying the output frequency according to an input control voltage, and a variable for dividing a signal from the voltage controlled oscillator 2 by an arbitrary frequency division number and outputting the divided signal Divider (DIV)
3, a frequency division number input unit e for inputting a frequency division number of the variable frequency divider 3, and a reference frequency input unit f for inputting a reference frequency (for example, having a very high stability and generated based on a crystal oscillator output). have.

Further, a frequency / phase comparator (FPD) 4 for outputting a duty ratio modulated pulse corresponding to a phase difference between an output of the variable frequency divider 3 and a signal of the reference frequency input section f, and an output from the frequency / phase comparator 4 The applied pulse is filtered to direct current (D
C) Active loop filter (AL
F) 5, a gain switching input section g for controlling the open loop gain of the active loop filter 5 is provided.

Next, the operation will be described. The output of the voltage controlled oscillator 2 is input to the variable frequency divider 3, and the frequency division number input e
Sets the frequency division number of the variable frequency divider 3 and divides the frequency so that the frequency becomes the same as the reference frequency input f. The frequency / phase comparator 4 compares the phase difference between the output of the variable frequency divider 3 and the reference frequency, and outputs a phase difference pulse whose duty ratio changes according to the phase difference.

The active loop filter 5 smoothes the phase difference pulse into a DC voltage, and further switches and amplifies the amplification degree based on the gain switching signal g, and outputs the amplified signal. By providing the output of the active loop filter 5 to the control voltage input of the voltage controlled oscillator 2, a PLL circuit is formed, and an output frequency having the same frequency stability as the reference frequency is obtained.

When a frequency division number different from the frequency division number which has been set is input by the frequency division number input e, the open loop gain of the active loop filter 5 is increased by the gain switching input g. Thereafter, when the output frequency is settled within a certain value, a gain switching signal for lowering the open loop gain of the active loop filter 5 is set as a gain signal switching input g.

At this time, the output of the active loop filter 5 (the control voltage of the voltage controlled oscillator 2) changes as shown in FIG.

[0010]

In the proposal described in Japanese Patent Application Laid-Open No. 5-183435 shown in FIGS. 4 and 5, it is possible to quickly converge the response at the time of switching the output frequency. There is a problem that the spread of the unnecessary spectrum with respect to the output communication channel (communication path) cannot be suppressed. The reason is described below.

FIG. 5 shows the waveform of the control voltage of the voltage controlled oscillator 2 at the time of frequency switching in the conventional frequency synthesizer. Immediately after the change of the output frequency, the open loop gain of the active loop filter is increased to converge at high speed. Therefore, the control voltage becomes a waveform including overshoot and ringing, and the spectrum of the output communication channel is expanded.

Although the response at the time of switching the output frequency varies depending on the variation width of the output frequency to be switched, only two types of control of the open loop gain of the active loop filter have been proposed. Even if a plurality of types of gain control are realized, a complicated circuit is required.

Further, there is a problem that it is difficult to change the open loop gain of the active loop filter. Normally, when an active filter is adopted as a loop filter, it is common to use an operational amplifier (op-amp) formed as a monolithic IC, and the design is easy. The open loop gain of this monolithic IC operational amplifier cannot be changed.

An object of the present invention is to provide a high-speed settling frequency synthesizer which eliminates overshoot or ringing in a frequency change transient state.

[0015]

According to the present invention, there is provided a voltage controlled oscillator, a variable frequency divider for variably dividing the output of the voltage controlled oscillator, and the output of the variable frequency divider and a reference frequency signal. A frequency synthesizer comprising a comparator for comparing a phase difference, and a loop filter for generating a control voltage of the voltage-controlled oscillator according to an output of the comparator. First and second active filters of two phases, positive and negative, each having an output of the comparator as positive and negative phase inputs, and an output of the first active filter by removing a DC component of an output of the second active filter. And an adding means for adding the result to the voltage-controlled oscillator to obtain a frequency synthesizer.

To describe the operation of the present invention, a voltage-controlled oscillator that varies the output frequency in accordance with a control voltage, a variable frequency divider that divides a signal from the voltage-controlled oscillator by an arbitrary frequency and outputs the divided frequency, A frequency-phase comparator that outputs a duty-ratio modulated pulse according to the phase difference between the output of the variable frequency divider and the reference frequency; a loop filter that filters the pulse output from the frequency-phase comparator and converts the pulse into a DC voltage. The loop filter includes two active filters, a capacitor for removing a DC component, and an adder, and is configured to invert the phases of the active filters. Suppresses a vibration component due to a response of the PLL circuit such as overshoot or ringing generated from the other active filter.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a frequency synthesizer according to the present invention, and the same parts as those in FIGS.

In FIG. 1, a frequency synthesizer according to the present invention comprises an output section d for outputting a desired frequency,
A voltage controlled oscillator (VCO) 2 that varies an output frequency according to a control voltage, a variable frequency divider (DIV) 3 that divides a signal from the voltage controlled oscillator 2 by an arbitrary frequency division number, and outputs the divided frequency; And a frequency division number input section e for inputting the frequency division number of the frequency divider 3.

Further, a reference frequency input section f for inputting a reference frequency, and a frequency phase comparator (FPD) for outputting a duty ratio modulated pulse corresponding to a phase difference between the output of the variable frequency divider 3 and the reference frequency f ) 4 and a loop filter (LF) 1 for filtering the pulse output from the frequency phase comparator 4 and converting it into a DC voltage.

The loop filter 103 includes operational amplifiers 11 and 12 constituting two active filters, a capacitor C for removing a DC component of the output of the operational amplifier 12, and an adder for combining the outputs of the two active filters. 13. FIG. 3 shows details of the loop filter 1 shown in FIG.

Referring to FIG. 3, a loop filter 1 composed of these two active filters 11 and 12 includes an operational amplifier 11 and 12, an adder 13, capacitors C and C1.
To C4 and resistors R1 to R8.

In the operation of the embodiment of the present invention, in FIGS. 1 and 2, the output d of the voltage controlled oscillator 2 is input to the variable frequency divider 3, and the frequency division number of the variable frequency divider 3 is changed by the frequency division number input e. The frequency is set so that the frequency is eventually the same as the reference frequency input f. The frequency phase comparator 4 compares the phase difference between the output of the variable frequency divider 3 and the reference frequency, and outputs a duty ratio modulated pulse according to the phase difference.

The loop filter 1 smoothes a pulse corresponding to the phase difference of the output of the frequency phase comparator 4 into a DC voltage and outputs the DC voltage. By providing the output of the loop filter 1 to the control voltage input of the voltage controlled oscillator 2, a PLL circuit is formed. As a result, an output frequency having the same frequency stability as the reference frequency is obtained.

The operation when a frequency division number different from the frequency division number set so far is input to the frequency division number input e will be described. First, the operational amplifier 11 outputs a voltage a having a waveform as shown in FIG. At the same time, the operational amplifier 12 outputs a waveform whose phase is inverted from that of the waveform shown in FIG. 2A. When the DC component is removed from this output by the capacitor C, the voltage b having the waveform shown in FIG. can get.

The voltages a and b shown in FIGS. 2A and 2B are combined by the adder 13 to obtain a voltage c having a waveform without vibration components such as overshoot and ringing as shown in FIG. 2C. Can be The adder 1 shown in FIG.
By giving the output c of 3 as a control voltage to the voltage controlled oscillator 2, it is possible to switch to an output frequency corresponding to the frequency division number e at high speed.

At this time, P near the communication channel
No unnecessary spectrum is generated by the response of the LL circuit. Such features can be realized with a simple circuit configuration.

Next, according to the present invention, for example, when the output is 230M
In the embodiment of the frequency synthesizer in which the channel interval is 12.5 kHz in the Hz band, the output d for outputting the desired frequency and the control voltage of 3 to 9 V correspond to 230 to 2.
A voltage controlled oscillator (V) that varies the output frequency of 45 MHz
CO) 2 and the signal d from the voltage controlled oscillator 2
A variable frequency divider (DIV) 3 for dividing and outputting an arbitrary frequency division number in the range of 00 to 19,600, and a frequency division number for setting the frequency division number of the variable frequency divider 3 by digital data Input e
A reference frequency input terminal f for inputting a reference frequency of 12.5 kHz, and a frequency / phase comparator (FPD) 4 for outputting a duty ratio modulated pulse corresponding to a phase difference between the output of the variable frequency divider 3 and the reference frequency. And a loop filter (LF) 1 that filters a pulse output from the frequency phase comparator 4 and converts it into a DC voltage of 3 to 9 V.

The loop filter 1 includes operational amplifiers 11 and 12 constituting two active filters, a capacitor C for removing a DC component of the output of the operational amplifier 12, and outputs a and a of the two active filters 11 and 12.
and an adder 13 for synthesizing b. FIG. 3 shows details of the loop filter 1 shown in FIG.

The two active filters 11 and 12
Is composed of operational amplifiers 11 and 12, each having the same characteristics, an adder 13, capacitors C and C1 to C4, and resistors R1 to R8.

Next, the operation of the embodiment of the present invention will be described with reference to FIGS. In FIG. 1, a frequency d of 230 to 245 MHz is output from the voltage controlled oscillator 2. This output d is input to a variable frequency divider 3 in which a frequency division ratio of 18,400 to 19,600 is set.
To 12.5 kHz. On the other hand, a reference frequency of 12.5 kHz is input from the reference frequency input f, and the phase difference between this signal f and the output of the variable frequency divider 3 is compared by the frequency phase comparator 4.

The duty ratio modulated pulse corresponding to the phase difference is converted by the loop filter 1 into a DC voltage of 3 to 9 V. By applying this DC voltage to the control voltage input of the voltage controlled oscillator 2, a PLL circuit is formed.

The operation when changing the output frequency of the frequency synthesizer (PLL circuit) will be described. As shown in FIG. 3, the loop filter 1 includes two active filters 11 and 12 having the same characteristics. When the frequency division number e of the variable frequency divider 3 is changed in order to change the frequency, the frequency / phase comparator 4 outputs a duty ratio modulated pulse signal having a phase difference.

The pulse signals are input to the active filters 11 and 12 in the opposite phases to each other, and the phases of the outputs a and b of the active filters 11 and 12 are set to the opposite phases.
The output of one of the active filters 12 removes the DC component by the capacitor C. These output waveforms a,
FIG. 2B is shown in FIG. By combining the outputs a and b with the adder 13, a signal c having a waveform without overshoot or ringing as shown in FIG. 2C is obtained.

By providing the output c of the adder 13 shown in FIG. 2C as a control voltage to the voltage controlled oscillator 2, it is possible to switch to a desired output frequency according to the frequency division number at high speed. At this time, it is also possible to suppress the generation of unnecessary spectrum near the communication channel due to the response of the PLL circuit.

[0036]

As described above, according to the present invention,
By using two active filters whose phases are inverted as loop filters, the oscillation component of the transient response of the PLL circuit can be removed, so that the output frequency can be switched at high speed in the frequency synthesizer. There is an effect that the generation of unnecessary spectrum near the communication channel due to the vibration component of the response can be realized with a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a waveform of each unit according to the embodiment of the present invention.

FIG. 3 is a detailed circuit diagram of a loop filter according to the embodiment of the present invention.

FIG. 4 is a block diagram of an example of a conventional frequency synthesizer.

FIG. 5 is an explanatory diagram of waveforms of respective parts of an example of a conventional frequency synthesizer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Loop filter 2 Voltage controlled oscillator 3 Variable frequency divider 4 Frequency phase comparator 11, 12 Operational amplifier 13 Adder

Claims (3)

[Claims] A variable frequency divider for variably dividing an output of the voltage controlled oscillator; and a comparator for comparing a phase difference between an output of the variable frequency divider and a reference frequency signal. A frequency synthesizer that forms a phase-locked loop by a loop filter that generates a control voltage of the voltage-controlled oscillator according to the output of the comparator, wherein the loop filter outputs the output of the comparator as a positive-negative-phase input. The two-phase first and second active filters and the DC component of the output of the second active filter are removed, added to the output of the first active filter, and supplied to the voltage controlled oscillator. A frequency synthesizer comprising: 2. The frequency synthesizer according to claim 1, wherein said first and second active filters have an operational amplifier. 3. The frequency synthesizer according to claim 1, wherein the DC component of the second active filter is removed by a capacitor.