JPH11112298A - Ring oscillation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To change an oscillation frequency widely by providing two capacitors connected between the emitters of two transistors and the collectors of a first differential transistor couple. SOLUTION: The transistors Q1 and Q2 form the first differential transistor couple. The bases of transistors Q7 and Q8, which form the emitter follower of a second differential transistor couple Q3 and Q4, are connected to the collectors of the differential transistors Q3 and Q4. The emitters are connected to the outputs of the first differential transistor couple, namely, the connectors of the transistors Q1 and Q2 through capacitors 10 and 12. In such a case, capacitance CT for oscillation becomes larger than a capacitor constant C by the Miller effect of the emitter followers Q7 and Q8 and the increase amount can be changed by the amplification degrees G1 and G2 of the first and second differential transistor couple. Thus, the number of divided frequencies can be changed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ring oscillation circuit in which a plurality of inverting or non-inverting delay circuits are connected in series, and the output of the last stage is fed back to the input of the first stage.

[0002]

2. Description of the Related Art As shown in FIG.
The ring oscillation circuit is configured by connecting the inversion delay circuits DLY1, DLY2, DLY3 and the non-inversion delay circuits DLYn,.

FIG. 16 is a circuit diagram showing a configuration of a conventional inverting delay circuit. This inverting delay circuit includes a transistor Q
1, Q2, two output resistors R, a capacitor C, and a current source. The base of transistor Q1, Q2 are input terminals Tin, it is connected to a T / in, the collector is connected via an output resistor R to the supply line of the power supply voltage V _CC, an emitter connected in common. Each collector of the transistors Q1 and Q2 is connected to a capacitor C
(Capacitance value C), and are connected to output terminals Tout and T / out, respectively. Transistor Q1,
Between the common emitter of Q2 and the ground line GND, a transistor Q3 and a resistor R0, which constitute the current source, are connected in series. The control voltage V is input to the base of the transistor Q3, whereby the current value i of the current source is adjusted.

The inverting delay circuit DLY1 having such a configuration (FIG. 1)
5) In the state where the control voltage V for flowing the predetermined current i is applied to the current source, the input signal IN is input to the input terminal Tin.
And an inverted signal of the input signal IN (inverted input signal INn) is input to the inverted input terminal T / in, and the base of the transistor Q1 changes from “low level (L)” to “high level (H)”. Assume that the base of Q2 changes from "L" to "H". Since the transistor Q1 is turned on and the transistor Q2 is turned off, a current i flows through the transistor Q1 and the potential of the node on the transistor Q1 side of the capacitor C drops, and electric charges are supplied to the other node from the power supply voltage line via the output resistor R. Is done. For this reason, while the level of the output signal OUT appearing at the output terminal Tout decreases, the inverted output signal OU appearing at the inverted output terminal T / out.
The level of Tn gradually increases with a time constant τ determined by the output resistance R and the capacitor C. Next, when the base of the transistor Q1 changes from “H” to “L” and the base of the transistor Q2 changes from “H” to “L”, the transistor Q1 turns off and the transistor Q2 turns on. Contrary to the above, the capacitor C discharges the node on the transistor Q2 side and charges the node on the transistor Q1 side with the time constant τ, so that the level of the inverted output signal OUTn decreases while the output signal OU
The T level gradually increases with a time constant τ.

As a result, the inversion operation of the next stage inversion delay circuit DLY2 is delayed by a time tpd determined by the time constant τ. This delay operation is performed by delay circuits DLY3,.
The delay time tpd is integrated during the repetition of DLYn,
If the integrated delay time matches the half cycle T / 2 of the signal when returning from the last stage DLYn to the first stage DLY, the ring oscillation circuit oscillates at a period T. In other words, if the number of stages of the delay circuit is m, the delay time t that satisfies the following equation:
Setting the constants of the output resistance R and the capacitor C so as to obtain pd is a condition for stable oscillation.

[0006]

[Expression 1] T / 2 = m × tpd (1)

[0007]

However, in this conventional ring oscillation circuit, the time constant τ determined by the constants of the output resistance R and the capacitor C is fixed, and the oscillation frequency cannot be changed. In particular, since the output resistance R defines the output signal amplitude, it cannot be changed unnecessarily, and the capacitance of the delay circuit shown in FIG. 17 does not move from the capacitor constant (fixed value). Was a factor that could not be changed.

The present invention has been made in view of the above circumstances, and has as its object to provide a ring oscillation circuit capable of adjusting an effective capacitance value and thereby widely changing an oscillation frequency.

[0009]

In order to solve the above-mentioned problems of the prior art and to achieve the above object, a first ring oscillation circuit according to the present invention comprises a plurality of inverting or non-inverting delay circuits. A ring oscillation circuit in which the last stage output is fed back to the first stage input in series connection, wherein each of the delay circuits has a base connected to an input terminal, a collector connected to an output resistor and an output terminal, and And a second differential transistor whose bases are respectively connected to the input terminals, and which can obtain an output having a phase opposite to that of the first differential transistor pair by changing the gain. A pair, two transistors each having a base connected to one or the other of the outputs of the second differential transistor pair, and an emitter of each of the two transistors and the first differential transistor. It characterized by having two capacitors are connected between the collectors of transistor pair. Preferably, a current source capable of individually adjusting a current amount is connected to at least each of the common emitter sides of the first or second differential transistor pair.

In the first ring oscillation circuit, the two transistors form an emitter follower when viewed from the second differential transistor pair. Therefore, in the high frequency region,
Due to the effect that the collector connection capacitance of the emitter follower is almost multiplied by the gain and is effectively inserted between the base and the collector (Miller effect), the capacitance value of the capacitor connected to the emitter becomes apparently larger than the capacitor constant.
In addition, the increase in the capacitance value is defined by the amplification of the first and second differential transistor pairs. Therefore, in this ring oscillation circuit, it is possible to substantially increase the capacitance value of the capacitor by changing the amplification degree of the first and second differential transistor pairs, for example, the current value of the current source.

In the second ring oscillation circuit according to the present invention,
The first and second differential transistor pairs, the two transistors forming an emitter follower, and the two capacitors are the same as those of the first ring oscillation circuit. The driving transistor pair is, for example, the second ring oscillator circuit.
The same phase is output by connecting the outputs of the differential transistor pair in reverse. In this case, the additional capacitance due to the above-mentioned Miller effect acts to make the capacitance value of the capacitor apparently smaller than the capacitor constant. For this reason,
In the second ring oscillation circuit, for example, the capacitance value of the capacitor can be substantially reduced by changing the current value of the current source.

[0012] The third ring oscillation circuit of the present invention further comprises:
By adding a switching circuit for selectively operating between a plurality of transistors serving as emitter followers, an output of the same phase or the opposite phase is selectively extracted from the second differential transistor pair. As a more specific configuration, for example, a total of four transistors forming an emitter follower are provided, and as the switching circuit, a second differential transistor pair of the four transistors is operated in accordance with an input selection signal. 3rd and 4th selecting two transistors which take out the same phase or the opposite phase output from
Is preferably connected to the emitters of the four transistors. The third ring oscillation circuit has the functions of the above-described first and second ring oscillation circuits of the present invention, and these functions can be electrically switched by a selection signal. It is possible to change both the positive side and the negative side around the capacitor constant. The amount of change is, for example, similar to that of the first and second ring oscillation circuits, for example, the first and second
Can be adjusted by changing the value of the current flowing through the current source of the differential transistor pair. Therefore, it is possible to change the oscillation frequency in a very wide range.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a ring oscillation circuit according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a configuration example of the ring oscillation circuit. The ring oscillation circuit according to the present embodiment has n stages of non-inverting delay circuits DLY1, DLY2, DLY3,.
DLYn are connected in series, and the final non-inverting delay circuit DL
The outputs of Yn are interchanged externally and connected to the input of the first stage non-inverting circuit DLY1. The same functionality is
It can also be achieved by connecting the inverting delay circuits in odd-numbered stages in series, or by inserting an odd number of inverting delay circuits into the non-inverting delay circuit row as appropriate. Since the inverting delay circuit can be achieved by exchanging the internal connection to the output terminal of the non-inverting delay circuit, the following description will be made for various ring oscillation circuits having different configurations of the non-inverting delay circuit.

First Embodiment This embodiment relates to a ring oscillation circuit capable of substantially increasing the capacitance value. FIG. 2 is a circuit diagram showing a configuration of the non-inverting delay circuit according to the present embodiment. This non-inverting delay circuit has n
pn type bipolar transistors Q1 to Q10, resistance elements 2 and 4 (resistance value: R1), 6 and 8 (resistance value: R2) and R3 to R6, capacitors 10 and 12 (capacitance value constant:
C).

The transistors Q1 and Q2 form a first differential transistor pair. The bases of the transistors Q1 and Q2 are respectively connected to the input terminals Tin and T / in, the collectors are respectively connected to the output terminals T / out and Tout, and the emitters are commonly connected. Also, the transistor Q
Collector 1 and Q2 are connected to each via an output resistor 2,4 common line of the power supply voltage V _CC (hereinafter, V _CC line),
A current source including a transistor Q5 and a resistance element R3 is connected between the common emitter and the ground line GND.
The transistor Q5 has a control voltage V1 input to the base.
Sets the value of the current i1. Similarly, transistors Q3 and Q4 form a second differential transistor pair. The bases of the transistors Q3 and Q4 are connected to input terminals Tin and T / in, respectively, and the emitters are commonly connected. The collectors of the transistors Q1 and Q2 are
Each is connected to the _Vcc line via output resistors 6 and 8, and a transistor Q is connected between the common emitter and the ground line GND.
6 and a current source composed of a resistance element R4. In transistor Q6, the value of current i2 is set by control voltage V2 input to the base.

The transistors Q7 and Q8 form an emitter follower of the second differential transistor pair Q3 and Q4. The bases of the transistors Q7 and Q8 are connected to the collectors of the differential transistors Q3 and Q4, respectively, and the emitters are connected to the output of the first differential transistor pair via the capacitors 10 and 12, respectively, that is, the collectors of the transistors Q1 and Q2. Have been. The collectors of the transistors Q7 and Q8 are both connected to the _Vcc line, and the transistor Q9 and the resistor R5 are connected between each emitter and the ground line GND.
Alternatively, a current source including the transistor Q10 and the resistance element R6 is connected to each other. Transistors Q9, Q10
, The values of the currents i3 and i4 are set by the control voltage V3 commonly input to the base.

In the non-inverting delay circuit having such a configuration, the output of the first differential transistor pair Q1 and Q2 has an opposite phase to the input, and the second differential transistor pair Q3 and Q4
Is in phase with the input. The first and second
G1 and G2 respectively.
Then, as shown in FIG. 3, the inverting amplifier (-G1)
Is connected in parallel with the non-inverting amplifier (G2) and the capacitance CT connected in series, and an output is taken out from a connection node between the inverting amplifier (-G1) and the capacitance CT. Here, the capacitance CT is the value of the capacitor 10
Or 12 indicates an effective capacitance value. Although omitted in FIG. 3, the emitter follower Q7 or Q8 is interposed between the non-inverting amplifier (G2) and the capacitance CT. In such a signal transmission circuit via an emitter follower, generally, the collector connection capacitance of the emitter follower is substantially multiplied by the gain and added between the gate and the emitter, that is, added to the signal transmission path.
Therefore, the effective capacitance CT of the capacitors 10 and 12 changes from the constant C according to the gains of the amplifiers (-G1) and (G2). Further, since the capacitors 10 and 12 are sandwiched between the inverting and non-inverting amplifiers, this capacitance change direction is positive. When this effective capacitance value CT is expressed by an equation, the following equation is obtained. The derivation of this equation will be described at the end of the second embodiment.

[0019]

## EQU2 ## CT = (1 + G2 / G1) .times.C (2)

In this equation, the amplification factors G1 and G2 can be changed in accordance with the currents i1 and i2 flowing through the differential transistor pair. The effective value CT can be changed in an increasing direction with respect to the constant C.

Next, this non-inverting delay circuit is connected to the DL in FIG.
The operation of the ring oscillation circuit will be described with reference to the case where Y1 to DLYn are used. FIG. 4 is a timing chart of the ring oscillation circuit. 4, signals IN and OUT input and output from terminals Tin and Tout are shown by solid lines, and inverted signals INn and OUTn input and output from terminals T / in and T / out are shown by dashed lines.

Now, assuming that the feedback loop of the ring oscillation circuit shown in FIG. 1 is not connected, a predetermined level of control voltage V
It is assumed that the input signal IN shown in FIG. 4A is input to the first stage DLY1 in a state where 1 to V3 are applied. First, since the level of the input signal IN is “H” and the level of the inverted input signal INn is “L”, the transistors Q1 and Q3 are turned on, the transistors Q2 and Q4 are turned off, and the current i1
i2 flows on the transistor Q1 side and Q3 side, respectively. At this time, the levels of output nodes ND1 (inverted output signal OUTn) and ND3 of transistors Q1 and Q3 are "L", and output nodes ND2 of transistors Q2 and Q4.
(Output signal OUT) and the level of ND4 take "H".
Further, the emitter follower Q7 is on and the transistor Q8 is off, so that the current i3 flows and the current i4 hardly flows. Therefore, if there is no current difference between currents i1 and i3, capacitor 10 is hardly charged, and capacitor 12 is in a charged state.

When the base potentials of the transistors Q1 and Q3 decrease to some extent and the base potentials of the transistors Q2 and Q4 increase to some extent, the transistors Q1 and Q3 and the emitter follower Q7 begin to transition from the conductive state to the non-conductive state, and conversely Q2, Q4 and emitter follower Q8 start to transition from the non-conductive state to the conductive state. Therefore, capacitor 12 starts discharging through transistor Q2, while capacitor 10 has its emitter follower Q7 side node potential pulled to GND by current i3 and the other node starts charging through output resistor 2. .
As a result, as shown in FIG. 4 (b), the output signal OUT of the first stage DLY1 gradually decreases with the time constant τ1 mainly determined by the effective capacitance CT and the resistance value R3 of the above equation (2). Further, the inverted output signal OUTn of the first stage DLY1 gradually increases with a time constant τ1 determined by the effective capacitance CT and the resistance value R1. In this example, the resistance value that contributes to the charging and discharging of the capacitor is assumed to be substantially equal, but this time constant may be changed. Thereafter, when the transistors Q1 and Q3 are cut off and the transistors Q2 and Q4 shift to a saturated state, the charging / discharging ends, and the output signals OUT and OUTn take constant values.

Next, when the base potentials of the transistors Q1 and Q3 increase to some extent and the base potentials of the transistors Q2 and Q4 decrease to some extent, the transistors Q1 and Q3 and the emitter follower Q7 start to transition from the non-conductive state to the conductive state. Conversely, the transistors Q2, Q4 and the emitter follower Q8 start to transition from the conductive state to the non-conductive state.
Therefore, the capacitor 12 has its emitter follower Q8
The side node potential is pulled toward the GND side by the current i4, the electric charge is supplied to the other node side via the output resistor 4 and starts to be charged, while the capacitor 10 starts to be discharged via the transistor Q1. As a result, as shown in FIG. 4B, the output signal OUT of the first stage DLY1 gradually increases with the time constant τ1, and the inverted output signal OUTn of the first stage DLY1 changes with the time constant τ1.
And gradually decrease. Thereafter, when the transistors Q1 and Q3 are saturated and the transistors Q2 and Q4 are cut off, the output signals OUT and OUTn take constant values. Such first stage D
Due to the operation of LY1, as shown in FIGS. 4A and 4B, the input / output differential point, that is, the intersection of the input signals IN and INn and the intersection of the output signals OUT and OUTn is delayed by the time tpd. .

The basic operation of the non-inverting delay circuit described above is the same in the next stage DLY2,..., Since the change in the output signal starts from the preceding differential point (the intersection of the output signals OUT and OUTn). An output which is further delayed by the time tpd is obtained for each delay circuit, and the delay time tpd is accumulated every time the stage is followed. A non-inverting delay circuit when the accumulation of the delay time tpd becomes an integral multiple of the half cycle T / 2 is set as a final stage.
When the output of the last stage DLYn is inverted and connected to the input of the first stage DLY1, the final first stage input becomes an inverted signal shifted by one pulse width from the initial input (FIG. 4A) shown in FIG. 4D. Therefore, the circuit satisfies the above-described equation (1) indicating the oscillation condition and oscillates stably. In other words, the ring oscillation circuit oscillates at the oscillation frequency T determined by the number of stages of the delay circuit and the time constant τ1, whereby a pulse train of the frequency T can be obtained.

In the ring oscillation circuit of this embodiment, the effective capacitance CT of the oscillation capacitors 10 and 12 becomes larger than the capacitor constant C due to the Miller effect of the emitter followers Q7 and Q8, and the amount of increase is the first and second.
Can be changed by the amplification degrees G1 and G2 of the differential transistor pair, so that the frequency can be changed correspondingly.

Second Embodiment This embodiment relates to a ring oscillation circuit whose capacitance can be substantially reduced. FIG. 5 is a circuit diagram showing a configuration of the non-inverting delay circuit according to the present embodiment. This non-inverting delay circuit has n
pn type bipolar transistors Q1 to Q10, resistance elements 2 and 4 (resistance value: R1), 6 and 8 (resistance value: R2) and R3 to R6, capacitors 10 and 12 (capacitance value constant:
The configuration of C) is the same as that of the first embodiment.

In this example, the connection between the output of the second differential transistor pair and the two emitter followers Q7 and Q8 is opposite to that in the first embodiment. That is, the base of the emitter follower Q7 is connected to the output node ND3 of the second differential transistor pair, and the base of the emitter follower Q8 is connected to the inverted output node ND4. Other connection relations are not different from those of the first embodiment.

FIG. 6 is a diagram showing a relationship between an amplifier and a capacitor using first and second differential transistor pairs.
In this example, the amplifier is an inverting amplifier (gain: -G2) by replacing the output of the second differential transistor pair with that of the first embodiment. Therefore, the effective capacitance CT in this example is represented by the following equation.

[0030]

## EQU3 ## CT = (1-G2 / G1) .times.C (3)

In this equation, the amplification factors G1 and G2 can be changed in accordance with the currents i1 and i2 flowing through the differential transistor pair. The effective value CT can be changed in a decreasing direction with respect to the constant C.

FIG. 7 is a timing chart of the ring oscillation circuit in this embodiment. The basic operation of the non-inverting delay circuit is the same as that of the first embodiment, but the charging and discharging of the capacitor is slightly different from the previous example.

That is, the base potential of the transistors Q1 and Q3 in FIG. 5 decreases to some extent due to the decrease of the first-stage input IN in FIG. 7A, and the base potentials of the transistors Q2 and Q4 increase to some extent. Emitter follower Q8 starts to transition from a conductive state to a non-conductive state, and conversely, transistors Q2, Q4 and emitter follower Q7 begin to transition from a non-conductive state to a conductive state.
In this case, since the current i1 decreases and the current i3 increases,
The capacitor 10 is discharged by the balance between the current decrease and the current increase. On the other hand, the current i
As the current 2 increases and the current i4 increases, the capacitor 12 is charged in a balance between the current increase and the current decrease. For this reason, the voltage applied between the capacitors is smaller than that in the first embodiment. In this case, however, the effective capacitance value CT itself is small as shown in the above equation (3), so that the charge and discharge can be sufficiently performed by adjusting the current value. Is guaranteed. As a result, as shown in FIG. 7B, the output signal OUT gradually decreases with a small time constant τ2, the inverted output signal OUTn gradually increases, and thereafter saturates.

Next, when the base potentials of the transistors Q1 and Q3 increase to some extent and the base potentials of the transistors Q2 and Q4 decrease to some extent, the transistors Q1 and Q3 and the emitter follower Q8 start to transition from the non-conductive state to the conductive state. Conversely, the transistors Q2, Q4 and the emitter follower Q7 begin to transition from the conductive state to the non-conductive state.
For this reason, the capacitor 10 is discharged in a manner opposite to the above, in a balance between the increase in the current i1 and the decrease in the current i3, and the capacitor 12 is configured to reverse the decrease in the current i2 and the current i3.
Charged with a balance of 4 increase. As a result, FIG.
As shown in (b), the output signal OUT has a small time constant τ.
2 and the inverted output signal OUTn has a small constant τ
Decrements at 2 and then saturates. Such first stage DLY
By the operation of No. 1, as shown in FIGS. 7 (a) and 7 (b),
The input / output differential point, that is, the intersection of the input signals IN and INn and the intersection of the output signals OUT and OUTn is delayed by the time tpd. The delay time tpd at this time is smaller than that in the first embodiment because it takes a half value of the time constant.

The basic operation of this non-inverting delay circuit is the same in the subsequent stages DLY2,..., As in the first embodiment.
The ring oscillation circuit at a predetermined oscillation frequency T at which the accumulation of pd becomes an integral multiple of the half cycle T / 2 and an inverted signal shifted from the initial input (FIG. 4A) by a unit of pulse width is fed back to the first-stage input. Oscillates, whereby a pulse train of frequency T can be obtained.

In the ring oscillation circuit of the present embodiment, the effective capacitance CT of the oscillation capacitors 10 and 12 becomes smaller than the capacitor constant C due to the Miller effect of the emitter followers Q7 and Q8, and the amount of decrease is the first and second.
Can be changed by the amplification degrees G1 and G2 of the differential transistor pair, so that the frequency can be changed correspondingly.

Here, the derivation of the equations (1) and (2) in the first and second embodiments will be described in more detail. In general, the capacitance C _M due to the above-mentioned Miller effect (hereinafter, Miller capacitance) is almost equal to the gain of the collector connection capacitance C in the circuit shown in FIG. 8, and is given by the following equation.

[0038]

[Number 4] _{C M = i / v i =} (1 + G) C ... (4)

[0039] Here, G is the voltage gain of the emitter follower, an input-output voltage ratio v _o / v _i.

In the first and second embodiments, if the emitter followers Q7 and Q8 of the voltage amplification factor 1 are neglected in the circuit, the transistors Q1 and Q4 are connected via the capacitor 10, and the transistors Q2 and Q3 are connected by the capacitor. 12
Connected through. This connection relationship is generalized as shown in FIG.

Here, the output voltage of Q1 (or Q2) is
_o1 , the output current is i _L , and the output voltage of Q4 (or Q3) is v
_o2 , _assuming that the output current is i _R , the following equations (5) and (6) hold from the above equation (4).

[0042]

Equation 5] _{i L = (1 + G1)} Cv i ... (5) i R = (1 + G2) Cv i ... (6) where, G1 and G2, the voltage gain of Q1 (or Q2) and Q4 (or Q3) It is.

[0043] Thus, the charging current of the capacitor C (10 or 12) (i _L -i _R), the following (7) expressed G1 and G2 are in phase and opposite phase of the mirror capacitance C _M and C _M 'is formula And the following equations (8) and (9).

[0044]

[6] _{i L -i R = (G1-} G2) C · v i = (1-G2 / G1) C · v i · G1 = (1-G2 / G1) C · v O1 ... (7) C _{M = (i L -i R)} / v O1 = (1-G1 / G2) C ( _{phase) ... (8) C M '} = (i L -i R) / v O1 = (1-G1 / G2) C (Negative phase)… (9)

On the other hand, the emitter follower Q7 (or Q8)
Amplification effect of the parasitic capacitance due to the Miller effect of the capacity as (1 + g) C _Ob in consideration of FIG. 10 (a) is connected in series with C _M. Where g is the emitter follower Q7 (or Q
8) The voltage gain, C _Ob, is the parasitic capacitance between their base and collector. However, since C _M ≫C _Ob and g = 1, (1 + g) C _Ob can be ignored and C _T ≒ C _M.

[0046] Thus, equation (8), (9) is the result with the formula that approximates the total capacitance C _T (2) and Equation (3)
The equation holds.

Third Embodiment This embodiment relates to a ring oscillation circuit capable of substantially increasing or decreasing the capacitance value from the capacitance constant and changing the frequency in a wider range. FIG. 11 is a circuit diagram showing a configuration of the non-inverting delay circuit according to the present embodiment. This non-inverting delay circuit includes npn-type bipolar transistors Q1 to Q6.
Q9 and Q10, resistance elements 2 and 4 (resistance value: R1),
6 and 8 (resistance value: R2) and R3 to R6, capacitor 1
Having 0 and 12 (capacitance value constant: C) is the same as in the first embodiment.

In this example, the emitter followers Q7 and Q8 in the first embodiment are replaced by Q7a, Q7b and Q8, respectively.
a and Q8b, the capacitors 10, 1 in the first embodiment.
2 is composed of two capacitors 10a and 10b and 12a and 12b, respectively, and a third differential transistor pair for selecting the emitter follower 7a or Q7b and a third differential transistor for selecting the emitter follower 8a or Q8b. The fourth embodiment differs from the first embodiment in that four differential transistor pairs and a current source are newly provided.

More specifically, the base of emitter follower Q7a is connected to node ND4, and capacitor 10a is connected between the emitter and node ND1. The base of the emitter follower Q7b is the node N
D3, a capacitor 10b is connected between its emitter and node ND1, and an emitter follower Q8a
Is connected to node ND3, a capacitor 12a is connected between its emitter and node ND2, the base of emitter follower Q8b is connected to node ND4, and a capacitor 1a is connected between its emitter and node ND2.
2b is connected. The constants (capacitances) of the four capacitors 10a, 10b, 12a and 12b in this example are all the same C. on the other hand,
Transistor Q1 forming third differential transistor pair
1 is connected to the emitter of the emitter follower Q7a, the collector of the transistor Q12 is connected to the emitter of the emitter follower Q7b, and both transistors Q1
The emitters of the transistors Q1 and Q12 are commonly connected to the collector of the transistor Q9 forming a current source. The collector of the transistor Q13 constituting the fourth differential transistor pair is connected to the emitter of the emitter follower Q8a, the collector of the transistor Q14 is connected to the emitter of the emitter follower Q8b, and the emitters of both transistors Q13 and Q14 are commonly used. The current source is connected to the collector of the transistor Q10. The third and fourth differential transistor pairs are driven by the selection signal S input to the bases of the transistors Q11 and Q13 and the inverted signal Sn of the selection signal S input to the bases of the transistors Q12 and Q14. Is done. Other connection relations are not different from those of the first embodiment.

FIG. 12 is a diagram showing a relationship between an amplifier and a capacitor using the first and second differential transistor pairs. In this example, the second differential transistor pair generates an output having the same phase as that of the first differential transistor pair and an output having the opposite phase, and both outputs are constituted by the third and fourth differential transistor pairs. The differential switches SW1 and SW2 are used to switch and take out. In other words, while the first differential transistor pair forms an inverting amplifier (gain: -G1), when SW1 is on and SW2 is off in the differential switch, the second differential transistor pair is non-inverting. When SW1 is off and SW2 is on in the differential switch, the second differential transistor pair forms an inverting amplifier (gain: -G2).
Therefore, the effective capacitance CT in this example is represented by the following equation.

[0051]

## EQU7 ## CT = CTa = (1 + G2 / G1) .times.C (SW1: on, SW2: off) CT = CTb = (1-G2 / G1) .times.C (SW1: off, SW2: on) (10)

The differential switch is driven by the selection signals S and Sn, and the amplification factors G1 and G2 can be changed according to the currents i1 and i2 flowing through the differential transistor pair. Within the range, the effective value CT of the capacitor can be changed in both directions of increasing and decreasing with respect to the constant C.

In the non-inverting delay circuit of this embodiment, four transistors Q7a, Q7b,
Of the transistors Q8a and Q8b, a pair of two transistors is switched and operated by a differential switch (a third and fourth differential transistor pair). Here, the switch SWa
Is ON when the transistors Q7a and Q8a are conducting, and when the switch SWb is ON, the transistor Q7a
This is the case where b and Q8b are conducting. When the level of the selection signal S is “H”, the switch SWa (the transistor Q7
The a, Q8a) side is turned on, the effective capacitance value CT becomes larger than the constant C by the same operation as in the first embodiment, and the ring oscillation circuit oscillates at a low frequency. On the other hand, when the level of the inversion selection signal Sn is “H”, the switch SWb
(Transistors Q7b, Q8b) are turned on, and the second
By the same operation as in the embodiment, the effective capacitance value CT becomes constant C
The ring oscillator circuit oscillates at a higher frequency. It should be noted that FIG. 4 is applied as it is for the former low-frequency oscillation, and FIG. 7 is applied as it is for the latter high-frequency oscillation, so that detailed description is omitted to avoid duplication.

In the ring oscillation circuit of this embodiment, FIG.
As shown in the figure, when the switch SWa is turned on, the effective capacitance CTa of the oscillation capacitors 10a and 12a increases by the coefficient of G2 / G1 based on the capacitor constant C due to the Miller effect of the emitter followers Q7a and Q8a. On the other hand, when the switch SWb is on, the effective capacitance CTb of the oscillation capacitors 10b and 12b is caused by the Miller effect of the emitter followers Q7b and Q8b.
Becomes smaller by the coefficient of G2 / G1 based on the capacitor constant C. For this reason, in the ring oscillation circuit according to the present embodiment, the delay time tpd per one stage of the delay circuit is the first delay time tpd.
Alternatively, there is an advantage that the oscillation frequency can be changed more widely than in the case of the second embodiment, and the change range of the oscillation frequency is wide.

Finally, an operation simulation result of the above-described ring oscillation circuit will be described.

Operation Simulation Results FIG. 14 shows the operation simulation results in a table. TYPEA has eight stages of the non-inverting delay circuit of the first embodiment shown in FIG. 2 connected to the ring oscillation circuit of FIG. 1, and TYPEB has eight stages of the non-inverting delay circuit of the second embodiment shown in FIG. When connected. In TYPEA, the oscillation frequency could be widely changed from 17 MHz to 71 MHz. In TYPEB, the oscillation frequency is 72 MHz.
It can be widely changed in the high frequency range of TYPEA, from z to 645 MHz. The current consumption per one stage of the non-inverting delay circuit was 1000 μA to 1800 μA. In addition,
In the case of the third embodiment shown in FIG. 11, the above TYPEA and B are combined, and the frequency is 17 MHz to 645.
MHz and wider oscillation is possible.

[0057]

As described above, according to the ring oscillation circuit of the present invention, it is possible to provide a ring oscillation circuit capable of adjusting the effective capacitance value and thereby widely changing the oscillation frequency. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of a ring oscillation circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a non-inverting delay circuit according to the first embodiment of the present invention.

3 is a diagram showing a relationship between an amplifier and a capacitor using first and second differential transistor pairs in the non-inverting delay circuit of FIG. 2;

FIG. 4 is a timing chart of a ring oscillation circuit including the non-inverting delay circuit of FIG. 2;

FIG. 5 is a circuit diagram showing a configuration of a non-inverting delay circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a relationship between an amplifier and a capacitor using first and second differential transistor pairs in the non-inverting delay circuit of FIG. 5;

FIG. 7 is a timing chart of a ring oscillation circuit including the non-inverting delay circuit of FIG. 5;

FIG. 8 is a basic circuit diagram for deriving a mirror capacitance.

FIG. 9 is a circuit diagram in which basic circuits for deriving a mirror capacitance are arranged symmetrically in two stages.

FIG. 10 is a diagram in which amplification of parasitic capacitance due to the Miller effect is considered.

FIG. 11 is a circuit diagram showing a configuration of a non-inverting delay circuit according to a third embodiment of the present invention.

12 is a diagram showing a relationship between an amplifier and a capacitor using first and second differential transistor pairs in the non-inverting delay circuit of FIG. 11;

FIG. 13 is a diagram illustrating a relationship between a variable coefficient of an effective capacitance and a time constant (delay time) according to the third embodiment.

FIG. 14 is a table collectively showing operation simulation results.

FIG. 15 is a diagram showing a configuration of a general ring oscillation circuit used for explaining a conventional technique.

FIG. 16 is a circuit diagram showing a configuration of a conventional inversion delay circuit.

FIG. 17 is a diagram illustrating a relationship between a differential amplifier and a capacitance in the inverting delay circuit of FIG. 16;

[Explanation of symbols]

2 to 8: output resistance, 10, 10a, 10b, 12, 12
a, 12b: capacitor, Q1, Q2: transistor forming a first differential transistor pair, Q3, Q4: transistor forming a first differential transistor pair, Q7, Q7a,
Q7b, Q8, Q8a, Q8b: transistors forming emitter followers; Q5, Q6, Q9, Q10: transistors forming current sources; R3 to R4: resistors;
DLYn ... non-inverting delay circuit, G1, G2 ... amplification degree of the differential transistor pair, C ... capacitor constant, C _M ... Miller capacitance, CT ... effective capacitance, Tin, T / in ... input terminal, Tout, T / out ... Output terminal, IN, INn input signal, OUT, OUTn output signal, V1 to V3 control voltage, S, Sn ... selection signal, τ time constant, tpd delay time, SWa, SWb third and fourth switching by the differential transistor pair, V _CC ... power supply voltage, GND ... ground potential.

Claims (8)

[Claims] 1. A ring oscillation circuit comprising a plurality of inverting or non-inverting delay circuits connected in series and a final-stage output fed back to an initial-stage input, wherein each base of the delay circuit is connected to an input terminal. A first differential transistor pair whose collectors are respectively connected to an output resistor and an output terminal and whose gain is variable, and each base is respectively connected to an input terminal and an output having a phase opposite to that of the first differential transistor pair A second differential transistor pair that can be obtained by changing the gain, two transistors each having a base connected to one or the other of the outputs of the second differential transistor pair, and the two transistors. A ring oscillation circuit having two capacitors respectively connected between each emitter of the first differential transistor pair and each collector of the first differential transistor pair. 2. The ring oscillation circuit according to claim 1, wherein a current source capable of individually adjusting a current amount is connected to at least each of the common emitter sides of said first or second differential transistor pair. 3. A ring oscillator circuit comprising a plurality of inverting or non-inverting delay circuits connected in series and a final stage output fed back to an initial stage input, wherein each base of the delay circuit is connected to an input terminal. A first differential transistor pair whose collectors are respectively connected to an output resistor and an output terminal and whose gain is variable, and each base is respectively connected to an input terminal and an output having the same phase as that of the first differential transistor pair. A second differential transistor pair, two transistors each having a base connected to one or the other of the outputs of the second differential transistor pair, an emitter of the two transistors and the first transistor, respectively. A ring oscillation circuit having two capacitors respectively connected between the collectors of the differential transistor pair. 4. The ring oscillation circuit according to claim 3, wherein a current source capable of individually adjusting a current amount is connected to at least each of a common emitter side of said first or second differential transistor pair. 5. A ring oscillator circuit comprising a plurality of inverting or non-inverting delay circuits connected in series and a final stage output fed back to an initial stage input, wherein each base of the delay circuit is connected to an input terminal. A first differential transistor pair having respective collectors connected to an output resistor and an output terminal, respectively, and having variable gains; and a base connected to an input terminal, respectively, and having the same or opposite phase as the first differential transistor pair. A second differential transistor pair generating a phase output; a plurality of transistors each having a base connected to one or the other of the outputs of the second differential transistor pair; and switching between the plurality of transistors. A switching circuit for operating and selectively extracting an output having the same phase or the opposite phase as the second differential transistor pair from their emitters; Ring oscillator circuit having a plurality of capacitors respectively connected between the collectors of the first differential transistor pair and the emitter of the data. 6. The ring oscillation circuit according to claim 5, wherein a current source capable of individually adjusting a current amount is connected to at least each of the common emitter sides of said first or second differential transistor pair. 7. A total of four transistors for extracting the output of the second differential transistor pair are provided, and as the switching circuit, a second one of the four transistors is selected in accordance with an input selection signal. The third and fourth differential transistor pairs for selecting two transistors that take out the in-phase or the opposite-phase output from the differential transistor pair are connected to the emitters of the four transistors. A ring oscillator circuit as described. 8. The ring oscillation circuit according to claim 6, wherein a current source capable of adjusting a current amount is connected to each of the common emitter sides of said third or fourth differential transistor pair.