JPH11111744A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH11111744A
JPH11111744A JP29042897A JP29042897A JPH11111744A JP H11111744 A JPH11111744 A JP H11111744A JP 29042897 A JP29042897 A JP 29042897A JP 29042897 A JP29042897 A JP 29042897A JP H11111744 A JPH11111744 A JP H11111744A
Authority
JP
Japan
Prior art keywords
resin
cavity
cavities
circuit board
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29042897A
Other languages
Japanese (ja)
Inventor
Keiji Takai
啓次 高井
Atsushi Shiraishi
淳 白石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP29042897A priority Critical patent/JPH11111744A/en
Publication of JPH11111744A publication Critical patent/JPH11111744A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To improve productivity, by pouring resin into a first cavity through a runner gate from a plurality of pots in a forming die and into the cavities other than the first cavity through connecting gates formed so as to connecting the cavities on a printed substrate. SOLUTION: Grooves, each of which is formed for making a part of wiring pattern region sealed with resin as a package 6 on a printed substrate 1 communicate with a part of the other wiring pattern region, are formed such that the ends thereof are included in cavities 7, thereby forming connecting gates 5. Resin is poured into the cavities through the connecting gates 5 and hence resin flowing through the connecting gates 5 is formed only in a level flush with the printed substrate 1 after the packages 6 are formed. This can substantially reduce a load applied to a punching device to easily punch the printed substrate 1 and improve the wear resistance of the punching device to elongate a punching life, which improves productivity.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体パッケージ
の個別分断の際に生じる不具合を防止する半導体装置の
製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device for preventing a problem that occurs when an individual semiconductor package is cut.

【0002】[0002]

【従来の技術】半導体装置の樹脂方法としては、一般的
にトランスファモールド法と呼ばれる樹脂封止方法が広
く用いられている。これを以下、図3を参照しつつ説明
する。
2. Description of the Related Art As a resin method for a semiconductor device, a resin sealing method generally called a transfer molding method is widely used. This will be described below with reference to FIG.

【0003】図3(a)において、プリント基板1には
複数個に亘って半導体素子が配列形成されている。この
ようなプリント基板1が成形金型2内に載置された状態
でプリント基板1の長手方向に沿った外側に配設した複
数個のポット(図示せず)内の樹脂タブレットを複数個
のプランジャ3でそれぞれ加圧する。ここで加熱溶融し
た樹脂Eは前記プランジャ3の加圧によって、成型金型
2のランナ4に流れ、さらにこのランナ4に連続するゲ
ート5を通して第1パッケージ6aを形成する第1キャ
ビティ7aに流れ込む。そして、成型金型2の各キャビ
ティ間を連通している連結ゲート8aを通して、第2パ
ッケージ6bを形成する第2キャビティ7bに流れ、さ
らに連結ゲート8bを通して第3パッケージ6cを形成
する第3キャビティ7cに流れ込む。このようにして各
パッケージ6a、6b、6cが完成し、この後の最終工
程において、カッティング装置により各パッケージはプ
リント基板1より個別分断される。
In FIG. 3A, a plurality of semiconductor elements are arrayed on a printed circuit board 1. A plurality of resin tablets in a plurality of pots (not shown) disposed outside along the longitudinal direction of the printed board 1 in a state where the printed board 1 is placed in the molding die 2 are connected to the plurality of resin tablets. Each pressure is applied by the plunger 3. The resin E heated and melted here flows into the runner 4 of the molding die 2 by the pressure of the plunger 3, and further flows into the first cavity 7a forming the first package 6a through the gate 5 connected to the runner 4. Then, it flows to the second cavity 7b forming the second package 6b through the connection gate 8a communicating between the respective cavities of the molding die 2, and further flows to the third cavity 7c forming the third package 6c through the connection gate 8b. Flow into In this manner, the packages 6a, 6b, and 6c are completed, and in a subsequent final step, the packages are individually cut from the printed circuit board 1 by a cutting device.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、上記の
ような樹脂方法では、各キャビティ間を連通して樹脂を
注入させる連結ゲート8a、8bが成型金型2の上型側
に形成されているため、同図(b)に示すように、樹脂
封止による各パッケージ形成後も前記連結ゲートを流れ
た樹脂がプリント基板1上に残留樹脂Mとして残ってし
まう。この残留樹脂樹脂Mは、最終工程におけるパッケ
ージ個別分断時にパンチに余分な負荷を与えて打抜性を
阻害し、打抜の際に残留樹脂M近辺のプリント基板に潰
れを生じさせたり、また、パンチの摩耗を招来して打抜
ライフを縮める等、生産性を低下させる要因となってい
る。
However, in the above-described resin method, the connecting gates 8a and 8b that allow the resin to be injected through the cavities are formed on the upper mold side of the molding die 2. As shown in FIG. 2B, the resin flowing through the connection gates remains as the residual resin M on the printed circuit board 1 even after each package is formed by resin sealing. This residual resin resin M imposes an extra load on the punch at the time of individual cutting of the package in the final process, impairs the punching property, and causes the printed circuit board near the residual resin M to be crushed during punching, This causes abrasion of the punch and shortens the punching life, which is a factor that lowers productivity.

【0004】本発明は、前記実情に鑑みてなされたもの
で、各パッケージの個別化の際にプリント基板に潰れを
生じさせることもなく、また、パンチの摩耗を低減させ
ることによって、生産性の向上に寄与する半導体装置の
製造方法を提供することを目的とする。
The present invention has been made in view of the above circumstances, and does not cause the printed circuit board to be crushed when each package is individualized, and reduces the wear of the punch to improve the productivity. It is an object of the present invention to provide a method for manufacturing a semiconductor device which contributes to improvement.

【0005】[0005]

【課題を解決するための手段】上記目的を達成する請求
項1記載の発明は、上面に配線パターンが形成され、こ
の配線パターンと電気的に接続された半導体チップを複
数個に亘って配列形成して成るプリント基板を成型金型
にセットし、この成型金型の各キャビティに樹脂を注入
して前記半導体チップを封止する半導体装置の製造方法
であって、前記成型金型内の複数のポットからランナ、
ゲートを通して第1キャビティに樹脂を注入し、前記プ
リント基板に各キャビティを連通するように形成された
連結ゲートを通して、前記第1キャビティ以降の各キャ
ビティに樹脂を注入することを特徴とする半導体装置の
製造方法にある。
According to the first aspect of the present invention, a wiring pattern is formed on an upper surface, and a plurality of semiconductor chips electrically connected to the wiring pattern are formed and arranged. A method of manufacturing a semiconductor device in which a printed circuit board is set in a molding die, and a resin is injected into each cavity of the molding die to seal the semiconductor chip. Runner from the pot,
A semiconductor device, wherein a resin is injected into the first cavity through a gate, and the resin is injected into each cavity after the first cavity through a connection gate formed so as to communicate each cavity with the printed circuit board. In the manufacturing method.

【0006】[0006]

【発明の実施の形態】以下、本発明による一実施例につ
いて添付図面を参照しつつ詳細に説明する。図1の
(a)乃至(c)は、本発明による半導体装置の製造方
法の第一の実施例を示す図であり、図2は本発明による
第二の実施例を示す図である。まず、図1(a)におい
て、例えばガラスクロスエポキシ樹脂、BTレジン等か
ら成るプリント基板1の上面には単位毎に独立機能を有
する複数の配線パターンが形成され、この配線パターン
と電気的に接続された半導体チップが複数個に亘って配
列形成されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below in detail with reference to the accompanying drawings. 1A to 1C are diagrams showing a first embodiment of a method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a diagram showing a second embodiment according to the present invention. First, in FIG. 1A, a plurality of wiring patterns having an independent function are formed for each unit on the upper surface of a printed board 1 made of, for example, glass cloth epoxy resin, BT resin, etc., and are electrically connected to the wiring patterns. Semiconductor chips are arranged in a plurality.

【0007】そして、上記プリント基板1を成型金型2
の下型Lに形成された凹部にセットし、上型Uを下降さ
せて型締した状態でプリント基板1の長手方向に沿った
外側に配設された複数個のポット(図示せず)内の各樹
脂タブレットを、複数個のプランジャ3でそれぞれ加圧
する。ここで加熱溶融した樹脂Eはプランジャ3の加圧
により、成型金型2の上型Uのランナ4を流れ、さらに
このランナ4に連続するゲート5を通して第1パッケー
ジ6aを形成する第1キャビティ7aに注入される。
Then, the printed circuit board 1 is formed into a molding die 2.
Is set in a concave portion formed in the lower mold L, and the upper mold U is lowered to clamp a mold in a plurality of pots (not shown) disposed outside along the longitudinal direction of the printed circuit board 1. Are pressed by a plurality of plungers 3 respectively. The resin E heated and melted here flows through the runner 4 of the upper mold U of the molding die 2 by the pressure of the plunger 3, and further passes through the gate 5 connected to the runner 4 to form the first cavity 7a forming the first package 6a. Is injected into.

【0008】つづいて、第1キャビティ7aに注入され
た樹脂Eは、この第1キャビィティ7aと第2キャビテ
ィ7b間を連通するようにプリント基板1に溝状に形成
された連結ゲート8aを通って、第2パッケージ6bを
形成する第2キャビティ7bに注入され、さらに前記同
様に第2キャビティ7bより連結ゲート8bを通って第
3パッケージ6cを形成する第3キャビティ7cに注入
される。このようにして各キャビティ7a、7b、7c
に樹脂が充填され、同図(b)に示すような各パッケー
ジ6a、6b、6cが完成する。
Subsequently, the resin E injected into the first cavity 7a passes through the connecting gate 8a formed in the groove on the printed circuit board 1 so as to communicate between the first cavity 7a and the second cavity 7b. Is injected into the second cavity 7b forming the second package 6b, and further injected from the second cavity 7b into the third cavity 7c forming the third package 6c through the connection gate 8b. Thus, each cavity 7a, 7b, 7c
Is filled with resin, and the packages 6a, 6b, 6c as shown in FIG.

【0009】上記のように、本発明では連結ゲートが上
型のキャビティ間を連通するものではなく、プリント基
板上のパッケージとして樹脂封止される配線パターン領
域の一部と、他の配線パターン領域の一部とを連通する
ように形成された溝部の端部をそれぞれのキャビティ内
に含むようにして、これを連結ゲートとして各キャビテ
ィ間の樹脂の注入を図ることから、連結ゲートを流れた
樹脂が各パッケージ形成後にプリント基板に残留して
も、この残留樹脂はプリント基板と同一の平面となる高
さにしか形成されることがないため、従来に比べパンチ
への負荷を大幅に低減することができることから、プリ
ント基板の打抜を格段に容易にするとともに、打抜が良
好になることにより、パンチの耐摩耗も向上し、打抜ラ
イフがより長く維持されるようになる。
As described above, according to the present invention, the connecting gate does not communicate between the cavities of the upper die, but a part of the wiring pattern area which is resin-sealed as a package on the printed board and another wiring pattern area. The end of the groove formed so as to communicate with a part of the cavity is included in each cavity, and this is used as a connection gate to inject the resin between the cavities. Even if the resin remains on the printed circuit board after the package is formed, this residual resin is formed only at the same height as the printed circuit board, so that the load on the punch can be greatly reduced compared to the conventional method. From this, the punching of the printed circuit board is made much easier, and the better punching improves the wear resistance of the punch and maintains the punching life longer Made to be.

【0010】また、上記ゲート5および連結ゲート8
a、8bは、同図(c)に示すように、樹脂Eの入口
側、出口側が方形キャビティの対峙する角部近傍にそれ
ぞれ形成されることにより、キャビティ内の樹脂の回り
込みを良好にしている。
The gate 5 and the connecting gate 8
As shown in FIG. 3C, the inlets a and 8b are formed near the corners of the rectangular cavity facing the entrance side and the exit side of the resin E, respectively. .

【0011】なお、連結ゲート8a、8bは樹脂の流動
性を考慮し、側端面をテーパー状に形成する他、Rを付
けてもよい。
The connection gates 8a and 8b may be formed in a side end surface in a tapered shape in consideration of the fluidity of the resin, or may be provided with an R.

【0012】さらに、樹脂注入が行われる最終キャビテ
ィ部分のプリント基板に、連結ゲート同様のダミー溝を
設けて、これをエア抜きとすることもできる。
Furthermore, a dummy groove similar to the connection gate may be provided on the printed circuit board in the final cavity portion where the resin is injected, and this may be used to release air.

【0013】さらにまた、上記連結ゲート8a、8b
は、プリント基板に溝状をなすように形成されている
が、これを図2に示すようにスリット状に形成してもよ
く、この場合も上記実施例同様の樹脂注入が可能であ
る。
Further, the connection gates 8a, 8b
Is formed in a groove shape on the printed circuit board, but may be formed in a slit shape as shown in FIG. 2, and in this case, resin injection similar to the above embodiment is possible.

【0014】[0014]

【発明の効果】以上説明したように、本発明では各キャ
ビティ間に樹脂を連通させる連結ゲートを上型ではな
く、プリント基板の各パッケージの角部近傍で連通する
溝状に形成しているため、各パッケージ形成後も前記連
結ゲート部分の残留樹脂がプリント基板の平面より、突
出した高さとなることがない。従って、各パッケージの
個別分断の際においても、パンチに余分な負荷を与えず
打抜性に影響を及ぼすことがなくなり、プリント基板に
潰し生じさせることなく切断が良好に実施され、また、
パンチの耐摩耗性も向上し、打抜ライフをより長く維持
することが可能となった。このような結果、半導体装置
の生産性の向上を図ることができた。
As described above, according to the present invention, the connecting gate for communicating the resin between the cavities is formed not in the upper die but in a groove shape communicating with the vicinity of the corner of each package of the printed circuit board. After the formation of each package, the height of the resin remaining in the connection gate portion does not protrude from the plane of the printed circuit board. Therefore, even in the case of individual cutting of each package, an extra load is not given to the punch and the punching property is not affected, and the cutting is favorably performed without crushing the printed circuit board.
The abrasion resistance of the punch has also been improved, making it possible to maintain a longer punching life. As a result, the productivity of the semiconductor device can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示す半導体装置の製造方法FIG. 1 shows a method of manufacturing a semiconductor device according to an embodiment of the present invention.

【図2】本発明の他の実施例を示す半導体装置の製造方
FIG. 2 shows a method of manufacturing a semiconductor device according to another embodiment of the present invention.

【図3】従来技術による半導体装置の製造方法を示す図FIG. 3 is a diagram showing a method of manufacturing a semiconductor device according to a conventional technique.

【符号の説明】[Explanation of symbols]

1、プリント基板 2、成型金型 3、プランジャ 4、ランナ 5、ゲート 6、パッケージ 7、キャビティ 8、連結ゲート 1, printed circuit board 2, molding die 3, plunger 4, runner 5, gate 6, package 7, cavity 8, connection gate

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 上面に複数の配線パターンが形成され、
この配線パターンと電気的に接続された半導体チップを
複数個に亘って配列形成して成るプリント基板を成型金
型にセットし、この成型金型の各キャビティに樹脂を注
入して前記半導体チップを封止する半導体装置の製造方
法であって、 前記成型金型内の複数のポットからランナ、ゲートを通
して第1キャビティに樹脂を注入し、前記プリント基板
に各キャビティを連通するように形成された連結ゲート
を通して、前記第1キャビティ以降の各キャビティに樹
脂を注入することを特徴とする半導体装置の製造方法。
1. A plurality of wiring patterns are formed on an upper surface,
A printed circuit board formed by arranging a plurality of semiconductor chips electrically connected to the wiring pattern is set in a molding die, and a resin is injected into each cavity of the molding die to remove the semiconductor chip. A method for manufacturing a semiconductor device to be sealed, comprising: injecting a resin from a plurality of pots in a molding die through a runner and a gate into a first cavity to communicate each cavity with the printed circuit board. A method of manufacturing a semiconductor device, comprising: injecting a resin into each cavity after the first cavity through a gate.
JP29042897A 1997-10-06 1997-10-06 Manufacture of semiconductor device Pending JPH11111744A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29042897A JPH11111744A (en) 1997-10-06 1997-10-06 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29042897A JPH11111744A (en) 1997-10-06 1997-10-06 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH11111744A true JPH11111744A (en) 1999-04-23

Family

ID=17755915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29042897A Pending JPH11111744A (en) 1997-10-06 1997-10-06 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH11111744A (en)

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