JPH11109060A - Electronic timepiece - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce consumption power and to enable self-rise of an initial time, by switching a part of a time piece electronic circuit or the whole power source between a battery voltage and a voltage conversion means output voltage on the basis of an operation state detection result. SOLUTION: Consumption power is suppressed to the two squares of the voltage rate of both as compared with a case directly driven battery voltage on a part, by supplying lower voltage Vdown generated with a voltage conversion means 102 as a power source Vwatch of an information processing part 110 of a timepiece circuit. An operation state detection means 103 detects the operation state of the conversion means 102, and the switching suppression of power source voltage for the processing part 110 is performed with a power source switching means 104 on the basis of a detection result. The conversion means 102 for generating no initial drive signal ϕClK does not operate, this is detected with the detection means 103, and switching of the power source for voltage Vss is performed. A power source switching circuit 104 is provided, so that self-rise is enabled in an initial state, and a conventionally needed sub- oscillator operated with battery voltage as a power source can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low power consumption electronic timepiece.

[0002]

2. Description of the Related Art It is very important to reduce the power consumption of a watch electronic circuit in which a long-term operating life must be ensured by using a battery having a limited volume as a power supply.
In a conventional timepiece circuit, a voltage regulation circuit 1100 generates a voltage Vreg lower than an electric energy supply source (hereinafter abbreviated as battery) voltage Vss as shown in FIG. Driving reduces power consumption.

[0003] Referring to FIG.
00 is for obtaining a constant low voltage from the battery voltage Vss by an equivalent variable resistor. For example, a configuration as shown in FIG. 12 is often used in a clock circuit. The reference signal generating mechanism 105 is a reference signal source of a timepiece, and usually uses a crystal oscillation circuit. The unit signal synthesizing mechanism 106 divides the reference signal and serves as a unit of time measurement, for example, 1 Hz for a home timepiece and 100 H for a chronograph timepiece.
Generate a signal like z. Energy conversion mechanism 107
Converts electric energy into mechanical energy for driving the hour, minute and second hands, and a step motor using electromagnetic induction is usually used. Note that the configuration shown in FIG. 11 is the simplest. In an actual timepiece circuit, circuits for performing various functions are provided.
These are, for example, a frequency adjustment circuit or a load generation type motor control pulse generation circuit which was a temperature error assurance circuit.

A portion of the clock circuit component using an electric signal as information processing means (the information processing section 11 in FIG. 11).
Regarding 0), power consumption can be reduced by compressing the power supply voltage. Since the current consumption of an electronic circuit composed of CMOS elements is proportional to the product of the power supply voltage and the operating frequency, the power supply voltage of the oscillator circuit and the first half of the frequency divider circuit, especially at the high operating frequency, is compressed using a regulating circuit. Doing so greatly contributes to a reduction in power consumption.

[0005] Of the clock circuit components, the energy conversion mechanism 107 that uses an electric signal as energy does not depend on the power supply voltage value, and therefore, it is generally driven directly by a battery voltage. It is of course possible to drive with the rate voltage Vreg. The regulation circuit 1100 also has a function of securing an operation margin of the circuit against fluctuations in the battery voltage Vss due to consumption of the battery and changes in the circuit load of the timepiece.

However, in the conventional timepiece circuit using the above-described voltage regulation circuit, there is a problem that a difference voltage between the battery voltage Vss and the regulation voltage Vreg is wasted as a loss of equivalent resistance. For example, the regulation circuit output voltage Vreg is １ ／ of the battery voltage Vss.
In this case, twice as much power as is originally required in the regulation circuit driving portion is actually consumed.

As a means for solving the above-mentioned problem, a method of generating a low voltage from a battery voltage by voltage conversion means by changing a capacitor and driving a watch electronic circuit by the low voltage has been proposed in Japanese Patent Application Laid-Open No. 2-40371. ing. The configuration described in this publication is shown in FIG. Voltage conversion means 13
01 is a low-voltage circuit that does not generate energy loss due to the potential difference between the input and output, unlike the regulator circuit using equivalent resistance, by rearranging capacitors and repeating energy storage and transfer according to the voltage difference between the input and output. By driving the clock circuit information processing unit 110 using the low voltage Vdown generated by the method as a power supply, the power consumption is further reduced as compared with the conventional clock circuit. The voltage conversion means 1301 calculates the battery voltage Vs
It is driven by a sub-signal which is always output by a sub-signal generating means 1300 using s as a power source.

[0008]

However, in the configuration disclosed in the above publication, large power is consumed in the sub-signal generating means 1300 for driving the voltage converting means 1301, and the power saving effect of the low voltage driving is offset. There is a problem that will be done. In the configuration of the publication, a ring oscillator circuit and a crystal oscillation circuit are described as specific examples of the sub-signal generating means 1300.
Since analog signal operation is performed on the MOS element,
The power consumption accompanying the driving is much larger than that of a normal logic circuit, and the signal generating means 1300 is always driven by using the battery voltage Vss as a power source. As a result, the power consumption of the entire clock circuit is greatly increased. It is expected that SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic timepiece capable of self-starting in an initial state while reducing power consumption in a normal state.

[0009]

In order to achieve the above object, an electronic timepiece according to the present invention is driven by a time reference signal or a frequency-divided signal of the signal to generate a voltage having a value lower than the energy supply voltage. Means, a detecting means for detecting an operation state of the voltage conversion means, and a power supply for a part or the whole of the electronic circuit for a watch is switched between a battery voltage and an output voltage of the voltage conversion means based on the operation state detection result. It is characterized by comprising a power supply switching means. The electronic timepiece according to another aspect of the invention includes a voltage conversion unit that generates a voltage having a value lower than the energy supply voltage, a unit that detects an operation state of the voltage conversion unit, and an auxiliary unit that is driven using the battery voltage as a power supply. Based on the signal generation means and the operation state detection result,
The voltage conversion means includes signal switching means for switching a drive signal between a reference signal or its divided signal and a sub-signal, and the sub-signal generation means operates when the reference signal or its divided signal is selected as a drive signal. Is stopped.

[0010]

Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a basic configuration of an electronic timepiece according to the present invention. The voltage conversion means 102 is driven by the reference signal or the frequency-divided signal φclk of the signal, and outputs the battery voltage Vss
Is a so-called step-down switching regulator for converting the voltage to a lower voltage Vdown. A chopper type regulator using a coil or a charge pump type regulator by changing a capacitor can be considered. It is preferable to use a charge pump type regulator from the viewpoint of low power.

[0011] The low voltage Vdown generated by the voltage conversion means 102 is converted to the power supply Vw of the information processing section 110 of the clock circuit.
By supplying the power as an “ach”, the power consumption in the part can be suppressed to one half of the square of the voltage ratio between the two as compared with the case where the battery is directly driven by the battery voltage. In a conventional configuration using a regulator circuit using an equivalent variable resistor, the reduction in power consumption compared to battery voltage driving is only one-first power of the voltage ratio between the two, so that the smaller the converted voltage value, the more the conventional The power saving effect of the present invention is greater than that of the configuration.

The operating state detecting means 103 is a voltage converting means 1
02, the switching control of the power supply voltage to the clock circuit information processing unit 110 is performed based on the detection result.
This is performed in the power supply switching unit 104. That is, in the state where the normal operation of the voltage conversion unit 102 is detected, the conversion unit output voltage Vdown is selectively supplied as the power supply Vwatch of the clock circuit information processing unit 110, but the abnormal operation of the voltage conversion unit 102 is detected. In this case, the battery voltage Vss is directly supplied as the power source of the information processing unit 110. As the operation state detection means 103, a signal generation detection circuit for detecting the presence or absence of the drive clock signal φclk, a voltage detection circuit for detecting the voltage value of the conversion means output voltage Vdown, and the like can be considered.

In the above-described clock circuit, when the clock circuit is stopped due to battery shortage and a normal battery voltage is supplied again by battery replacement, charging, or the like, the self-starting operation by power supply switching described below is performed. Done. Since the drive signal φclk is not initially generated, the voltage conversion means 10
The operation 2 is not performed, and this is detected by the operation detecting means 103, and the power supply is switched to the battery voltage Vss. The operation of the clock circuit information processing unit 110 is started using the battery voltage Vss as a power supply, and the driving signal φc
When lk starts to be output, the voltage conversion means 10
2 is also started, and the output voltage Vdown starts to be generated. Thereafter, the detecting means 103 detects the voltage conversion means 1
02 is detected to have reached the normal operation state, the information processing unit 110 power supply Vwatch changes the conversion unit output voltage Vd.
The driving of the information processing unit 110 is continued by the conversion unit output voltage Vdown unless the operation of the conversion unit 102 is abnormal.

If the clock circuit information processing section 110 including the drive clock generation section is always driven by the conversion means output voltage Vdown as a power supply, once the power supply is in a power-deficient state, the normal battery voltage thereafter becomes low. Even if given, both the voltage conversion circuit and the clock circuit are not permanently driven, as in the chicken and egg analogy. By providing the power supply switching circuit having the above configuration, self-startup in an initial state becomes possible, and it becomes possible to omit a conventionally required auxiliary oscillator using a battery voltage as a power supply.

Although the power supply of the entire information processing unit 110 is switched in the configuration of FIG. 1, the minimum switching is required for the drive signal generation unit including a reference signal generation mechanism and a part of a frequency dividing circuit. The power supply of the other information processing units including circuits not shown may always be the voltage conversion unit output voltage Vdown. A configuration is also possible in which the entire clock circuit including the energy conversion mechanism 107 is to be switched over.

FIG. 2 shows a specific circuit example of the present invention. The circuit of FIG. 2 shows the most basic case of 1/2 voltage division for simplification of description, and uses a drive signal detection circuit as an operation state detection means. The voltage converter 202 connects two capacitors in series to store energy, and then connects them in parallel to average the potential difference between both ends of the capacitors to generate a voltage value of １ ／ of the power supply voltage. As long as the capacitor has a small capacity, it can be built in the integrated circuit for a watch, but using a capacitor with a large value of about 1 uF externally reduces the ripple of the output voltage,
Also, conversion efficiency is improved. The frequency of the voltage converter drive signal is usually about 100 Hz to 1 KHz, and is determined by the relationship between the value of the capacitor, the allowable ripple amount, the power consumption, and the like. By increasing the frequency, the ripple can be suppressed small, but the through current of each FET increases, so that the power consumption increases. 32.7 in a normal clock circuit
A 68 KHz crystal oscillator is oscillated to generate a time reference signal, which is frequency-divided into 15 steps to generate a 1 Hz clock unit signal. The driving signal φ of the voltage conversion unit 202
It is possible to optimize this trade-off by choosing it as clk. FE constituting voltage conversion section 202
As for T, it is important to select a transistor having a larger value of W (channel width) / L (channel length) than that used in a normal logic circuit to minimize the loss due to the on-resistance of the FET. Level shifter 20 like the circuit of FIG.
Signal φcl raised to battery voltage Vss level by 1
Driving at kss is also effective in reducing on-resistance. By appropriately selecting a capacitor, a drive signal frequency, an FET, and the like, the conversion efficiency of the conversion circuit can achieve a high value of about 99% near the optimum voltage value and 95% or more in the entire voltage range average. .

The drive signal detector comprises a detection signal generator 203 and a signal stop detector 204, and operates as shown in the flowchart of FIG. Detection signal generator 2
Numeral 03 is a logical sum of a drive signal φclkss and a delay signal by a flip-flop composed of a W / L small FET, and has a signal width corresponding to the delay amount when the input is a continuous pulse signal. Although a pulse signal is output, when the input is a DC signal, the output signal φpulse is fixed at a low level regardless of whether the signal is a high or low level. In this state, the stop detection unit output φswt is fixed at a high level, and the power supply switch 205 is kept on. (Fig. 3 first half)

When the drive signal starts to be continuously input from the state described above, the stop detection unit output φstop becomes the signal shown in FIG.
As shown in the above, when the level gradually lowers and exceeds the threshold potential of the subsequent-stage inverter, the level of φswt is inverted and maintained at a high level thereafter, and the changeover switch is kept in the off state. Although a voltage higher than the target voltage Vss / 2 is output as the output of the voltage conversion unit 202 at the time of power switching, the voltage gradually shifts to the Vss / 2 potential due to the influence of the load and the capacitor rearrangement operation. Note that the drive signal detection circuit shown in FIG. 2 is an example, and various other known configurations can be used.

FIG. 4 shows a circuit example using a voltage detection circuit as the operation state detection means. The voltage detection unit 403 includes a P-channel and an N-channel FE to which the drain is connected.
Input the voltage conversion unit output voltage Vdown to the gate of T,
In this configuration, voltage detection is performed based on the difference between the two on-resistances. That is, by making the W / L of the P-channel FET larger than that of the N-channel, the output φswtA of the detector becomes a high level in the normal state where the conversion unit voltage Vdown is at or near １ ／ of the battery voltage Vss. The switch A404 is kept off and the switch B405 is kept on. When the conversion unit output voltage Vdown becomes lower than a predetermined value, the detection unit output φswtA becomes low level, the switch A404 is turned on, and the switch B4 is turned on.
05 is turned off, and the battery voltage Vss is supplied as the clock circuit power supply Vwatch.

In the voltage detection circuit having the configuration shown in FIG. 4, the intermediate potential Vs is always supplied to the voltage detection inverter in the normal operation state.
Since s / 2 is input, there is a possibility that a large amount of through current will flow in the location. To prevent this, W / L (P)>
It is important to use both FETs with extremely small W / L while maintaining the relationship of W / L (N), and insert a FET for adding potential between Vss and N-FET,
A device for reducing the potential between the gate and the source of the N-FET is also effective for reducing the through current.

In the circuit shown in FIG.
In some cases, 405 can be omitted. When the output voltage of the conversion unit 402 becomes smaller than a predetermined value in a configuration in which the switch B405 is omitted, the battery voltage Vss becomes Vwa.
tch, and this voltage is supplied to the voltage detector 40
3 and the voltage Vwatch is eventually stabilized at the power supply switching setting voltage Vth.
Switch B only when the clock circuit can be started with
405 can be omitted. Further, by providing the voltage detection unit 403 with hysteresis so that the input potential at the time of low output is higher than the input potential of high output, the range in which the switch B405 can be omitted is expanded. Further, as the simplest configuration, there is a case where a power supply can be switched by providing a diode having both a voltage detection function and a changeover switch function between Vss and Vwatch. However, since the voltage drop amount of a diode generally changes greatly depending on the current value, the above configuration can be used only when the operation margin of the clock circuit can be ensured even when the voltage change of Vwatch is large.

The voltage detecting means shown in FIG. 4 is an example. In addition, for example, a configuration in which the battery voltage Vss and the output voltage Vdown of the voltage conversion circuit are divided by resistance and compared by a voltage comparison circuit has been known. The various configurations described are available. Further, the voltage conversion circuits described above all have 1/2 voltage division,
The present invention can be similarly applied to a (1 / n) voltage conversion circuit, and can also be applied to an arbitrary integer (m / n) voltage conversion circuit of an arbitrary integer obtained by combining a booster circuit and a voltage divider circuit. It is equally adaptable. It is to be noted that all of the above-described circuit configurations including the voltage conversion circuit can be formed in the integrated circuit for a timepiece except for a part thereof, and the present invention does not greatly increase the number of components of the electronic timepiece.

It is also effective to further stabilize the converted voltage Vdown by the regulation circuit 1100 as shown in FIG. In this case, the difference voltage between the converted voltage Vdown and the regulated voltage Vreg is a loss,
This is a much smaller loss than the difference voltage between Vss and Vreg in the configuration of the related art. FIG.
As shown in (2), there is a method of comparing the output voltage Vdown of the voltage conversion circuit with the voltage of the reference voltage source 601 and performing feedback control to keep the output voltage value constant.

In the above invention, the self-startup in the initial state and the low-power operation in the steady state can both be achieved by the power supply switching control of the clock circuit information processing unit. It can also be obtained by a configuration in which the drive signal is switched between a sub-signal from a sub-oscillator driven by using the battery voltage as a power supply and a reference signal or a frequency-divided signal of the signal. Hereinafter, a second embodiment having this configuration will be described.

FIG. 7 shows a basic configuration diagram of the present invention. The voltage converter 102 converts the battery voltage Vss to a lower voltage Vd.
The clock circuit information processing unit 110 is constantly driven using the voltage as a power supply. Operating state detecting means 103
Detects the operation state of the voltage conversion means 102, and the drive signal switching means 702 switches the drive signal φclk of the voltage conversion means 102 based on the detection result. That is, when an abnormal operation of the voltage conversion means is detected, the sub-signal φclk generated by the sub-oscillator 701 is output.
The sub signal is selected as the drive signal φclk. When the normal operation of the voltage conversion means is detected, the reference signal or the divided signal φclkm of the reference signal is used as the drive signal φclk.
In this state, the operation of the sub oscillator 701 is stopped. The sub-oscillator 701 is a continuous clock generation circuit driven by the battery voltage Vss, and is realized by a ring oscillator circuit, a crystal oscillation circuit, a CR oscillation circuit, or the like.

In the clock circuit having the configuration shown in FIG. 7, after the clock circuit is stopped due to battery shortage, if a normal battery voltage is applied again, the following self-starting operation is performed. At first, the voltage conversion means 102 is not operated, and this is detected by the operation detection means 103, and the drive signal φclksub from the sub oscillator 701 is selected as the drive signal φclk. The operation of the voltage conversion means 102 is started by the drive signal, and thereafter, when the detection circuit 103 detects that the voltage conversion means 103 is in a normal operation state, the drive signal φclk becomes the reference signal or its divided signal φclkma.
In addition, the operation of the sub-oscillator 701 is stopped. That is, the sub-oscillator 701 that consumes a large amount of power is used only at the time of self-starting, and its operation is stopped in the steady state, thereby enabling both the self-starting in the initial state and the low-power operation in the steady state. Has become.

As the operating means detection circuit 103, a drive signal detection circuit or a voltage detection circuit can be used as described in the first embodiment. Since these are the same as those described in the first embodiment, a detailed description thereof will be omitted. However, when the drive signal detection circuit is used in this configuration, the reference signal or its divided signal φclkmmain must be detected. .

FIG. 8 shows a specific circuit example of the sub-oscillator 701 and the drive signal switching means 702. In the circuit shown in FIG. 8, a ring oscillator circuit 801 using a battery voltage Vss as a power supply is used as a sub-oscillator. I'm thinking about output.

The operation of the circuit of FIG. 8 will be described with reference to the timing chart of FIG. Φs when voltage conversion means operates abnormally
The signal wt is at the low level, and the sub-signal φclksub is output as the converter driving clock φclk. When the normal operation of the voltage conversion means is detected, φswt goes high (1 in FIG. 9), and the driving signal φclk becomes φclkma.
can be switched to in. At the time of clock switching, the flip-flops 802 and 803 control the control signal φs
By performing switching by synchronizing wt with the falling edge of its own clock signal, safe switching while maintaining the clock signal width can be performed. However, since the voltage converter driven by φclk is less affected by noise and the like than a normal logic circuit, the synchronization unit can be omitted in many cases. The sub-oscillator stop signal φstop is generated by delaying the switching signal φswt, and φclkm
The operation of the sub-oscillator 801 is stopped (2 in FIG. 9) after the switching of the drive signal to “in” is surely completed. An output level fixing FET 804 which is effective at the time of stop so that the output level at the time of stopping the sub-oscillator 801 when the power is turned off does not become unstable is provided.

In the circuit shown in FIG. 8, the operation of the sub-oscillator is stopped by stopping the supply of power. However, as shown in FIG. 9, operation stop control by fixing the level is also possible. The same applies to the case of using.

[0031]

As described above, the electronic timepiece of the present invention can reduce the power consumption in the normal state and can start up in the initial state.

[Brief description of the drawings]

FIG. 1 is a drawing showing a configuration of an electronic timepiece according to an embodiment of the present invention.

FIG. 2 is a diagram showing a specific circuit example of the electronic timepiece according to the embodiment of the present invention.

FIG. 3 is a diagram showing a timing chart of a circuit of the electronic timepiece according to the embodiment of the present invention.

FIG. 4 is a drawing showing another example of a circuit of the electronic timepiece according to the embodiment of the present invention.

FIG. 5 is a drawing showing another configuration of the electronic timepiece according to the embodiment of the present invention.

FIG. 6 is a diagram illustrating a circuit example of a voltage conversion unit using feedback control of the electronic timepiece according to the embodiment of the present invention.

FIG. 7 is a drawing showing an electronic timepiece according to an embodiment of the present invention.

FIG. 8 is a drawing showing an electronic timepiece according to an embodiment of the present invention.

FIG. 9 is a diagram showing a timing chart of a circuit of the electronic timepiece according to the embodiment of the present invention.

FIG. 10 is a diagram showing a circuit example of a sub-oscillator of an electronic timepiece according to an embodiment of the present invention.

FIG. 11 is a drawing showing a configuration of an electronic timepiece according to the related art.

FIG. 12 is a diagram showing a circuit example of a regulation circuit of an electronic timepiece according to the related art.

FIG. 13 is a drawing showing a configuration of an electronic timepiece according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Battery 102 Voltage conversion means 103 Operation state detection means 104 Power supply switching means 108 Clock electronic circuit 110 Clock circuit information processing part 701 Sub oscillator 702 Signal switching means 1100 Voltage regulation circuit

Claims (4)

[Claims] 1. An electronic timepiece comprising a time reference signal generating mechanism, a clock unit signal synthesizing mechanism, an electromechanical energy converting mechanism, a mechanical counting mechanism, a time display mechanism, an external operating means, and an electrical energy supply, Voltage conversion means driven by the time reference signal or the frequency-divided signal of the signal to generate a voltage lower than the energy supply voltage, detection means for detecting the operation state of the voltage conversion means, and based on the operation state detection result An electronic timepiece comprising a power supply switching means for switching the power of a part or the whole of the electronic circuit for a watch between a battery voltage and an output voltage of a voltage conversion means. 2. The electronic timepiece according to claim 1, wherein the operation state detection means is a circuit for detecting a generation state of a drive signal of the voltage conversion means. 3. The electronic timepiece according to claim 1, wherein the operating state detecting means is a circuit for detecting an output voltage value of the voltage converting means. 4. An electronic timepiece comprising a time reference signal generating mechanism, a clock unit signal synthesizing mechanism, an electromechanical energy converting mechanism, a mechanical counting mechanism, a time display mechanism, an external operating means, and an electric energy supply source. Voltage conversion means for generating a voltage having a value lower than the supply voltage, detection means for detecting the operation state of the voltage conversion means, sub-signal generation means driven by the battery voltage as a power source, and operation state detection results. Signal switching means for switching a voltage conversion means drive signal between a reference signal or a frequency-divided signal thereof and a sub-signal, and wherein the reference signal or the frequency-divided signal thereof is selected as a drive signal, a sub-signal generation means Is an electronic timepiece whose operation is stopped.