JPH11103060A - Thin film transistor and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor having improved performance and reliability and good characteristics and a manufacturing method therefor. SOLUTION: A gate-insulating film 13 is formed on a semiconductor layer 12 formed on an insulating substrate 11. The gate-insulating film 13 has a first region 13b abutting on the source region 12b of the semiconductor layer 12 and a first region 13c abutting on the drain region 12c thereof, and a second region 13a between the first regions 13b, 13c, which are thicker than the second region. First electrodes 14b, 14c are formed on the gate insulating film 13b, 13c, and a second electrode is formed on the gate-insulating film 13a and the first electrodes 14b, 14c. The first electrodes and the second electrode form a gate electrode 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor applied to, for example, a liquid crystal display and a method for manufacturing the thin film transistor.

[0002]

2. Description of the Related Art In general, a thin film transistor (hereinafter referred to as a TFT) used for a liquid crystal display device or the like is formed on an insulating substrate such as a glass substrate, and amorphous silicon or polysilicon is used for a semiconductor layer. ing.

[0003] T using polysilicon as a semiconductor layer
Since the FT has higher mobility and better semiconductor characteristics than amorphous silicon, the FT is not only a switching element for driving the display unit of the liquid crystal display device for each pixel, but also a driving circuit (mainly composed of a CMOS transistor) for operating the switching element. ) Can be applied. For this reason, the switching element and the driving circuit can be formed on the same glass substrate, which is effective for reducing the size of the liquid crystal display device.

[0004]

However, when polysilicon is applied to a TFT, there are the following problems. The first problem is that since the mobility is high, the drain current multiplication phenomenon easily occurs at the voltage between the source and the drain, and the drain current largely flows, and the TF
The point is that the T characteristic is deteriorated. A second problem is that when light is irradiated, a leak current flows when the TFT is turned off through many defects existing inside the polysilicon. In response to this, attempts have been made to reduce the defects by inactivating the defects with H, but the leak current cannot be sufficiently reduced.

In order to solve these problems, a low impurity concentration region (hereinafter referred to as an LDD) having a lower impurity concentration than the source / drain region is provided between the channel region and the source / drain region having a high impurity concentration. A liquid crystal display device using a polysilicon TFT on which a TFT is formed has been proposed. This LDD region is a polysilicon TFT
In order to obtain good semiconductor characteristics, precise resistance value control is required.

However, in a polysilicon TFT having such an LDD region, control is performed so that the resistance value of the LDD region in a large-area substrate such as a liquid crystal display device having a large display portion is made uniform. It is difficult.
Therefore, the LDD of a TFT formed in a large-area substrate
In the region, there is a variation in the resistance value, and as a result, the variation in the TFT characteristics may be increased, and the performance of the liquid crystal display device may be reduced.

Accordingly, the present invention has been made in view of the above points, and an object of the present invention is to prevent the electric field concentration in the source / drain regions, improve the performance and reliability without forming the LDD region, and improve the characteristics. And a method for manufacturing the thin film transistor.

[0008]

In order to achieve the above object, a thin film transistor according to the present invention is provided on an insulating substrate, and includes a channel region, and a source region and a drain region located on both sides of the channel region. A pair of first regions formed on the semiconductor layer and located near a junction between the channel region and the source region and the drain region and separated from each other; and A gate insulating film having a second region located between the first regions and having a smaller thickness than the first region, and a pair of first electrode portions formed on the first region of the gate insulating film And a second electrode formed on the second region and electrically connecting the pair of first electrode portions.
And a gate electrode having an electrode portion.

Further, according to the method of manufacturing a thin film transistor of the present invention, a polysilicon semiconductor layer is formed on an insulating substrate,
Forming a gate insulating film over the semiconductor layer, forming a pair of first electrode portions at predetermined intervals on the gate insulating film, and etching the gate insulating film using the first electrode portion as a mask; Forming a gate insulating film thin film portion having a thickness smaller than that of the gate insulating film located immediately below the pair of first electrode portions, and forming a pair of the first electrode portions so as to conduct the pair of first electrode portions; Forming a second electrode portion on the gate insulating film thin film portion therebetween to form a gate electrode; implanting impurity ions into the semiconductor layer using the gate electrode as a mask to form a source region and a drain region; Forming an interlayer insulating layer on a gate insulating film and a gate electrode; and forming a source electrode and a drain electrode connected to the source region and the drain region, respectively, on the interlayer insulating layer. A.

According to the thin film transistor and the method of manufacturing the thin film transistor of the present invention, the pair of first regions is located on the source region side and the drain region side of the semiconductor layer, and is located between the pair of first regions. The semiconductor device includes a gate insulating film including a second region, and the pair of first regions is formed to be thicker than the second region. As described above, by increasing the thickness of the gate insulating film corresponding to the junction between the source / drain region and the channel region where the electric field intensity is highest, the electric field intensity near the end of the source / drain region can be suppressed. Thus, it is possible to reduce the leakage current.

Thus, there is provided a thin film transistor capable of preventing electric field concentration at the end of the source / drain region, improving performance and reliability and obtaining good characteristics without forming an LDD region, and a method of manufacturing the thin film transistor. be able to.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a thin film transistor according to an embodiment of the present invention and a method for manufacturing the thin film transistor will be described in detail with reference to the drawings. In addition,
In this embodiment, as an example of a thin film transistor,
A coplanar thin film transistor will be described as an example.

FIG. 1 is a sectional view showing an example of the structure of a thin film transistor according to an embodiment of the present invention. As shown in FIG. 1, a thin film transistor or TFT 10 comprises:
For example, an insulating substrate 11 made of transparent glass is provided, and a semiconductor layer 12 made of polysilicon is formed on a surface of the insulating substrate 11.

The semiconductor layer 12 includes a channel region 12a located in a substantially central region thereof, and a channel region 1a.
Source regions 12b respectively located on both sides of 2a
And a drain region 12c. The source region 12b and the drain region 12c have phosphorus ions (P
⁺ ).

On the surfaces of the semiconductor layer 12 and the insulating substrate 11, a gate insulating film 13 made of a silicon oxide film is formed. This gate insulating film 13 is formed in the channel region 1
Regions 13 as a pair of first regions located on both side edges of 2a, that is, almost immediately above the source region side and the drain region side
b, 13c and the first region 13b of the channel region 12a,
13c, that is, a region 13a as a second region which is located almost immediately above the center of the channel region 12a.

The gate insulating film 13 has a thickness distribution in each of the regions 13a to 13c. In other words, the thickness of the second region, ie, the thin film portion 13a, overlapping near the center of the channel region 12a is smaller than that of the first region, ie, the thick film portions 13b, 13c, which overlaps the source region side and the drain region side of the channel region 12a. Is formed. In this embodiment, the thin film portion 13a has a thickness of about 1000 angstroms and the thick film portions 13b, 13b
The film thickness of c is about 2000 angstroms.

A gate electrode 14 is formed on the gate insulating film 13 so as to face the channel region 12a. The gate electrode 14 is provided on the pair of thick film portions 13b and 13c of the gate insulating film 13, and is disposed on the pair of first electrode portions 14 at predetermined intervals.
b, 14c and the first electrode portion 14b and the first electrode portion 1 provided on the thin film portion 13a of the gate insulating film 13.
4c so that the first electrode portions 14b and 1c are electrically connected to each other.
4c and a second electrode portion 14a disposed on the thin film portion 13a of the gate insulating film 13. The first electrode portions 14b and 14c and the second electrode portion 14a of the gate electrode 14 may be formed of the same metal material or different metal materials.

An interlayer insulating film 15 made of a silicon oxide film is formed on the gate electrode 14. A source electrode 17 and a drain electrode 18 are formed on the interlayer insulating film 15 so as to face the source region 12b and the drain region 12c, respectively. Then, the source electrode 17 and the drain electrode 18 are
The semiconductor layer 12 is electrically connected to the source region 12b and the drain region 12c via a and 16b.

The drain electrode 18 is connected to a pixel electrode made of ITO (not shown). Next, a method for manufacturing a thin film transistor having the above-described structure will be described with reference to FIGS. 2A to 2D and FIGS. 3A and 3B.

First, as shown in FIG. 2A, an amorphous silicon thin film is formed to a thickness of 100 nm on the surface of an insulating substrate 11 made of transparent glass by using a plasma CVD method. Then, the amorphous silicon thin film is annealed by an excimer laser or the like and crystallized to form a polysilicon film. Then, the semiconductor layer 12 is formed by patterning the polysilicon film.

Subsequently, as shown in FIG. 2B, a gate insulating film 13 is formed on the surface of the semiconductor film 12 and the insulating substrate 11.
A silicon oxide film to be 100
It is formed to a thickness of nm.

Subsequently, as shown in FIG. 2C, a metal thin film made of a first metal material, for example, molybdenum-tungsten (Mo-W) is formed on the gate insulating film 13 to a thickness of 200 nm by a sputtering method. Form a film. Then, portions of the metal thin film other than necessary portions such as a position opposed to the semiconductor layer 12 at predetermined intervals are removed by reactive ion etching, that is, RIE, and a pair of first electrode portions 14 b of the gate electrode 14 are removed. 14c is formed. At this time, the first
The surface layer of the gate insulating film 13 other than immediately below the electrode portions 14b and 14c is removed by over-etching, and
The third thin film portion 13a is formed. Thus, a distribution is formed in the thickness of the gate insulating film 13. That is, the pair of thick film portions 13 is provided immediately below the pair of first electrode portions 14b and 14c.
b, 13c, the first electrode portion 14b and the first electrode portion 1
4c is formed with the thin film portion 13a.

Subsequently, as shown in FIG. 2D, the thin film portion 13a of the gate insulating film 13 and the first electrode portion 14 are formed.
b, 14c, a second metal material, for example, a metal thin film made of molybdenum-tungsten (Mo-W) is formed and patterned to form a second electrode portion that is electrically connected to the first electrode portion 14c. 14a is formed.

Thus, the first electrode portions 14b, 14
The gate electrode 14 is formed by c and the second electrode portion 14a. Subsequently, as shown in FIG. 3A, phosphorus ions or the like are implanted into the semiconductor layer 12 in a self-aligned manner using the gate electrode 14 as a mask to form a source region 12b and a drain region 12c. Then, the semiconductor layer 12
Activation is performed by performing a heat treatment at 600 ° C. for 3 hours.

Subsequently, as shown in FIG. 3B, a silicon oxide film serving as an interlayer insulating film 15 is formed on the gate electrode 14 and the gate insulating layer 13 by a plasma CVD method. Further, an ITO film is formed on this interlayer insulating film 15 by 100
Then, a pixel electrode (not shown) is formed by removing ITO other than a necessary portion using a photolithography method. Further, the source region 12 of the semiconductor layer 12 is formed on the gate insulating film 13 and the interlayer insulating film 15 by using photolithography.
b, contact hole 1 opening in drain region 12c
6a and 16b are formed. Thereafter, an aluminum film or an alloy film thereof is formed to a thickness of 400 nm over the interlayer insulating film 15 by a sputtering method, and the source electrode 17 and the drain electrode 18 are removed by removing portions other than the source and drain portions by a photolithography method. Complete the wiring including. At this time, the source electrode 17 is electrically connected to the source region 12b of the semiconductor layer 12 via the contact hole 16a, and the drain electrode 18 is electrically connected to the drain region 12c of the semiconductor layer 12 via the contact hole 16b. It is connected.

Through the above-described manufacturing steps, the thin film transistor 10 as shown in FIG. 1 is completed. According to the thin film transistor configured as described above and the method for manufacturing the thin film transistor, the gate insulating film 13 includes a pair of semiconductor layers 12 located on the side adjacent to the source region 12b and the side adjacent to the drain region 12c. 1st area 1
3b, 13c and a second region 13a located between the pair of first regions 13b, 13c. The first regions 13b and 13c are formed to be thicker than the first region 13a. As described above, by increasing the thickness of the gate insulating film in the source / drain regions where the electric field intensity is highest, the electric field intensity near the edges of the source / drain regions can be reduced and the leak current can be reduced. Become.

Thus, there is provided a thin film transistor capable of preventing electric field concentration in the source / drain region, improving performance and reliability and obtaining good characteristics without forming an LDD region as in the prior art, and a method of manufacturing the thin film transistor. Can be provided.

The present invention is not limited to the above-described embodiment, but can be variously modified within the scope of the present invention. For example, in the above-described embodiment, the polysilicon thin film forming the semiconductor layer is formed by the laser annealing method. However, the active layer may be obtained by solid-phase growing amorphous silicon. In the step of forming the channel region, the source region, and the drain region, an etch-back method using a photoresist is used, but a method of mechanically polishing the surface may be used.

The gate electrode is not limited to a metal thin film formed by a sputtering method, but may be a silicon thin film to which impurities are added. In addition, the n-type thin film semiconductor device using phosphorus as an impurity to be implanted into the semiconductor layer has been described. Is also good.

The interlayer insulating film is not limited to a silicon oxide film formed by a plasma CVD method, but may be a silicon oxide film formed by a thermal CVD method or a sputtering method. In this case, another film can be used instead of the silicon oxide film as long as the film has an insulating property. Further, the source electrode and the drain electrode are made of aluminum,
Not only the alloy thin film but also other conductive materials may be used.

[0031]

As described above in detail, according to the present invention, the electric field intensity near the end of the source / drain region is suppressed and the leakage current is reduced, thereby preventing the electric field concentration in the source / drain region, It is possible to provide a thin film transistor capable of improving performance and reliability and obtaining favorable characteristics without forming a region, and a method for manufacturing the thin film transistor.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an example of a structure of a coplanar thin film transistor according to an embodiment of the present invention.

FIGS. 2A to 2D are cross-sectional views illustrating respective steps of manufacturing the thin film transistor shown in FIG.

3 (a) and 3 (b) are cross-sectional views showing steps of manufacturing the thin film transistor shown in FIG. 1, respectively.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Insulating substrate 12 ... Semiconductor layer 12a ... Channel region 12b ... Source region 12c ... Drain region 13 ... Gate insulating film 13a ... Thin film part 13b, 13c ... Thick film part 14 ... Gate electrode 14a ... Second electrode part 14b, 14c ... 1st electrode part 15 ... Interlayer insulating film 16a, 16b ... Contact hole 17 ... Source electrode 18 ... Drain electrode

Claims (6)

[Claims] A semiconductor layer provided on an insulating substrate and having a channel region, and a source region and a drain region located on both sides of the channel region; and a semiconductor layer formed on the semiconductor layer. A pair of first regions that are located near the junction between the channel region and the source and drain regions and that are spaced apart from each other, and that are located between the pair of first regions and have a smaller thickness than the first region; A gate insulating film having a formed second region; and a pair of first insulating films formed on the first region of the gate insulating film.
A thin film transistor, comprising: an electrode portion; and a gate electrode formed on the second region and having a second electrode portion that conducts the pair of first electrode portions. 2. The thin film transistor according to claim 1, wherein said semiconductor layer is formed of polysilicon. 3. The thin film transistor according to claim 1, wherein the first electrode portion and the second electrode portion of the gate electrode are formed of different metal materials. 4. The thin film transistor according to claim 1, wherein the first region of the gate insulating film is formed to be thicker than other regions of the gate insulating film located on the semiconductor layer. 5. A method according to claim 5, wherein a polysilicon semiconductor layer is formed on the insulating substrate, a gate insulating film is formed on the semiconductor layer, and a pair of first electrode portions are formed on the gate insulating film at predetermined intervals. Etching the gate insulating film using the first electrode portion as a mask to form a gate insulating film thin film portion having a thickness smaller than that of the gate insulating film located immediately below the pair of first electrode portions; The first pair of first electrodes are connected so as to conduct the first electrode portion.
Forming a second electrode portion on the gate insulating film thin film portion between the electrode portions to form a gate electrode; and implanting impurity ions into the semiconductor layer using the gate electrode as a mask to form a source region and a drain region. Forming an interlayer insulating layer on the gate insulating film and the gate electrode; and forming a source electrode and a drain electrode connected to the source region and the drain region, respectively, on the interlayer insulating layer. A method for manufacturing a thin film transistor. 6. A polysilicon semiconductor layer is formed on an insulating substrate; a gate insulating film is formed on the semiconductor layer; a first metal thin film is formed on the gate insulating film; Etching is performed to form a pair of first electrode portions arranged at a predetermined interval, and simultaneously, the gate insulating film is etched to form the pair of first electrode portions.
Forming a gate insulating film thin film portion having a thickness smaller than that of the gate insulating film located immediately below the electrode portion; and forming the first pair of first electrodes so as to conduct the pair of first electrode portions.
A gate electrode is formed by providing a second metal thin film on the gate insulating film thin film portion between the electrode portions to form a second electrode portion, and implanting impurity ions into the semiconductor layer using the gate electrode as a mask. Forming a source region and a drain region, forming an interlayer insulating layer on the gate insulating film and the gate electrode, and forming a source electrode and a drain electrode connected to the source region and the drain region on the interlayer insulating layer, respectively. Forming a thin film transistor.