JPH111026A - Raster data-processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To properly cope with an increase of a count of light beams used in a plotting apparatus for plotting a pattern by scanning many light beams. SOLUTION: Light beams are arranged with a pixel arrangement pitch at the time of plotting and recording in a sub scan direction, and with an integral multiple of the pixel arrangement pitch in a main scan direction. In a raster data-processing apparatus, raster data are read out from a bit map memory sequentially in the order of lines in the main scan direction and stored in a first storing means 44B. When the raster data are to be read out from the lines in the main scan direction corresponding to a count of light beams, a read address is offset by an amount corresponding to the integral multiple. The raster data read out from the first storing means 44B are stored in a second storing means 44G in a predetermined order of addresses with bits of a divisor corresponding to the integral multiple. The raster data of a count of bits corresponding to a count of the light beams are read out in the order of addresses.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a raster data processing apparatus incorporated in a drawing apparatus for writing a predetermined pattern by scanning a drawing object with a light beam and modulating the light beam based on raster data. About.

[0002]

2. Description of the Related Art A drawing apparatus as described above is generally used for drawing a fine pattern on a surface of an appropriate object by using a light beam. Examples include drawing a circuit pattern in a process of manufacturing a printed circuit board and a transparent electrode pattern of a plasma display panel (PDP) using a photolithographic technique. In this case, the object to be drawn includes, for example, a photosensitive film for a photomask or a photoresist layer on a substrate.

[0003] In addition, as such a drawing apparatus, a type using a laser generator as a light source for generating a light beam and a type using a light emitting diode (LED) are known. In any case, in order to increase the drawing recording efficiency, it is common to simultaneously perform the drawing recording of a plurality of lines using a plurality of light beams. During the drawing operation, the plurality of light beams are moved in the Y-axis direction with respect to the object to be drawn, while the object to be drawn is moved in the X-axis direction perpendicular to the Y-axis direction with respect to the plurality of light beams. .

In particular, in the case of a multi-beam drawing apparatus using light emitting diodes, since the outer dimensions of the light emitting diodes are larger than the pixel arrangement pitch, the arrangement pitch of the light emitting diodes cannot be matched with the pixel arrangement pitch. The arrangement pitch of the plurality of light beams is made larger than the pixel arrangement pitch at the time of writing and recording. That is, the plurality of light emitting diodes are sequentially shifted at a predetermined pitch larger than the pixel arrangement pitch in the scanning direction, and the light emitted from each light emitting diode has a beam diameter size on the order of the pixel size on the object to be drawn. The beam is shaped and irradiated onto the object to be drawn. In order to perform drawing and recording at an appropriate pixel arrangement pitch with a plurality of light beams arranged at such a pitch, modulation of each light beam based on raster data in the X-axis direction is performed by a predetermined pitch in the Y-axis direction. It is necessary to delay only in time.

Conventionally, the above-described raster data delay processing is performed by a raster data processing device. More specifically, one line of raster data corresponding to each light beam is sequentially read out from the bit map memory by a predetermined number of bits, and the read out raster data is temporarily stored in a shift register after being subjected to parallel / serial conversion. By appropriately adjusting the read timing of the raster data from the shift register, the delay processing of the raster data is performed.

[0006]

For this reason, in the conventional raster data processing apparatus, there is a problem that as the number of light beams used increases, the circuit configuration becomes complicated and the cost increases. . For example, in the main scanning direction, when it is assumed that drawing and recording of 32 lines are performed at a time with 32 light beams, and that raster data of each line is read out from a bit map memory by 8 bits at a time, The delay processing requires 32 × 8 shift registers.

On the other hand, in a multi-beam drawing apparatus using light emitting diodes, the number of light beams used tends to gradually increase. For this reason, in a conventional raster data processing apparatus, the number of light beams used is actually increased. The inability to deal with it has also been pointed out as a problem.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a raster data processing incorporated in a drawing apparatus which draws a predetermined pattern by performing a modulation of the light beam based on the raster data while scanning the drawing object with the light beam. An object of the present invention is to provide a raster data processing apparatus which is configured to appropriately cope with an increase in the number of light beams used in the drawing apparatus.

[0009]

A raster data processing apparatus according to the present invention draws a predetermined pattern by scanning an object to be drawn with a plurality of light beams and modulating the light beams based on the raster data. A plurality of light beams are arranged in the sub-scanning direction at a pixel arrangement pitch at the time of image recording, and an arrangement pitch along the main scanning direction is an integral multiple of the pixel arrangement pitch. This is used when they are arranged in. A raster data processing apparatus according to the present invention comprises: a bitmap memory in which raster data is expanded; first raster data storage means for reading and storing raster data from the bitmap memory in the order of lines in the main scanning direction; A first raster data read operation for reading raster data by offsetting a read address of the raster data by an amount corresponding to an integral multiple when raster data is read from a main scanning direction line corresponding to the number of light beams from the storage means; Means, second raster data storage means for storing raster data read by the raster data reading means in a predetermined address order with a divisor bit number corresponding to an integer multiple, and second raster data storage means Raster data of the number of bits corresponding to the number of light beams from Reading those formed by and a second raster data reading means.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a raster data reading apparatus according to the present invention will be described with reference to the accompanying drawings.

Referring to FIG. 1, there is shown a multi-beam drawing apparatus incorporating a raster data reading apparatus according to the present invention. The multi-beam drawing apparatus is a circuit for manufacturing a printed circuit board using, for example, a photolithographic technique. This is used for drawing a pattern.

The multi-beam writing apparatus has a base 10 on which a pair of guide rails 12 is laid. The drawing table 1 is placed on the pair of guide rails 12.
4, the drawing table 14 is connected to a movable body (not shown) engaged with a ball screw 16 provided between the pair of guide rails 12, and the ball screw 16 is rotated by a driving motor (not shown). When driven, the drawing table 14 is moved in the Y-axis direction, that is, in the main scanning direction. An object to be drawn 18 is placed at a predetermined position on the drawing table 14, and the object to be drawn 18 is, for example, a photosensitive film for a photomask.

A gate-like structure 20 is provided on the base 10 so as to straddle a pair of guide rails 12, and a pair of guides perpendicular to the pair of guide rails 12 are provided on the gate-like structure 20. A rail 22 is laid. A carriage 24 is mounted on the pair of guide rails 22, and the carriage 24 is connected to a movable body 28 engaged with a ball screw 26 provided between the pair of guide rails 22, and the ball screw 26 is driven by a drive motor 30. When driven to rotate, the carriage 24 is moved in the X-axis direction, that is, in the sub-scanning direction.

A beam irradiation unit 32 including a large number of light emitting devices, ie, light emitting diodes (LEDs), is fixedly supported on the carriage 24. The beam irradiation unit 32 is moved together with the carriage 24 in the sub-scanning direction. The beam irradiation unit 32 is operated based on the raster data processed by the raster data processing device according to the present invention to perform a drawing operation.

In FIG. 1, reference numeral 34 denotes an X attached to the gate-like structure 20 along the sub-scanning direction.
Reference numeral 36 denotes a scale sensor for reading the scale of the X scale 34, by which the moving distance of the beam irradiation unit 32 in the sub-scanning direction is measured.

Referring to FIG. 2, the beam irradiation unit 3
2, a drawing head 38 is provided, in which LEDs 40 are arranged in a predetermined manner as a large number of light emitting devices. In the present embodiment, the LED 40
Arranged in a 32 × 64 matrix, the total number of LEDs 40 is 2048, and the light emitted from each LED 40 is applied to the object to be drawn as a light beam forming each pixel via an appropriate optical system. It has become. At the time of drawing recording, the drawing head 38 is moved in the X-axis direction (that is, the main scanning direction), and is scanned by one scanning in the Y-axis direction with 2048 light beams.
The drawing record of 2048 lines (that is, 2048 dots) can be performed.

For convenience of explanation, in FIG. 2, the row consisting of the 32 LEDs 40 located at the top row is the first row, and the row located at the bottom row is the first row.
Row 64. Also, in FIG. 2, the rightmost LED among the 32 LEDs 40 included in each row
40 is the first LED, and the leftmost LED 40 is the 32nd LED.

As shown in FIG. 2, from the first row to the first row
The array pitch along the main scanning direction of the array of 32 LEDs 40 included in each of the 64th row is 32 at the time of drawing recording.
The light beams correspond to the dots, so that the light beams obtained from the LEDs 40 do not interfere with each other.

On the other hand, two adjacent rows included in each row
Sub-scanning direction (X
The array pitch along the axis) is the pixel (dot) at the time of drawing recording
32nd LED 40 that matches the array pitch and is in each row
Light beam and the first row of rows located immediately below it
The arrangement pitch with the light beam by the LED 40 also coincides with the pixel arrangement pitch at the time of drawing and recording. In short, 2048
When the light beams from the LEDs 40 are projected onto a straight line parallel to the X-axis, the arrangement pitch of those projection locations matches the pixel arrangement pitch at the time of drawing and recording.

Referring to FIG. 3, there is shown a control block diagram of the multi-beam drawing apparatus shown in FIG. 1. In the block diagram, reference numeral 42 indicates a system controller. Microprocessor such as CPU and memory (RO)
M, RAM) and the like. The raster data processing apparatus according to the present invention comprises a raster data processing circuit 44 constituting a part of the control block diagram, and the raster data processing circuit 44 is controlled by a system controller 42.

As shown in FIG. 3, the control block diagram includes a raster conversion circuit 46 and a bit map memory 48. The raster conversion circuit 46 receives vector data created by a CAD (Computer Aided Design) station for designing circuit patterns and the like, and the vector data is sequentially converted into raster data and then output to a bitmap memory 48. There is temporarily held.

Referring to FIG. 4, bit map memory 4
The raster data expanded on the drawing 8 is schematically shown, and the drawing head 3 based on the raster data expanded in this manner.
8 is performed. That is, the drawing head 38
The drawing line in the main scanning direction drawn by each LED 40 corresponds to the horizontal arrangement line (Y) of the raster data shown in FIG. In short, 20 shown in FIG.
The array lines of 64 groups obtained by dividing the array lines of 48 raster data into units of 32 lines from the upper side are included in the first to 64th rows of the drawing head 38, respectively. This corresponds to the number of LEDs 40.

As shown in FIG. 4, in the present embodiment, the raster data in the horizontal (Y) array line includes raster data of 3000 × 32 bits = 96000 bits. 31 × 32 bits are given “0” as dummy data. Such dummy data can be added to the vector data when it is created, or the dummy data can be written in a predetermined address area of the bit map memory 48 in advance.

The capacity of the bit map memory 48 can store at least 2048 lines of raster data, and preferably has a storage capacity equivalent to a multiple of 2048 lines.

In this embodiment, the bit map memory 48
, Raster data is read out in predetermined bit units, for example, in 32-bit units for each array line, and the 32-bit raster data is stored in a raster data processing circuit 44 according to the present invention.
Are sequentially input. The 32-bit raster data input to the raster data processing circuit 44 is processed in accordance with the present invention and then output to the drawing synchronization circuit 50 in a predetermined bit unit, for example, an 8-bit unit. The drawing synchronization circuit 50 is connected to the drawing head 38 (FIG. 2), and the drawing synchronization circuit 50 includes an LED for the 2048 LEDs 40 of the drawing head 38.
A drive circuit is included. On the other hand, a drawing timing clock generation circuit 52 is connected to the drawing synchronization circuit 50, and a clock pulse signal of a predetermined frequency is output from the drawing timing clock generation circuit 52 to the drawing synchronization circuit 50 under the control of the system controller 42. .

After the output bit number of the raster data to the drawing synchronization circuit 50 reaches 2048 bits (the number of drawing lines by one drawing operation in the main scanning direction in the drawing head 38), the drawing head 50 38 individual LEDs 4
For 0, the value of the corresponding raster data (ie, “0”)
A drive pulse is output in accordance with (1), and the output timing of the drive pulse is controlled in accordance with the drawing timing clock pulse from the drawing timing clock generation circuit 52.

The operation of the raster conversion circuit 46 is controlled by the system controller 42. The writing of raster data to the bitmap memory 48 and the reading of raster data therefrom are performed by the system controller 4.
2 is performed by a write clock pulse and a read clock pulse output from the second clock pulse.

Referring to FIG. 5, there is shown a detailed block diagram of a raster data processing circuit 44 constructed according to the present invention. As shown in FIG. 5, the raster data processing circuit 44 includes a first data changeover switch circuit 44A. And a first data storage means 44B. The first data storage means 44B has eight memories, namely memories C0, C1, C2,
C3, C4, C5, C6 and C7, and the first data changeover switch circuit 44A has memories C0, C1, C2, C3, C4, C5, C6 and C as shown in FIG.
Eight switch circuit elements corresponding to each of 7 are provided.

When raster data is read from the bit map memory 48 for each 32 bits, the eight switch circuit elements of the first data changeover switch circuit 44A are switched to the input side, and the bit map memory 48 outputs the data for each array line. The read 32-bit raster data is stored in the eight memories C0, C1, C2, C3, C4, C5, C of the first data storage means 44B according to the arrangement line number.
6 and C7 are sorted and stored by the first data changeover switch circuit 44A.

As shown in FIG. 5, the memories C0 to C7 of the first data storage means 44B have a first address signal generation circuit 44D via an address offset circuit 44C.
Connected to. When 32-bit raster data read for each array line from the bit map memory 48 is written to any of the memories C0 to C7, the address is the write address output from the first address signal generation circuit 44D. Determined by signal. When the raster data is written to the memories C0 to C7, the address offset circuit 44C is set so as not to give an address offset amount to the address signal from the first address signal generation circuit 44D.

Referring to FIG. 7, bit map memory 4
The raster data expanded in FIG. 8 is schematically shown in more detail than FIG. 4, and the raster data array line corresponding to the drawing line in the main scanning direction at the time of drawing recording starts from “0000” as the line number for convenience. “2047” has been given. Numerical value “32” assigned to each cell of each array line indicates the number of bits of the raster data, and the 32-bit raster data included in each cell is displayed in the margin [D31; D30;... D01; ]
It is shown as

The reading of raster data from the bitmap memory 48 is first performed from the line number "0000". The reading unit is 32 bits as described above, and the raster data [D31; D30; … D01;
D00] is stored in the memory C0. When the reading of the raster data of 32 bits from the line number “0000” is repeated 3000 times, all the raster data of 96000 bits is read. Next, the line number "0001"
Is read, and the 32-bit read raster data is stored in the memory C1.
Reading of 32-bit raster data is also repeated 3000 times. In a similar manner, the line numbers “0002” to “000”
The raster data is read from each of the 7 "and the raster data is sequentially stored in the memories C2 to C7 from each line number.
Is stored in

When all the raster data read from the line number "0007" is stored in the memory C7, the raster data is read from the line number "0008". The storage destination of the raster data is the memory C0. Return to When the reading of the raster data up to the line number “2047” is completed in this way, the raster data of each array line shown in FIG. 7 is stored in the memory C0 to C0 according to the line number.
7 is stored.

Referring to FIG. 8, the memories C0 to C7
And the line numbers of raster data to be stored in the memory. As can be seen from the figure, the line numbers of the raster data stored in the memories C0 to C7 can be expressed by the following equations. Memory C0: Line number = 8N Memory C1: Line number = 8N + 1 Memory C2: Line number = 8N + 2 Memory C3: Line number = 8N + 3 Memory C4: Line number = 8N + 4 Memory C5: Line number = 8N + 5 Memory C6: Line number = 8N + 6 memory C7: line number = 8N + 7 (0 ≦ N (integer) ≦ 255 in FIG. 8) As is clear from FIG. 8, the memories C0 to C7
Each of these stores a total of 256 lines of raster data.

When raster data of each line number is stored in each of the memories C0 to C7, the raster data is stored at the same address by 32 bits as schematically shown in FIG.

For example, when attention is paid to the memory C0, as apparent from FIG.
Each of the raster data sequentially read in 32 bits from the line number “0000” is stored in the address [0] to the address [2999]. At this time, the 32 bits of the first read out from the line number “0000” are stored. Is stored at address [0], and the last 32-bit raster data read from line number "0000" is stored at address [2999]. Also, raster data sequentially read in 32-bit units from the line number “0008” of the bitmap memory 48 is also stored at addresses [3000] to [5999].

In short, in order to store 96000 bits of raster data included in each array line of the bitmap memory 48, 3000 addresses having a storage capacity of 32 bits are required, and a total of 256 addresses are required. The number of addresses required to store all of the drawing rasters is 768 000 = (3000 x 256). Therefore, the raster data (FIG. 8) of the line number "2040" to be stored last in the memory C0 is distributed to the address [765000 = 3000X255] or the address [767999 = (3000X256) -1] in units of 32 bits and stored. Is done.

In the case of the memories C1 to C7, each line number is different from that of the memory C0.
It will be apparent from FIG. 9 that the raster data read from the bitmap memory 48 by 32 bits for each line number is stored at the same address as in the case of the memory C0.

The memory C in the manner shown in FIGS.
After the raster data is written to 0 to C7, the raster data is sequentially read from the memories C0 to C7 in units of 32 bits. The reading of the 32-bit raster data from the memories C0 to C7 is performed based on the read address signal output from the first address signal generating circuit 44D, and the 32-bit raster data from the memories C0 to C7 is read. Reading is performed in the order of line numbers.

In this embodiment, the first address signal generating circuit 44D outputs a read address signal for accessing the same address in each of the memories C0 to C7. However, the read address is output. A different address offset amount is assigned to the signal by the address offset circuit 44C for each of the memories C0 to C7. That is, the read address signal input to C0 to C7 is provided with an address offset amount that decreases by one address from the memory C0 to the memory C7.

32 from the memories C0 to C7 described above.
The reading of raster data for each bit will be described below with reference to the schematic diagrams shown in FIGS.

The first address signal output from the address generation signal circuit 44C accesses the address [0] of each of the memories C0 to C7. However, the address signal accessed to the memory C0 includes: As shown in FIG. 10, an address offset amount “31” is given. Therefore, the address signal output from the address generation signal circuit 44C accesses not the address [0] of the memory C0 but the address [31]. That is, the memory C
The 32-bit raster data read from 0 is not stored at address [0], but is stored at address [31].

As is apparent from FIG. 10, the address signal inputted to the memory C1 is given an address offset amount "30". Therefore, the address signal accesses the address [30] instead of the address [0] of the memory C1. That is, the 32-bit raster data read from the memory C1 is not stored at the address [0], but is stored at the address [30]. Similarly, address offset amounts "29", "28", "27", "2"
6 "," 25 "and" 24 ", respectively,
Addresses 2 to C7 [29], [28], [27], [2
6], [25] and [24], 32-bit raster data is read.

In short, FIG. 10 shows the addresses [31] and [3] of the raster data of the line numbers “0000” to “0007” stored in the memories C0 to C7, respectively.
0], [29], [28], [27], [26], [25] and [2
4] schematically shows the reading of the raster data of 32 bits stored in [4].

Next, the first address signal generation circuit 44
From D, each address [3
000] is output. At this time, the address signals input to the memories C0 to C7 include address offset amounts "23", "22", and "21" as shown in FIG. , “20”, “19”, “1”
8 "," 17 "and" 16 ", respectively,
Addresses [3023], [3022], [302] of 0 to C7
1], [3020], [3019], [3018], [3017] and [3
016], 32-bit raster data is read.

In short, FIG. 11 shows the memories C0 to C0.
7 respectively stored in the line numbers “0008” to “00”.
Address [3023], [302
2], [3021], [3020], [3019], [3018], [301
7] and [3016] schematically show the readout of raster data for 32 bits stored in [3016].

Subsequently, the first address signal generation circuit 44
From D, the respective addresses [6
000] is output. At this time, the address signals input to the memories C0 to C7 include address offset amounts "15", "14", and "13" as shown in FIG. , “12”, “11”, “1”
0, "09" and "08" are given to the memory C
Addresses 0 to C7 [6015], [6014], [601]
3], [6012], [6011], [6010], [6009] and [6
008], 32-bit raster data is read.

In short, FIG. 12 shows the memories C0 to C
7, the line numbers “0016” to “00” stored respectively.
Address [6015], [601
4], [6013], [6012], [6011], [6010], [600
9] and [6008] schematically showing the readout of raster data for 32 bits.

Next, the first address signal generation circuit 44D
From the respective addresses of the memories C0 to C7 [900
[0] is output,
At this time, the address signals input to the memories C0 to C7 respectively have the address offset amounts "07", "06", "05", "04", "03", "02", as shown in FIG.
“01” and “00” are given, respectively, and addresses [9007], [9006], [9005], [90
04], [9003], [9002], [9001] and [9000]
32-bit raster data is read.

In short, FIG. 13 shows the memories C0 to C0.
7 respectively stored in the line numbers “0024” to “00”.
Address [9007], [9007
6], [9005], [9004], [9003], [9002], [900
1] and [9000] schematically show the readout of raster data of 32 bits.

The above-described raster data reading corresponds to the 32 LEDs 40 included in the first row (32 lines) of the drawing head 38 (FIG. 2). Subsequently, reading of raster data corresponding to the 32 LEDs 40 included in the second row of the drawing head 38 is performed in a similar manner. That is, the first address signal generation circuit 4
From 4D, the respective addresses of the memories C0 to C7
Address signals for accessing [12000], [15000], [18000], and [21000] are output, and the same address offset amounts as described above are sequentially applied to the respective address signals. .

From the first address signal generation circuit 44D, the respective addresses of the memories C0 to C7 [756000 = 3000]
X252], [759000 = 3000X253], [762000 = 3000X254] and
When an address signal for accessing [765000 = 3000X255] is output, all L of the drawing head 38 are output.
This means that all of the first 32 bits of raster data have been read out for each of the EDs 40 (2048).

As shown in FIGS. 5 and 6, the 32-bit raster data read from each of the memories C0 to C7 is output to the multiplexer circuit 44E. The multiplexer circuit 44E has eight multiplexers, namely, multiplexers M0, M1, M2, M3, M
4, M5, M6 and M7.

In this embodiment, even if 32 bits of raster data from each of the memories C0 to C7 are input to the multiplexers M0, M1, M2, M3, M4, M5, M6 and M7, 8 of them are output. Only raster data for bits are selectively output from the multiplexers. Specifically, the raster data of 32 bits [D31; D3
0; ... D01; D00], that is, 8-bit data
[D31; D30; ... D25; D24], 8-bit data [D23; D22; ...
D17; D16], one of 8-bit data [D15; D14;... D09; D08] and 8-bit data [D07; D06;... D01; D00]
Only one is output from multiplexers M0 through M7. Accordingly, the line number “0000” to the line number “202”
All of the raster data [D31; D30;... D01; D00] for the first 32 bits of each of 7 ”are multiplexed into multiplexers M0 and M0.
In order to output the data from 1, M2, M3, M4, M5, M6 and M7, it is necessary to repeat the reading of the drawing data (32 bits) from the respective addresses of the memories C0 to C7 four times.

The multiplexers M0 to M7 output the 8-bit data [D31; D30;... D25; D24], the 8-bit data [D23; D22;.
5; D14; ... D09; D08] and 8-bit data [D07; D06;
D01; D00] is selected by setting the selection switching mode in the multiplexers M0 to M7 as described later.

The 8-bit raster data output from the multiplexers M0 to M7 of the multiplexer circuit 44E is output to the second data storage means 44G via the second data changeover switch circuit 44F. As in the case of the first data changeover switch circuit 44A, the second data changeover switch circuit 44F is provided with eight switch circuit elements as shown in FIG. 14, and the second data storage means 44G is also provided with the first data changeover means 44G. Of the memories R0, R1, R2, R3, R4, R
5, R6 and R7. Multiplexer M0
When eight bits of raster data from M7 to M7 are output to the memories R0 to R7 of the second data storage means 44G, the switch circuit elements of the second data changeover switch circuit 44F are input as shown in FIG. Connected to the side.

The multiplexers M0 to M7 of the multiplexer circuit 44E select 8-bit data from the 32-bit (4 × 8 bits) raster data read from each of the memories C0 to C7, and select the 8-bit data from the memories R0 to R7. It has a function to sort and output each,
This function itself extends from each of the memories C0 to C7
This is a function of selectively switching the connection between the 32-bit data line and the 8-bit data line extending from each of the memories R0 to R7. Such selective connection switching is performed by setting a selection switching mode for the multiplexers M0 to M1.

The setting of the selection switching mode for multiplexers M0 to M7 is performed by multiplexer switching circuit 44H.
H can set one of four types of selection switching modes to the multiplexers M0 to M7 according to the address signal from the first address signal generation circuit 44D. In the present embodiment, the four types of connection switching modes are conveniently distinguished as set values “3”, “2”, “1”, and “0”.

Referring to Tables 1 to 8 below, for each of multiplexers M0 to M7, memory C0
To C7, the selective connection switching relationship between the 32-bit data line extending from each of the memories R0 to R7 and the 8-bit data line extending from each of the memories R0 to R7 is set to "3", "2" in the selection switching mode. , "1" and "0".

[0060]

[Table 1]

[0061]

[Table 2]

[0062]

[Table 3]

[0063]

[Table 4]

[0064]

[Table 5]

[0065]

[Table 6]

[0066]

[Table 7]

[0067]

[Table 8]

In Tables 1 to 8, "C0-
"0" to "C0-31" indicate 32-bit data lines extending from the memory C0. Similarly, the 32-bit data lines extending from the memories C1 to C7 correspond to "C1-0" to "C1". −31 ”,“ C2
−0 ”to“ C2-31 ”,“ C3-0 ”to“ C
3-31 "," C4-0 "to" C4-31 "," C
5-0 "to" C5-31 "," C6-0 "to" C6-31 "and" C7-0 "to" C7-31 "
Indicated by

The 32-bit data lines "C0-0" to "C0-31" extending from the memory C0 are 32-bit raster data [D00; D01;... D30; D31 read from a predetermined address of the memory C0. This is the same for the 32-bit data line extending from the memories C1 to C7.

On the other hand, "R0-0" to "R0-7" indicate 8-bit data lines extending from the memory R0, and similarly, 8-bit data lines extending from the memories R1 to R7 respectively. “R1-0” to “R1-7”, “R2-0” to “R2-7”,
“R3-0” to “R3-7”, “R4-0” to “R4-7”, “R5-0” to “R5-7”, “R
6-0 to R6-7 and R7-0 to R7-7.

For example, when "0" is set as the setting value of the selection switching mode for the multiplexers M0 to M7, the multiplexer M7 (Table 8) connects the data lines "C0-31" to "C7-31" respectively. The multiplexer M6 (Table 7) is connected to the data lines "R7-0" to "R7-7" and the data lines "C0-3".
0 "to" C7-30 "are connected to the data lines" R
6-0 to R6-7, multiplexer M5 (Table 6) connects data lines C0-29 to C7-29 to data lines R5-0 to R5-7, respectively. The multiplexer M4 (Table 5) is connected to the data lines "C0-28" through "C7-2".
8 "to data lines" R4-0 "to" R4
−7 ”, multiplexer M3 (Table 4) connects data lines“ C0-27 ”through“ C7-27 ”to data lines“ R3-0 ”through“ R3-7 ”, respectively, and multiplexer M2 (Table 4). 3) is the data line “C”
The multiplexers M1 (Table 2) connect the data lines "C0-25" to "C7-25" to the data lines "R2-0" to "R2-7", respectively. Each data line "R1-
0 to "R1-7" and multiplexer M0 (Table 1) connects data lines "C0-24" to "C7-24" to data lines "R0-0" to "R0-7", respectively. It is made to let.

In short, the multiplexers M0 to M7
When "0" is set as the setting value of the selection switching mode for multiplexer C0, multiplexers M0 to M7 store data in memory C0.
.. D01; D00], only 8-bit data [D31; D30;... D25; D24] of the 32-bit raster data [D31; D30;... D01; D00] are output.

As is clear from Tables 1 to 8, when "1" is set as the setting value of the selection switching mode for the multiplexers M0 to M7, the multiplexers M0 to M7 store the data in the memories C0 to C7. Raster data of 32 bits read from each [D31; D3
0; ... D01; D00] 8-bit data [D23; D22; ... D1]
7; D16] are output, and when "2" is set as the set value of the selection switching mode, the multiplexers M0 to M7 output 8-bit data [D15; D14;... D09; When "3" is set as the set value of the multiplexor, the multiplexers M0 to M7 output 8-bit data.
[D07; D06; ... D01; D00] are output.

The line number "00" in the memories C0 to C7
After the reading of the first 32 bits of each of the line numbers “2027” from “00” is repeated four times, ie, the line number “000”
All of the first 32 bits of raster data [D31; D30;... D01; D00] of line numbers "2027" from "0" are multiplexers M0, M1, M2, M3, M4, M5,
After being output to the memories R0 to R7 through M6 and M7, the first address signal generation circuit 44D outputs addresses [1], [30001], and [6000] of the memories C0 to C7.
1]... Address signals for accessing [756001], [759001], [762001], and [765001] are sequentially output, whereby all the LEDs 40 (2048
), The next 32 bits of raster data are read out. As described above, the address signals for accessing the respective addresses of the memories C0 to C7 are sequentially set to "1".
Each raster data of the line numbers “0000” to “2047” is sequentially read from the memories C0 to C7 by 32 bits.

Accordingly, the addresses [2999], [5999], [8999], [11999]... [75899] of the respective memories C0 to C7 are stored.
9], [761999], [764999] and an address signal for accessing [767999] are generated by the first address signal generation circuit 44D.
, All raster data are read from the memories C0 to C7, and all the raster data are written to the memories R0 to R7 by the multiplexers M0 to M7.

Referring to FIGS. 15 to 18, the raster data written in the memories R0 to R7 is schematically shown. In each of the memories R0 to R7, 8-bit raster data is stored at each address. For example, from address [0] to address [2] of the memory R7 in FIG.
55], raster data [D31] for a total of 2048 (256 × 8) bits is stored. These raster data [D31] for 2048 bits are first stored in the drawing head 3 at the time of drawing start recording.
8 to be recorded by the 2048 LEDs 40.

The 32-bit raster data [D] stored from address [0] to address [3] of the memory R7 are stored.
31] correspond to the 32 LEDs 40 included in the first row of the drawing head 38, and refer to FIGS.
As is clear from FIG. 3, the raster data [D31] of the most significant bit of the address [0] is 32 times the dot pitch at the time of drawing recording, that is, 32 dots. Minutes apart.

Further, as is apparent from FIGS. 10 to 13, the most significant bit of address [0] of the 32-bit raster data stored from address [0] to address [3] of memory R7. All other raster data [D31] except for the raster data [D31] are dummy data,
The same is true from address [4] of memory R7.
The same applies to the 32-bit raster data stored up to [7].

Address [0] of memory R6 shown in FIG.
From the address to the address [255], a total of 2048 (256 × 8) bits of raster data [D30] are stored.
The raster data [D30] for bits is the address of the memory R7
The 2048-bit raster data [D31] stored from [0] to the address [255] is to be recorded by the 2048 LEDs 40 of the drawing head 38. Similarly, respective addresses of the memories R5 and R4 in FIG.
The raster data [D29] and [D28] of 2048 bits stored from [0] to address [255] are stored in the memory R3 in FIG.
Address [0] to address [255] of R2 and R2
The raster data [D27] and [D26] of 2048 bits stored up to and the raster data [D48] of 2048 bits stored from address [0] to address [255] of each of the memories R1 and R0 in FIG. [D25] and [D24] are to be sequentially recorded by the 2048 LEDs 40 of the drawing head 38.

Referring again to FIG. 18, from address [256] to address [511] of memory R7, 2048 stored from address [0] to address [255] of memory R0 are stored.
Should be recorded following raster data [D24] for bits
Raster data [D23] for 2048 bits is stored.
In short, in each of the memories R0 to R7, 2048 bits of raster data to be appropriately sequentially recorded by the 2048 LEDs 40 of the drawing head 38 are stored in a predetermined address order.

As shown in FIGS. 5 and 14, the second data storage means 44G includes a second address signal generation circuit 44.
I is connected to the second address signal generation circuit 44I
As the address signal, an address signal adapted to sequentially access the respective addresses of the memories R0 to R7 is output. When reading the raster data from the memories R0 to R7 in units of 8 bits, the eight switch circuit elements of the second data changeover switch 44F are connected to the output side. Reading of the raster data from the memories R0 to R7 as described above is performed based on the address signal output from the second address signal generating circuit 44I.

The raster data processing circuit 4 shown in FIG.
4, various components such as a first data changeover switch circuit 44A, an address offset circuit 44C, a first address signal generation circuit 44D, a second data changeover switch circuit 44F, and a second address signal generation circuit 44I. Is operated under the control of the system controller 42.

Next, a raster data processing routine according to the present invention will be described with reference to the flowcharts shown in FIGS. This raster data processing routine is a part of the drawing operation routine of the multi-beam drawing apparatus shown in FIG.

First, in step 1901, the first data changeover switch circuit 44A is connected to the input side (FIG. 6). Next, in step 1902, when an address signal is output from the first address signal generation circuit 44D, the address offset circuit 44C is set so as not to add an address offset amount to the address signal.

In step 1903, the raster conversion circuit 4
6 is operated, the vector data input thereto is sequentially converted into raster data, and the bit map memory 4 is operated.
At this time, the raster data is developed in the bit map memory 48 in a manner as shown in FIG. Next, at step 1904, the memory selection counter a is reset, and then at step 1905, the data read counter b is reset.

At step 1906, the count value of the memory selection counter a is divided by the numerical value "8", and one of the remaining values, that is, one of the memories C0 to C7 according to any of "0" to "7". One is selected. Table 9 below shows the relationship between the remaining numerical values and the memories to be selected.

[0087]

[Table 9]

At this stage, since the count value of the memory selection counter a is "0" (the remainder is zero), the memory C0 is selected (Table 9). Next, the routine proceeds to step 1907, where it is determined whether or not the count value of the data read counter b has reached the numerical value "2999". at the present stage,
Since the count value of the data read counter b is "0", the process proceeds from step 1907 to step 1908, where the line number "0000" in the bit map memory 48 is set.
It is confirmed whether or not the 32-bit raster data has been read from FIG. 7.

When the reading of the 32-bit raster data from the line number "0000" is confirmed, the process proceeds to step 1909, where the 32-bit raster data is stored in the memory C0 at a predetermined address (at this stage, the address [0]). ) Is written. Next, the process proceeds to step 1910. When the count value of the data read counter b is counted up by "1", the process returns to step 1907.

Until the count value of the data read counter b reaches the numerical value "2999", that is, all of the raster data (96000 bits) of the line number "0000" is read in units of 32 bits and the predetermined address of the memory C0 is read. Are repeated until the data is sequentially stored in steps 1907 to 1910.

The raster data of line number "0000" (96000
When all the readings of the data reading counter (b) have been completed, that is, when the count value of the data read counter b has reached the numerical value "2999", the process proceeds from step 1907 to step 1911, where the count value of the memory selection counter a has become the numerical value "2047". Is determined. at the present stage,
Since the count value of the memory selection counter a is "0", the process proceeds to step 1912, where the count value of the memory selection counter a is counted up by "1".
Thereafter, the flow returns to step 1905, where the data read counter b is reset. Then, step 190
At 6, the count value of the memory selection counter a is divided by the numerical value "8", and one of the memories C0 to C7 is selected according to the remaining numerical value.

At this stage, since the count value of the memory selection counter a is "1", the remainder is also "1", and the memory C1 is selected (Table 9). Next, the routine proceeds to step 1907, where it is determined whether or not the count value of the data read counter b has reached the numerical value "2999". At this time, since the count value of the data read counter b is "0", the process proceeds from step 1907 to step 1908, where the 32-bit raster data is read from the line number "0001" (FIG. 7) in the bit map memory 48. It is confirmed whether or not the data has been read.

When the reading of the 32-bit raster data from the line number "0001" is confirmed, the process proceeds to step 1909, where the 32-bit raster data is stored in the memory C1 at a predetermined address (at this stage, the address [0]). ) Is written. Next, the process proceeds to step 1910. When the count value of the data read counter b is counted up by "1", the process returns to step 1907.

Until the count value of the data read counter b reaches the numerical value "2999", that is, all the raster data (96000 bits) of the line number "0001" is read in units of 32 bits, and the predetermined address of the memory C1 is read. Are repeated until the data is sequentially stored in steps 1907 to 1910.

The raster data of line number "0001" (96000
When all the readings of the data reading counter (b) have been completed, that is, when the count value of the data read counter b has reached the numerical value "2999", the process proceeds from step 1907 to step 1911, where the count value of the memory selection counter a has become the numerical value "2047". Is determined again. At this stage, since the count value of the memory selection counter a is "1", the process proceeds to step 1912, where the count value of the memory selection counter a is counted up again by "1". Thereafter, the flow returns to step 1905, where the data read counter b is reset. Next, in step 1906, the count value of the memory selection counter a is divided by the numerical value "8", and the memory C0
To C7 are selected. That is, at this time, the remaining numerical value is "2", so that the memory C2 is selected (Table 9).

In this manner, when the raster data is sequentially read from the bit map memory 48 and all the raster data for 2048 lines are stored in the memories C0 to C7 (FIGS. 8 and 9), that is, at step 1911 When the count number of the memory selection counter a reaches the numerical value “2047”, the process proceeds from step 1911 to step 1913,
Therefore, the operation of the raster conversion circuit 46 is temporarily stopped.

In step 1914 (FIG. 20), the connection of the first data changeover switch circuit 44A is switched to the output side (FIG. 6), and then in step 1915, the second data changeover switch circuit 44F is connected to the input side. Is done.
Subsequently, in step 1916, when an address signal is output from the first address signal generation circuit 44D, the address offset circuit 44C is set so as to add a predetermined address offset amount to the address signal.

At step 1917, the counter i, counter j and counter m are reset. It should be noted that the counter i is a 32
A counter j is a data read counter for counting the reading of raster data for the line, a counter j is a mode selection counter for setting a selection switching mode of the multiplexers M0 to M7, and a counter m is 32 from the memories C0 to C7. This is an address counter for counting the read address of raster data in bit units.

In step 1918, the count value of the mode selection counter j is set as the set value of the selection switching mode for the multiplexers M0 to M7. At this stage, since the count value of the mode selection counter j is “0”, “0” is set as the set value of the selection switching mode.

At step 1919, the counter k is reset. The counter k sets an address offset amount to be given to the address signal by the address offset circuit 44C when the address signal is output from the first address signal generation circuit 44D to each of the memories C0 to C7. Is an address offset counter.

In step 1920, a predetermined address offset amount to be added to the address signal output from first address signal generation circuit 44D to each of memories C0 to C7 is set according to the count value of counter k. Is done. At this stage, since the count value of the counter k is "0", an address offset amount is set in the address signal output to each of the memories C0 to C7 in a manner as shown in Table 10 below. .

[0102]

[Table 10]

That is, as is apparent from Table 10, the address offset amounts "31" to "24" are set in the address signals output to each of the memories C0 to C7.

In step 1921, 32-bit raster data is read from the memories C0 to C7. More specifically, an address signal is output from the first address signal generation circuit 44D, and this address signal is used to access the address [0] of each of the memories C0 to C7.
The address offset amount as described above is added to the address signal to be input to the. Accordingly, as shown in FIG. 10, 32 bits of raster data at addresses [31] to [24] are read from each of the memories C0 to C7.

At step 1922, the addresses [31] to [24] from the memories C0 to C7, respectively.
Of the 32-bit raster data read from
The bit data is sorted by the multiplexers M0 to M7 and written to predetermined addresses of the memories R0 to R7. At this stage, the set value of the selection switching mode set in the multiplexers M0 to M7 is "0".
Is set (step 1918),
.. D01; D00], only 8-bit data [D31; D30;... D25; D24] are selected and written to the memories R0 to R7 (Tables 1 to 8). ).

At step 1923, it is determined whether or not the count value of the counter k is equal to the numerical value "3". At this stage, since k = 0, the process proceeds from step 1923 to step 1924, where the count value of the counter k is incremented by “1”, and then the process proceeds to step 1920.
Return to

At this time, since k = 1, step 19
At 20, an address offset amount is set in the address signal output to each of the memories C0 to C7 in a manner as shown in Table 11 below.

[0108]

[Table 11]

That is, as is apparent from Table 11, address offset amounts "23" to "16" are set in the address signals output to each of the memories C0 to C7.

In step 1921, 32 bits of raster data are read from the memories C0 to C7 again. More specifically, the first address signal generation circuit 44D
From the memory C0 to C7, the address signals are to be accessed, but the address signals to be input to the memories C0 to C7 are shown in Table 11. Since the address offset amount shown in FIG.
As shown in FIG. 11, 32 bits of raster data from address [3023] to address [3016] are read from each of 0 to C7.

In step 1922, the addresses [3023] to [3] from the memories C0 to C7, respectively.
016], 8-bit data of the 32-bit raster data is sorted by the multiplexers M0 to M7 and written to predetermined addresses of the memories R0 to R7.
Since the setting value of the selection switching mode set in M7 to M7 is set to "0" (step 1918), the above-described 32-bit raster data [D31; D30;... D01;
0], only 8-bit data [D31; D30;... D25; D24] are selected and written into the memories R0 to R7 (Tables 1 to 8).

At step 1923, it is determined whether or not the count value of the counter k is equal to the numerical value "3". At this time, since k = 1, the process proceeds from step 1923 to step 1923, where the count value of the counter k is incremented by “1”, and then the process proceeds to step 1920.
Return to.

At this time, since k = 2, step 19
At 20, an address offset amount is set in the address signal output to each of the memories C0 to C7 in a manner as shown in Table 12 below.

[0114]

[Table 12]

That is, as is clear from Table 12, the address offset amounts “15” to “08” are set in the address signals output to each of the memories C0 to C7.

In step 1921, 32 bits of raster data are read from the memories C0 to C7 again. More specifically, the first address signal generation circuit 44D
From the memory C0 to C7, the address signal is to access the respective address [6000] of the memories C0 to C7, but the address signals to be input to the memories C0 to C7 are shown in Table 12. Since the address offset amount as shown is added, 32 bits of raster data of addresses [6015] to [6008] are read from each of the memories C0 to C7 as shown in FIG.

At step 1922, the address [6015] to address [6] from each of the memories C0 to C7 is used.
008], the 8-bit data of the 32-bit raster data read out from the memory is distributed by the multiplexers M0 to M7 and written to the predetermined addresses of the memories R0 to R7. Since "0" is set as the set value of the selected switching mode (step 19)
18), the above-described 32-bit raster data [D31; D30;
… D01; D00] and 8-bit data [D31; D30;… D
25; D24] are selected and written to the memories R0 to R7 (Tables 1 to 8).

At step 1923, it is determined whether or not the count value of the counter k is equal to the numerical value "3". At this time, since k = 2, the process proceeds from Step 1923 to Step 1924, where the count value of the counter k is incremented by “1”, and then Step 1920
Return to.

At this time, since k = 3, step 19
At 20, the address offset amount is set in the address signal output to each of the memories C0 to C7 in a manner as shown in Table 13 below.

[0120]

[Table 13]

That is, as is apparent from Table 13, address offset amounts "07" to "00" are set in the address signals output to the memories C0 to C7, respectively.

In step 1921, 32 bits of raster data are further read from the memories C0 to C7. More specifically, the first address signal generation circuit 44D
Output an address signal, which is to access the respective address [9000] of the memories C0 to C7, but the address signals to be inputted to the memories C0 to C7 are shown in Table 13. Since the address offset amount as shown is added, 32 bits of raster data of addresses [9007] to [9000] are read from each of the memories C0 to C7 as shown in FIG.

At step 1922, the addresses [9007] to [9] from the memories C0 to C7, respectively.
000] is sorted by the multiplexers M0 to M7 and written to predetermined addresses of the memories R0 to R7, but is still set in the multiplexers M0 to M7. Since "0" is set as the set value of the selected switching mode (step 19)
18), the above-described 32-bit raster data [D31; D30;
… D01; D00] and 8-bit data [D31; D30;… D
25; D24] are selected and written to the memories R0 to R7 (Tables 1 to 8).

Thus, at this point, 8-bit data [D24;... D24] are stored in each of the addresses [0] to [3] of the memory R0, and the address of the memory R1 is stored.
8-bit data for each of [0] to address [3]
[D25;... D25] are stored in each of the addresses [0] to [3] of the memory R2.
.. D26] are stored in each of address [0] to address [3] of the memory R3.
Is stored in the address [0] or the address of the memory R4.
Each of [3] stores 8-bit data [D28;... D28], and each of the addresses [0] to [3] of the memory R5 stores 8-bit data [D29;.
.. D30] is stored in each of the addresses [0] to [3] of the memory R6, and is stored in each of the addresses [0] to [3] of the memory R7. .. D31] are stored (FIGS. 15 to 18).

On the other hand, since k = 3 at this point, the process proceeds from step 1923 to step 1925,
Therefore, the count value of the counter i is changed to the value "63 (2048/32
1), that is, whether or not the first 32 bits of raster data from line number “0000” to line number “2047” have been read.

At this stage, since i = 0, the process proceeds from step 1925 to step 1926, where the count value of the data read counter i is incremented by "1", and then the process returns to step 1919. Step 19
At 19, after the counter k is reset, the routine consisting of steps 1920 to 1924 is repeated again. By sequentially repeating such a routine, each address of the memories R0 to R7 is obtained.
[0] or address [255] stores predetermined raster data in units of 8 bits.

In step 1925, when the count value of the data read counter i reaches the numerical value "63", that is, predetermined raster data of 8 bits is stored in each of the addresses [0] to [255] of the memories R0 to R7. When it is stored, the process proceeds from step 1925 to step 1927, where it is determined whether or not the count value of the mode selection counter j is equal to the numerical value "3". At this stage, j =
Since it is 0, the process proceeds to step 1928, where the counter i is reset. Then, in step 1929, the count value of the counter j is incremented by "1", and the process returns to step 1918.

At this time, since j = 1, in step 1918, “1” is set as the set value of the selection switching mode for the multiplexers M0 to M7 (Tables 1 to 8). Next, the routine proceeds to step 1919, where the counter k is reset.

Thereafter, the same routine as that described above is repeated. However, since the set value of the selection switching mode for the multiplexers M0 to M7 is "1", 32 bits read from the memories C0 to C7 are read. .. D01; D00], only 8-bit data [D23; D22;... D15; D16] are selected by the multiplexers M0 to M7 and written to the memories R0 to R7 (Tables 1 to 7). Table 8).

At the time of execution of the above routine, step 1925
And the count value of the data read counter i returns to "6
When 3 ”is reached, that is, when predetermined raster data is stored by 8 bits at each address [256] to address [511] of the memories R0 to R7, the process proceeds from step 1925 to step 1927, where the mode selection is performed. It is determined whether or not the count value of the counter j is equal to the numerical value “3.” At this stage, since j = 1, the process proceeds to step 1928 again, where the counter i is reset. Is incremented by "1", and the process returns to step 1918.

Since j = 2 at this time, in step 1918, "2" is set as the set value of the selection switching mode for the multiplexers M0 to M7 (Tables 1 to 8). Next, the routine proceeds to step 1919, where the counter k is reset.

Thereafter, the same routine as described above is repeated again, except that the multiplexers M0 to M7
.. D01; D00] of the 32-bit raster data [D31; D30;... D01; D00] read from the memories C0 to C7.
Only bit data [D14; D13;... D09; D08] are selected by the multiplexers M0 to M7 and written to the memories R0 to R7 (Tables 1 to 8).

When the above routine is executed, step 1925 is executed.
When the count value of the data read counter i reaches the numerical value "63" again, that is, when the predetermined raster data is stored by 8 bits in each of the addresses [512] to [767] of the memories R0 to R7. , Step 1
From 925, the process proceeds to step 1927, where it is determined whether or not the count value of the mode selection counter j is equal to the numerical value "3". At this stage, since j = 2, the process proceeds to step 1928 again, where the counter i is reset. Then, in step 1929, the count value of the counter j is counted up by “1”, and the process returns to step 1918.

At this time, since j = 3, in step 1918, “3” is set as the set value of the selection switching mode for the multiplexers M0 to M7 (Tables 1 to 8). Next, the routine proceeds to step 1919, where the counter k is reset.

Thereafter, the same routine as described above is repeated again, except that the multiplexers M0 to M7
.. D01; D00] of the 32-bit raster data [D31; D30;... D01; D00] read from the memories C0 to C7.
Only bit data [D07; D06;... D01; D00] are selected by the multiplexers M0 to M7 and written into the memories R0 to R7 (Tables 1 to 8).

When the above routine is executed, step 1925 is executed.
When the count value of the data read counter i reaches the numerical value "63" again, that is, when predetermined raster data is stored by 8 bits at each address [768] to address [1023] of the memories R0 to R7. , Step 1
From 925, the process proceeds to step 1927, where it is determined whether or not the count value of the mode selection counter j is equal to the numerical value "3". Since j = 3 at this time, step 19
From 27, the process proceeds to step 1930, where the counters i and j are reset, respectively.

Thus, at this time, the memories R0 to R0
In FIG. 7, 32 bits of raster data to be drawn and recorded by each of the 2048 LEDs 40 of the drawing head 38 are stored in a manner as shown in FIGS.

At step 1931, it is determined whether or not the count value of the address counter m is equal to the numerical value "2999". At this stage, since m = 0, step 193 is executed.
2, the count of the address counter m is incremented by "1".
Return to 8. At this time, the routine consisting of steps 1918 to 1929 is repeated again. At this time, when the address signal is output to each of the memories C0 to C7 from the first address signal generating circuit 44D, the address accessed by the address signal becomes 1 Only the address is advanced. For example, in the case described above, when an address signal is output from the first address signal generation circuit 44D to the memory C0, the address signal accesses the address [0] of the memory C0 (actually, Although the address [31] is accessed for the address offset), the address [1] is accessed to count up the count value of the address counter m to "1" (FIG. 9).

Note that the first address signal generation circuit 44D
When an address signal is output from the memory to the memories C0 to C7, the address to which the address signal is to be actually accessed can be expressed by the following equation. m + (k + i) x 3000 + address offset amount

For example, the address of the memory C0 shown in FIG.
Considering the case where an address signal for accessing [0] is output, the count value of the counter i is “0”.
The count value of the address counter m is also "0", and the address offset counter k is also "0". Therefore, only the term "address offset amount" remains in the above equation, and the address signal is actually As described above, the address [31] of the memory C0 is accessed. Similarly, considering the case where the count value of the address counter m is incremented by “1”, the above equation is “1 (m) + the amount of address offset”. Address [31] will be accessed.

On the other hand, the address [3] of the memory C0 shown in FIG.
000] is output, the count values of the counter i and the address counter m are both “0”, and the address offset counter k is “1”. The formula is "3000
Therefore, the address signal actually accesses the address [3023] of the memory C0 as described above. Similarly, address counter m
Considering the case where the count value of “1” is counted up by “1”, the above equation is “1 (m) + 3000 + address offset amount”. In this case, the address signal is stored in the address [3024] of the memory C0. Will have access.

Therefore, when the count value of the address counter m reaches the numerical value "2999" in step 1931, all the raster data, that is, all the line numbers "0000" to "2047" are read from the memories C0 to C7. Is read and stored in the memories R0 to R7. 15 through FIG.
8 shows only the first 32 bits of each of the line numbers “0000” to “2047”. When all raster data from the line numbers “0000” to “2047” are stored, Memory R0 to memory R
The final address in each of 7 is [12000 = 96000/8].

From the line number “0000” to the line number “204”
When all the raster data up to 7 "has been read and stored in the memories R0 to R7, that is, in step 193
When m = 2999 in step 1, 1933 (FIG. 2)
Proceed to 1), where the second data changeover switch circuit 44
F is connected to the output side.

At step 1934, the drawing record counter c is reset, and then at step 1935, the memory selection counter d is reset.

At step 1936, one of the memories R0 to R7 is selected according to the count value of the memory selection counter d. Table 14 below shows which of the memories R0 to R7 is selected according to the count value of the memory selection counter d.

[0146]

[Table 14]

At this stage, since the count value of the memory selection counter d is "0", the memory R7 is selected, as apparent from Table 14, and then, in step 1937, the data read counter e is reset.

At step 1938, 8-bit data [D31;... D31] is read from address [0] of the memory R7 (FIG. 18), and the 8-bit data [D31;... D31] is passed through the selector circuit 44J. It is output to the drawing synchronization circuit 50.

Next, at step 1939, it is determined whether or not the count value of the data read counter e is equal to the numerical value "255 (2048/8)". At this stage, since e = 0, the process proceeds to step 1940, where the count value of the data read counter e is incremented by "1", and the process returns to step 1938.

Subsequently, at step 1938, the memory R
, D31] is read from the address [1] of No. 7, and the 8-bit data [D31;... D31] is output to the drawing synchronization circuit 50 via the selector circuit 44J. In step 1939, it is determined again whether or not the count value of the data read counter e is equal to the numerical value "255". At this stage, since e = 1, step 194 is executed.
0, and the count value of the data read counter e is counted up by “1”.
Return to 8 again.

In short, the routine consisting of steps 1938 to 1940 corresponds to the address of the memory R7.
This operation is repeated until all 2048-bit raster data [D31] from [0] to address [255] are read.

When e = 255 in step 1939, that is, from address [0] to address [255] of the memory R7
When reading of all the raster data [D31] for 2048 bits up to is confirmed, the process proceeds from step 1939 to step 1941, where it is determined whether or not the count value of the memory selection counter d is equal to the numerical value "7". You. At this stage, since d = 0, the process proceeds to step 1942, where the count value of the memory selection counter d is counted up by “1”, and the process returns to step 1936.

On the other hand, all 2048-bit raster data from address [0] to address [255] in the memory R7
When [D31] is read and sent to the drawing synchronization circuit 50,
In the multi-beam writing apparatus shown in FIG.
2048 LEDs 40 of raster data [D
31] at a time, thereby performing drawing recording based on 2048-bit raster data [D31]. After the drawing recording, the drawing head 38 moves one dot (pixel) along the main scanning direction. Shifted by minutes.

When the process returns from step 1942 to step 1936, since d = 1, the memory R6 is selected as is clear from Table 14. Next, at step 1937, the data read counter e is reset.

At step 1938, 8-bit data [D30;... D30] is read from address [0] of the memory R6 (FIG. 18), and the 8-bit data [D30;... D30] is passed through the selector circuit 44J. It is output to the drawing synchronization circuit 50.

Next, at step 1939, it is determined whether or not the count value of the data read counter e is equal to the numerical value "255". At this stage, since e = 0, the process proceeds to step 1940, where the data read counter e
Is incremented by "1", and the process returns to step 1938.

Subsequently, at step 1938, the memory R
, D30] is read from the address [1] of No. 6 and the 8-bit data [D30;... D30] is output to the drawing synchronization circuit 50 via the selector circuit 44J. In step 1939, it is determined again whether or not the count value of the data read counter e is equal to the numerical value "255". At this stage, since e = 1, step 194 is executed.
0, and the count value of the data read counter e is counted up by “1”.
Return to 8 again.

In short, the routine consisting of step 1938 to step 1940 is executed at the address of the memory R6.
This operation is repeated until all 2048-bit raster data [D30] from [0] to address [255] are read.

When e = 255 in step 1939, that is, from address [0] to address [255] of the memory R7
When reading of all the raster data [D30] for 2048 bits up to the above is confirmed, the process proceeds from step 1939 to step 1941, where it is determined again whether or not the count value of the memory selection counter d is equal to the numerical value "7". Is done. At this stage, since d = 1, the process proceeds to step 1942, where the count value of the memory selection counter d is "1".
, And return to step 1936 again.

On the other hand, as in the case described above, the memory R6
When all 2048-bit raster data [D30] from address [0] to address [255] are read out and sent to the drawing synchronizing circuit 50, the multi-beam drawing apparatus shown in FIG. Are driven at a time based on the raster data [D30] for 2048 bits, and the drawing recording is performed based on the raster data [D30] for 2048 bits. Reference numeral 38 is shifted by one dot (pixel) along the main scanning direction.

Similarly, raster data [D29], [D28], [D27], [D26], [D2] of 2048 bits from the address [0] to the address [255] of each of the memories R5 to R0.
5] and [D24] are sequentially read out and sent to the drawing synchronizing circuit 50, and the drawing recording based on the respective 2048-bit raster data is performed.

At step 1041, the memory selection counter d
Is equal to the numerical value "7", that is, 2048 bits of raster data [D31] from address [0] to address [255] of each of the memories R7 to R0,
[D30], [D29], [D28], [D27], [D26], [D25] and
When the drawing recording based on [D24] is completed, step 19
From 41, the process proceeds to 1943, where it is determined whether or not the count value of the drawing record counter c is equal to the numerical value "12000 (96000/8)". That is, it is determined whether or not the drawing recording for 96000 bits included in each of the line numbers “0000” to “2047” has been completed.

At this stage, since the count value of the drawing record counter c is "0", the process proceeds from step 1943 to step 1944, where the count value of the drawing record counter e is incremented by "1". 1
Return to 935.

At this time, the count value of the memory selection counter d is "7", but the memory selection counter d is reset in step 1935. Next, the same routine as described above is sequentially repeated, whereby raster data is sequentially read from each address of the memories R7 to R0 in 8-bit units in the same manner as in the case described above. When the number of read bits of such raster data becomes 2048, drawing recording based on the raster data is sequentially performed.

When c = 12000 in step 1943, that is, when the drawing recording of 96000 bits included in each of the line numbers “0000” to “2047” is completed, the process proceeds from step 1943 to step 1945. Then, it is determined whether the conversion from the vector data to the raster data has been completed. That is, it is determined whether or not the drawing data to be drawn still remains. If there is drawing data to be drawn, the process returns to step 1901 and the above-described routine is repeated.

In the above embodiment, an example is shown in which the raster data processing apparatus according to the present invention is incorporated in a multi-beam drawing apparatus using light-emitting diodes. However, a raster drawing apparatus using a plurality of laser beams is also used. It should be understood that it is applicable.

[0167]

As is apparent from the above description, in the raster data processing apparatus according to the present invention, even if the number of light beams used is greatly increased, the circuit configuration itself is unrealistically complicated. It is possible to cope with a drastic increase in the number of light beams used at low cost.

[Brief description of the drawings]

FIG. 1 is a schematic perspective view of a multi-beam drawing apparatus incorporating a raster data processing apparatus according to the present invention.

FIG. 2 is a schematic diagram of a drawing head provided in a beam irradiation unit of the multi-beam drawing apparatus of FIG.

FIG. 3 is a block diagram of the multi-beam writing apparatus of FIG. 1;

FIG. 4 is a schematic diagram showing raster data developed on a bit map memory shown in FIG. 3;

FIG. 5 is a block diagram showing in detail a part of the block diagram of FIG. 1, that is, a raster data processing circuit constituting a raster data processing device according to the present invention;

FIG. 6 is a block diagram showing a part of the block diagram of FIG. 5;

FIG. 7 is a schematic diagram similar to the schematic diagram of FIG. 3 and shows the raster data expanded on the bitmap memory in more detail;

FIG. 8 is a schematic diagram showing a state in which raster data read from a bitmap memory is stored in eight memories according to the present invention.

FIG. 9 is a schematic diagram similar to the schematic diagram shown in FIG. 8,
FIG. 4 is a schematic diagram showing the storage state of raster data in more detail.

FIG. 10 is a diagram showing four of each of the eight memories shown in FIG. 9;
FIG. 9 is a part of a schematic diagram showing a read mode when raster data for a total of 32 lines is read in 32-bit units according to the present invention.

FIG. 11 is a table showing four of each of the eight memories shown in FIG. 9;
FIG. 11 is another part of the schematic diagram showing a read mode when raster data for a total of 32 lines is read in 32-bit units according to the present invention.

FIG. 12 is a diagram showing four of each of the eight memories shown in FIG. 9;
FIG. 13 is still another part of the schematic diagram showing a reading mode when raster data for a total of 32 lines is read in 32-bit units according to the present invention for each line.

FIG. 13 is a table showing four of each of the eight memories shown in FIG. 9;
It is the remaining part of the schematic diagram showing the reading mode when raster data for a total of 32 lines is read in 32-bit units according to the present invention for each line.

FIG. 14 is a block diagram showing a part of the block diagram of FIG. 5;

15 is a part of a schematic diagram showing a storage state when 32-bit raster data read from the eight memories shown in FIG. 9 according to the present invention is stored in eight memories in 8-bit units according to the present invention; is there.

16 is another schematic diagram showing a storage state when 32-bit raster data read from the eight memories shown in FIG. 9 according to the present invention is stored in eight memories in 8-bit units according to the present invention; Part.

17 is still another schematic diagram showing a storage state when 32-bit raster data read from the eight memories shown in FIG. 9 according to the present invention is stored in eight memories in 8-bit units according to the present invention; Part.

18 is a schematic diagram showing the storage state when 32-bit raster data read from the eight memories shown in FIG. 9 according to the present invention is stored in eight memories in 8-bit units according to the present invention. Part.

FIG. 19 is a part of a flowchart showing a raster data processing routine executed by the raster data processing device according to the present invention;

FIG. 20 is another part of a flowchart showing a raster data processing routine executed by the raster data processing device according to the present invention.

FIG. 21 is the remaining part of the flowchart showing the raster data processing routine executed by the raster data processing device according to the present invention.

[Explanation of symbols]

 32 Beam irradiation unit 38 Drawing head 40 LED 42 System controller 44 Raster data processing circuit 44A First data changeover switch circuit 44B First data storage means 44C Address offset circuit 44D First address signal generation circuit 44E Multiplexer circuit 44F Second Data switching switch circuit 44G second data storage means 44I second address signal generation circuit 44J selector circuit 50 drawing synchronization circuit 52 drawing timing clock generation circuit

Claims (2)

[Claims] 1. A raster data processing apparatus incorporated in a drawing apparatus for drawing a predetermined pattern by performing a modulation of the light beam on the basis of raster data while scanning an object to be drawn with a large number of light beams. A raster in the case where the plurality of light beams are arranged in the sub-scanning direction at a pixel arrangement pitch at the time of drawing and recording, and are arranged in the main scanning direction at an arrangement pitch of an integral multiple of the pixel arrangement pitch. In the data processing device, a bitmap memory that expands the raster data, a first raster data storage unit that reads and stores raster data from the bitmap memory in line order in the main scanning direction, and a first raster data storage unit When reading raster data from the main scanning direction line corresponding to the number of light beams from the First raster data reading means for reading raster data by offsetting the dress by an amount corresponding to the integral multiple, and converting the raster data read by the raster data reading means to a divisor corresponding to the integral multiple. A second raster data storage means for storing the data in a predetermined address order with the number of bits; a second raster data readout for reading out the raster data of a bit number corresponding to the number of the light beams from the second raster data storage means in the address order Raster data processing apparatus comprising: 2. The raster data processing device according to claim 1, wherein the bit map memory includes dummy data of a bit number smaller than the number of the light beams by at least one at both ends in the main scanning direction. A raster data processing device.