JPH1098693A - Image signal converter and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform an up conversion of an image signal at low cost and with a simple structured device. SOLUTION: The image signal with standard resolution of five lines is supplied by a scanning order conversion circuit 23 directly or via line memory 22-1 to 22-4. The scanning order conversion circuit 23 supplies the data in which an order of the line in an odd number field is reversed to an up conversion circuit 24 by switching a connection of a data bus by using a reference signal F whose signal level is different depending on the image signal inputted to an image signal converter 21 is of an even numbered field or the odd numbered field. When the image signal converted to the one with high resolution by the up conversion circuit 24 is supplied to a scanning order conversion circuit 25, it judges the image signal inputted in the image signal converter 21 whether the image signal is of the even numbered field or of the odd numbered field by using the reference signal F and when the image signal is judged to be of the odd numbered field, the data where the order of the line is reversed again is outputted to outside via an output terminal 27.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal conversion apparatus and method, and more particularly to a method for generating a higher resolution image signal based on an image signal having a predetermined resolution.
By inverting the order of scanning of the image signal of the odd field and the order of scanning of the image signal of the even field,
The present invention relates to an image signal conversion device and method that use the same up-conversion circuit in both processes.

[0002]

2. Description of the Related Art Conventionally, there has been an image converter for converting (upconverting) a standard resolution signal (SD signal) into a high resolution signal (HD signal).

[0005] FIG. 5 shows a case where an up-conversion is performed.
2 shows an SD signal before conversion and an HD signal after conversion of a predetermined field. In FIG. 5, pixels of the SD signal are indicated by white circles, and pixels of the HD signal are indicated by black circles. In FIG. 5, the horizontal direction indicates the horizontal direction, and the vertical direction indicates the vertical direction.

As shown in FIG. 5, an SD signal corresponding to an HD signal of one pixel is an SD signal of four pixels.
An HD signal having a data amount four times that of the input SD signal is generated. When the distance between adjacent scanning lines of the SD signal in a predetermined field (the distance between corresponding pixels on adjacent scanning lines) is 1,
The vertical distance from a predetermined pixel of the SD signal is
Two HD signal pixels are generated at the positions of 1/8 and 3/8, respectively. Then, in both the horizontal direction and the vertical direction, HD signals arranged at equal intervals are generated.

FIG. 6 shows the relationship between the time direction and the vertical direction at the pixel position of the HD signal generated by up-conversion. That is, in FIG. 6, the horizontal direction is the time direction, that is, continuous fields, the vertical direction is the vertical direction,
Each is shown.

As shown in FIG. 6, in order to arrange the pixels of the generated HD signal evenly in the space defined by the vertical direction and the time direction, the positions of the pixels of the even field and the positions of the pixels of the odd field are determined. In and, the distance of the SD signal from the pixel is inverted. That is, for example, in the K-th field, 3 /
The corresponding HD signal pixels are generated at positions 8 and 1/8 downward, respectively, but in the (K + 1) th field, the pixels of the SD signal are shifted upward by 1/8 from the pixels of the SD signal. At the 3/8 position, corresponding HD signal pixels are respectively generated.

FIG. 7 is a block diagram showing a configuration of an example of a conventional image signal conversion device 1. As shown in FIG.

The SD signal as an input signal is supplied to a field memory 11-1 and a field memory 11-2. The SD signals stored in the field memories 11-1 and 11-2 are controlled by the address control circuit 15. That is, the address control circuit 15
Controls the writing timing by using a reference signal F having different signal levels when the image signal input to the image signal converter 1 is an even field and an odd field. For example, the SD signal of the odd field is
The SD signal of the even field stored in the field memory 11-1 is stored in the field memory 11-2.

The address control circuit 15
Field memory 11-1 and field memory 11-2
Are performed alternately, and the order of reading data is reversed between the field memory 11-1 and the field memory 11-2.
That is, for example, the data of the odd field stored in the field memory 11-1 is read out in descending order from the maximum line, while the data in the field memory 11-2 is read out.
Are read from the smallest line in ascending order.

The field data read out in this manner is supplied to the up-conversion circuit 13 directly or via the line memories 12-1 to 12-4 in units of data for predetermined five lines. It has been made.

The up-conversion circuit 13 generates (classifies) a class corresponding to the input data from the data (input data) of seven pixels in the vicinity of a predetermined pixel of interest from the data of the five lines. By calculating a predetermined linear linear combination expression using coefficients corresponding to the class, pixel data of four HD signals corresponding to the pixel of interest is generated, and stored in the field memories 14-1 and 14-2. It is made to supply. Field memory 14-1
And the timing of writing data to the field memory 14-2 are controlled by the address control circuit 15. For example, odd-numbered field data is stored in the field memory 14-1, and even-numbered field data is stored in the field memory 14-2. , To be remembered.

The data stored in the field memory 14-1 and the field memory 14-2 are controlled by the address control circuit 15 in read timing and order. That is, the data of the odd field stored in the field memory 14-1 is read out in descending order from the maximum line, whereas
The data of the even-numbered field stored in 2 is read in ascending order from the smallest line. Therefore,
Odd field data is stored in the field memory 11-1.
, The data is read out in descending order from the data of the largest line and processed, and then read out again from the field memory 14-1 in descending order. As a result, the data is output in the same order as the input line data. Will be.

In this manner, the input data obtained by inverting the order of the data of the even field data and the odd field data is supplied to the up-conversion circuit 13,
Further, the data after the up-conversion is output by reversing the order of the data again with the data of the even field and the data of the odd field. Therefore, the same up-conversion processing can be applied when processing data in even-numbered fields and when processing data in odd-numbered fields.

[0014]

However, in the conventional image signal conversion apparatus 1, in order to invert the order of input and output to the up-conversion circuit 13 between even field data and odd field data, Field memories 11-1, 11-2, 14-1, 14-2,
In addition, the address control circuit 15 is required, and the circuit scale becomes large, and it is difficult to realize the circuit at low cost.

The present invention has been made in view of such a situation, and is intended to realize an image signal conversion device having a simple configuration without using a field memory.

[0016]

An image signal conversion device according to claim 1 is a device which is located near an extracted pixel of interest.
When the above pixel data is in the even field,
An inverting means for inverting the order of scanning in the case of an odd field,
Converting means for converting the above pixel data into a second image signal having a second resolution higher than the first resolution; and outputting the second image signal in an even field, an odd field, And output means for further reversing and outputting the order of scanning.

According to a third aspect of the present invention, in the image signal conversion method, two or more pieces of pixel data located in the vicinity of the extracted pixel of interest are inverted in the order of scanning between an even field and an odd field. Then, the two or more pixel data located near the inverted target pixel are converted into a second image signal having a second resolution higher than the first resolution, and the output second image signal is output. Are further inverted in the order of scanning in the case of the even field and the case of the odd field, and are output.

In the image signal conversion device according to the first aspect, the inverting means converts two or more pieces of pixel data located in the vicinity of the extracted pixel of interest into an even field and an odd field. The scanning order is inverted, and the conversion unit converts the two or more pixel data located near the inverted target pixel into a second image signal having a second resolution higher than the first resolution. The output means outputs the output second image signal after reversing the order of scanning in the case of the even field and the case of the odd field.

In the image signal conversion method according to the third aspect, the order of scanning depends on whether the extracted two or more pixel data located in the vicinity of the target pixel are in an even field or in an odd field. Two or more pixel data located in the vicinity of the inverted and inverted target pixel are converted to a second image signal having a second resolution higher than the first resolution, and the output second image is output. The scanning order is further inverted when the signal is in the even field and in the odd field, and is output.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below. In order to clarify the correspondence between each means described in the claims and the following embodiments, parentheses after each means are described. Within
The characteristics of the present invention will be described as follows by adding a corresponding embodiment (but one example). However, of course,
It does not mean that each means is limited to those described.

The image signal conversion device according to the first aspect of the present invention provides an extracting means for extracting, from a first image signal having a first resolution, two or more pixel data located in the vicinity of a target pixel (for example, FIG. 1). Line memories 22-1 to 22-4) and two or more pixel data located in the vicinity of the pixel of interest extracted by the extraction means are used for scanning in an even field and an odd field. Inverting means for inverting the order (for example, the scanning order conversion circuit 23 in FIG. 1), and two or more pixel data located in the vicinity of the pixel of interest inverted by the inverting means are converted into second data having a resolution higher than the first resolution. Conversion means (for example, the up-conversion circuit 24 in FIG. 1) for converting the second image signal into a second image signal having the resolution of As in de, in the case in the odd field, output means the order of the scanning, further inverts and outputs (e.g., scanning of Figure 1 sequence inverting circuit 2
5).

FIG. 1 is a block diagram showing the configuration of an embodiment of the image signal conversion device 21 of the present invention.

An SD signal as an input signal is directly or in a line memory 22 in units of data for predetermined five lines.
-1 to the scanning order conversion circuit 23 via the line memory 22-4.

The scanning order conversion circuit 23 responds to the reference signal F having a different signal level when the image signal input to the image signal conversion device 21 is an even field and an odd field, according to the input SD signal. Is determined as to whether or not the input SD signal is data of an odd field, and if it is determined that the input SD signal is data of an odd field, the order of the input data is inverted and the up conversion circuit 2
4. That is, specifically, when the input SD signal receives the input of the reference signal F corresponding to the data of the odd field, the scanning order conversion circuit 23 outputs the data of the n-th line directly input from the input terminal 26. , Line memory 22-1 to line memory 22
-4, the data of the (n + 2) th, (n + 4) th, (n + 6) th, and (n + 8) th lines are inverted in the input order, and the nth +8, n + 6, n + 4, n + 2, and input terminals corresponding to the n-th line.

The up-conversion circuit 24 generates an HD signal corresponding to the SD signal of the even field. That is, the up-conversion circuit 24
A class is generated based on pixel data in the vicinity of the pixel of interest including the pixel of interest, a coefficient of a linear linear combination equation corresponding to the class is read out from the built-in ROM, and a linear one-coupling equation is calculated using the coefficient. The HD that corresponds to the pixel of interest by calculating the following
The pixel data of the signal is generated and supplied to the scanning order conversion circuit 25.

The scanning order conversion circuit 25 determines whether or not the HD signal supplied from the up-conversion circuit 24 is data of an odd field according to the reference signal F, similarly to the scanning order conversion circuit 23. When it is determined that the supplied HD signal is data of an odd field, the scanning order of the HD signal is inverted and output to the output terminal 27.

FIG. 2 is a block diagram showing the configuration of one embodiment of the up-convert circuit 24.

The predetermined five lines of data supplied from the scanning order conversion circuit 23 via the terminals I0 to I4 are input to the delay elements 31-1 to 31-6 of the up-conversion circuit 24. Has been made. The pixel data in the vicinity of the target pixel including the target pixel is extracted by these delay elements 31-1 to 31-6 and supplied to the class classification circuit 32, and the product-sum operation circuit 34
And the product-sum operation circuit 35.

The classifying circuit 32 includes a delay element 31-1.
The pixel data in the vicinity of the target pixel supplied from the delay element 31-6 is classified into a predetermined class represented by a quantization code of a plurality of bits, and the classification result is output to the coefficient memory 33.

The coefficient memory 33 stores linear linear coefficients corresponding to each class generated by using the least squares method or the like, based on the classification results of the classes supplied from the classification circuit 32. Then, a coefficient corresponding to each tap is read and output to the product-sum operation circuit 34 and the product-sum operation circuit 35.

The product-sum operation circuit 34 and the product-sum operation circuit 35
A linear first-order product-sum operation is performed on the pixel data in the vicinity of the pixel of interest using the coefficient supplied from the coefficient memory 33, and pixel data of the HD signal corresponding to the pixel of interest (HD data shown in FIGS. 5 and 6). From the pixel of the signal, data of a pixel at a distance of 1/8 (X) or 3/8 (Y)) is generated and output to the scanning order inversion circuit 25.

Next, a specific processing operation of the image signal conversion device 21 will be described with reference to a flowchart of FIG.

In step S 1 of FIG. 3, the SD signal as an input signal is supplied to the image signal conversion device 21 through the input terminal 26.
When the SD signal is input to the SD memory, the data of the predetermined five lines are respectively stored directly or in the line memory 22.
-1 to the scan order conversion circuit 23 via the line memory 22-4.

In the following step S2, the scanning order conversion circuit 2
3 determines whether the input field data is even field data or odd field data based on the signal value of the reference signal F whose signal level switches in field units.

If it is determined that the input field data is even field data, step S4
, And when it is determined that the input field data is odd field data (reference signal F
Is determined to be one level), in step S3, the scanning order conversion circuit 23 sets the data buses of the input five lines to the opposite order of the input as shown in Table 1. The connection is switched so that an output in the order of is obtained.

[0036]

[Table 1]

That is, for example, the scanning line order conversion circuit 2
When the order of the data of the five lines input to No. 3 is the order of data A to data E, when the signal value of the reference signal F is at the 0 level (when the data of the even field is input), The order of output to the up-conversion circuit 24 without switching the connection of the data bus is the order of data A to data E, but when the signal value of the reference signal F is at one level (data of an odd field is input. ), The connection of the data bus is switched, and the order of output to the up-conversion circuit 24 is the reverse of the order of input, that is, the order of data E to data A.

In the subsequent step S4, the delay elements 31-1 to 31-46 of the up-conversion circuit 24 determine the five lines input to the input terminals I0 to I4 from the data of the five lines.
The pixel data of the pixel located in the vicinity of the predetermined pixel of interest and the pixel data of the pixel of interest are extracted and supplied to the classifying circuit 32.
To supply.

For example, as shown in FIG.
Assuming that pixel data of pixels g1 to g6 in the vicinity are represented by pixel data G0 to G6, pixel data G1 of the n-th line is extracted by the delay circuit 31-1 and supplied to the class classification circuit 32. Together with the product-sum operation circuit 3
4 and the product-sum operation circuit 35. Similarly, pixel data G2 on the (n + 2) th line, pixel data G5 on the (n + 4) th line,
G0, G6, pixel data G3 of the (n + 6) th line, and (n + 8) th
The pixel data G4 of the line is output from the delay circuit 31-
2, input terminal I1, delay circuits 31-3, 31-4, 31-
5 or 31-6, which is extracted and classified
Is supplied to the product-sum operation circuit 34 and the product-sum operation circuit 35.

The class classification circuit 32 performs a dynamic range coding (ADRC) process on each of the pixel data G0 to G6 to generate (classify) a class corresponding to the set of the pixel data G0 to G6. I do.

That is, a dynamic range DR (maximum signal value-minimum signal value) of pixel data is obtained, and the dynamic range DR is divided by, for example, k bits (2 ^ k) to quantize each signal level. Pixel data G0 to G6
Are determined by finding the ADRC code C in equation (1) (^ indicates a power). C = (X-minimum signal value) / (DR / 2 ^ k) (1)

The set of pixel data quantized by the equation (1) is represented by a plural-bit quantization code.

For example, each of the pixel data G0 to G6 is set to a value which is larger or smaller than 1/2 of the dynamic range.
It is represented by bit data (when k in Equation (1) is set to 1, whether the ADRC code C is larger or smaller than 0.5 is represented by 1 bit data). By doing so, the pixel data G
Since 1-bit information is obtained for each of 0 to G6, a total of 7-bit (2 ^ 7 = 128) classes can be generated. In this manner, the input data (a set of pixel data G0 to G6) can be associated (classified) with any of the 128 classes.

In the following step S5, the coefficients corresponding to the class (the class corresponding to the set of pixel data G0 to G6) classified in step S4 are read out from the coefficient memory 33, and the product-sum operation circuit 34 It is supplied to the arithmetic circuit 35. The coefficients stored in the coefficient memory 33 are determined in advance by a predetermined method, for example, a least-squares method of finding coefficients as a solution of a normal equation defined by a teacher signal input during the learning period and input data. It has been generated.

In the subsequent step S6, the product-sum operation circuit 34
Is obtained by multiplying the individual pixel data G0 to G6 by the coefficient supplied from the coefficient memory 33, and adding all of the signals (by performing a linear linear combination operation) to the target pixel g0. The pixel data X1 and X2 of the corresponding pixel x1 and x2 of the HD signal (data of the pixel located at a distance of 1/8 from the pixel of the SD signal shown in FIGS. 5 and 6) are generated, and are sent to the scanning order conversion circuit 25. Supply. Similarly, the product-sum operation circuit 34 also outputs the pixel y1 of the HD signal corresponding to the target pixel g0.
And y2 pixel data Y1 and Y2 (data of a pixel at a distance of 3/8 from the pixel of the SD signal shown in FIGS. 5 and 6) are generated and supplied to the scanning order conversion circuit 25.

Subsequently, in step S7, the scanning order conversion circuit 25 determines, based on the signal value of the reference signal F, whether the input field data is even field data or odd field data. to decide.

If it is determined that the input field data is even field data, step S9 is performed.
, And when it is determined that the input field data is odd field data (reference signal F
Is determined to be one level), in step S8, the scanning order conversion circuit 25 connects as shown in Table 2 such that an output in an order opposite to the input order is obtained ( Data bus).

[Table 2]

That is, when the signal value of the reference signal F is at the 0 level (when data of an even field is being processed), the data X1 and X2 are supplied to the output terminal 27-1 in the order of the input lines. Output terminal 27-
2, the data Y1 and Y2 are supplied. When the signal value of the reference signal F is at the 1 level (when processing the data of the odd field), the order of the input lines is reversed. The data Y1 and Y2 are supplied to the output terminal 27-1 and the data X1 and X2 are supplied to the output terminal 27-2.

Then, in step S9, the HD signal generated based on the SD signal is output to the output terminal 27-1 and the output terminal 2
The signal is output to a predetermined signal processing mechanism via 7-2.

Although the scan order conversion circuits 23 and 25 invert the scan order of the odd field, when the up-convert circuit 24 is designed to up-convert the SD signal of the odd field, The scanning order is reversed.

As described above, the order of the data processing at the time of up-conversion can be reversed between the even field data and the odd field data.

Further, since the order of data processing can be reversed simply by switching the connection of the data bus without using the field memory, a simple configuration and an inexpensive image signal conversion device can be realized. it can.

In the above embodiment, the class classification has been described with respect to an example in which one pixel data is represented by one bit. Of course, one pixel data may be represented by a plurality of bits. Also, as a class classification method, AD
In addition to RC, a method using PCM data, DPCM (prediction coding), or the like may be used. Further, the coefficients stored in the coefficient ROM 47 may be obtained without using the least squares method. In addition, the present invention can be applied to a VCR and the like in addition to a TV receiver.

[0054]

As described above, according to the image signal conversion apparatus according to the first aspect and the image signal conversion method according to the third aspect, the extracted pixel data is obtained in the even field and in the odd field. In some cases, the order of scanning is inverted, the inverted pixel data is converted into a second image signal having a second resolution higher than the first resolution, and the output second image signal is converted to a second image signal. Since the order of scanning is further inverted in the case of the even field and the case of the odd field, the image signal conversion device having a simple configuration can be realized at low cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an image signal conversion device 21 of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an embodiment of an up-conversion circuit 24;

FIG. 3 is a flowchart illustrating a processing operation of the image signal conversion device 21.

FIG. 4 is a diagram illustrating a method of classifying pixel data G0 to G6 into a predetermined class.

FIG. 5 is a diagram illustrating horizontal and vertical pixel positions when an HD signal is generated from an SD signal.

FIG. 6 is a diagram illustrating pixel positions in a time direction and a vertical direction when an HD signal is generated from an SD signal signal.

FIG. 7 is a block diagram illustrating a configuration of an example of a conventional image signal conversion device 1.

[Explanation of symbols]

1 image signal converter, 11-1, 11-2 field memories, 12-1 to 12-4 line memories,
13 Up-conversion circuit, 14-1, 14-2
Field memory, 15 address control circuit, 21 image signal conversion device, 22-1 to 22-
4 line memory, 23 scanning order conversion circuit, 24
Up-conversion circuit, 25 scanning order conversion circuit,
26 input terminals, 27-1, 27-2 output terminals,
31-1 to 31-6 delay element, 32 class classification circuit, 33 coefficient memory, 34, 35 product-sum operation circuit

Claims (3)

[Claims] An extracting means for extracting, from a first image signal having a first resolution, two or more pieces of pixel data located in the vicinity of a target pixel; Inverting means for inverting the order of scanning between two or more pixel data located in an even field and in an odd field, two or more pixel data located near the target pixel inverted by the inverting means. A conversion unit for converting the pixel data into a second image signal having a second resolution higher than the first resolution; and a case where the second image signal output from the conversion unit is in an even field. And an output means for further reversing and outputting the order of scanning in the case of an odd field. 2. The image signal conversion apparatus according to claim 1, wherein said inverting means and said output means invert the order of scanning by switching connections. 3. Extracting two or more pixel data located in the vicinity of a target pixel from a first image signal having a first resolution, and extracting two or more pixel data located in the vicinity of the extracted target pixel. The order of scanning is inverted between the case of the even field and the case of the odd field, and two or more pixel data located in the vicinity of the inverted pixel of interest are replaced with a second data having a resolution higher than the first resolution. Converting the output second image signal into a second image signal having a resolution of 2 and outputting the second image signal after reversing the order of scanning between an even field and an odd field. An image signal conversion method characterized in that: