JPH1098175A - Mos-type solid-state image pickup device and driving method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a fine unit cell, without reducing the dynamic range by providing a second conductivity type second conductive region having a concn. different from that of a first conductivity type, and insufficient for depleting the interface of a semiconductor substrate. SOLUTION: The unit cell of an MOS-type solid-state image pickup device has a p-type diffusion region 81 over the entire surface of an n-type diffusion layer forming a photodiode. This region 81 has a concn. higher than that of an n-type diffusion region, and its potential is fixed to a reference. The concn. of the region 81 is not sufficient to deplete the interface of a semiconductor substrate. The region 81 is formed on the entire surface of the n-type diffusion layer forming the photodiode, thereby lowering the potential of the n-type diffusion layer. Thus all or almost of charged remain when reset are stored in a detection part, resulting in a substantially small capacity of the photodiode and reduced thermal noise generated at resetting.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a MOS type solid-state imaging device and a driving method thereof.

[0002]

2. Description of the Related Art In recent years, various amplification type solid-state imaging devices have been proposed as one of MOS type solid-state imaging devices. This type of MOS solid-state imaging device amplifies a signal voltage due to a signal charge in each pixel, and can improve sensitivity, which is a problem when pixels are miniaturized.

FIG. 18 is a circuit diagram showing an outline of such a MOS type solid-state imaging device. As shown in the figure,
The unit cell of this MOS type solid-state imaging device includes an amplifier that amplifies signals of the photodiode 1 (1-1-1 to 1-2-2) and the photodiode 1 (1-1-1 to 1-2-2). Transistor 2 (2-1-1 to 2-2-2), vertical select transistor 3 (3-1) for selecting a line from which a signal is read out.
-1 to 3-2-2) and reset transistors 4 (4-1-1 to 4-2-2) for resetting signal charges.

[0006] Here, a diagram in which 2 × 2 unit cells are arranged two-dimensionally is shown, but actually more unit cells are arranged.

The horizontal address lines 6 (6-1, 6-2) wired in the horizontal direction from the vertical shift register 5 are connected to the gates of the vertical selection transistors 3 (3-1-1 to 3-2-2). To determine the line from which the signal is read.

The reset line 7 (7-1, 7-2) is connected to the gate of the reset transistor 4 (4-1-1 to 4-2-2). Amplification transistor 2 (2-1-1)
To 2-2-2) are the vertical signal lines 8 (8-1, 8-).
Connected to 2).

A load transistor 9 (9-1, 9-2) is connected to one end of the vertical signal line 8 (8-1, 8-2), and one line (one row) is connected to the other end. Signal capturing transistor 10 (10-1, 10-
2), is connected to an amplified signal storage capacitor 11 (11-1, 11-2) for storing one line (one row) of signals, and is selected by a selection pulse supplied from the horizontal shift register 13. Horizontal selection transistor 12
It is connected to the horizontal signal line 15 via (12-1, 12-2).

Hereinafter, the operation of the MOS type solid-state imaging device will be described with reference to a timing chart of FIG. When an address pulse 21-1 for setting the horizontal address line 6-1 to a high level is applied, only the selection transistors 3-1-1 and 3-1-2 of this line are turned on, and the amplification transistors 2-1 of this row are turned on. A source-follower circuit is constituted by 1, 1-2-1 and the load transistors 9-1 and 9-2.

As a result, the amplification transistor 2-1
Gate voltages of 1, 1-2-2, that is, voltages substantially equal to the voltages of the photodiodes 1-1-1, 1-1-2 appear on the vertical signal lines 8-1, 8-2.

At this time, the signal capturing transistor 10
A signal capture pulse is applied to the common gates 14-1 and 10-2, and the voltages appearing on the vertical signal lines 8-1 and 8-2 and the products of the capacitances are applied to the amplified signal storage capacitors 11-1 and 11-2. The amplified signal charge is stored.

After the signals are stored in the amplified signal storage capacitors 11-1 and 11-2, the reset transistors 4-1 and 4-1 are reset.
A reset pulse 22-1 is applied to -1-2 to reset the signal charges accumulated in the photodiodes 1-1-1 and 1-1-2.

Next, horizontal selection pulses 23-1 and 23-2 are sequentially applied from the horizontal shift register 13 to the horizontal selection transistors 12-1 and 12-2, and one row of output signals 24- Take out 1,4-2-2 sequentially.

By continuing this operation sequentially with the next line, all signals of the photodiodes arranged two-dimensionally can be read. FIG.
FIG. 3 is a diagram showing a layout of a unit cell of such a MOS solid-state imaging device. FIG. 21 is a cross-sectional view showing a cross section of the unit cell.

In FIG. 1, reference numeral 31 denotes an amplification gate which is a control electrode of an amplification transistor; 32, a reset gate;
Reference numeral 3 denotes a detection unit, reference numeral 34 denotes a photodiode serving as a photoelectric conversion unit, reference numeral 35 denotes an electrode connecting the amplification gate and the detection unit, and reference numeral 36 denotes a reset drain.

Reference numeral 37 denotes a p-type substrate; 38, an n-type diffusion layer forming a photodiode; 39, an n-type diffusion layer forming a detector; and 40, an address gate. FIG.
FIG. 21 is a diagram showing a potential distribution along arrow AA ′ in FIG. 20.

In the same figure, when t = 1,
A state in which signal charges are accumulated in the photodiode 34 is shown, and a state at the time of reset is shown in a state of t = 2, and a state after reset is shown in a state of t = 3.

In the amplification type solid-state imaging device having the structure shown in FIG. 18, since the charges of the photodiodes in each unit cell are sequentially read out for each row, the signal accumulation timings of the photodiodes in each row are different. There's a problem. In particular, there is a serious problem that the shape of the subject is distorted and reproduced when the subject moves in the horizontal direction on the screen.

To solve such a problem, FIG.
There is a MOS type solid-state imaging device having a configuration as shown in FIG. Note that the same parts as those in FIG.
The MOS solid-state imaging device differs from the MOS solid-state imaging device shown in FIG. 18 in the structure of the basic cell.

That is, in the unit cell of this MOS type solid-state imaging device, the address capacitors 53 (53-1-1 to 53-3-3) are connected to the horizontal address lines 6 (6-1 to 6) instead of the vertical selection transistors. -3) and the amplification transistor 2 (2-
1-1 to 2-3-3).

The photodiode 1 (1-1-1 to 1-1-1)
1-3-3) and the amplifying transistor 2 (2-1-2-1).
The transfer transistors 54 (54-1-1 to 54-3-3) are connected between the gates of the transfer transistors 1 to 2-3-3).

The gate of the transfer transistor 54 is connected to the transfer signal line 52 (52-1 to 52-3). The transfer transistor 54 is connected to the transfer signal line 52 (5
When a pulse signal is input from 2-1 to 52-3), the charges accumulated in the photodiode 1 (1-1-1 to 1-3-3) are transferred to the address capacitors 53 (53-1-1 to 53-3). -3
-3) and the detection unit 55 (55-1-1 to 55-3-3).

The detector 55 (55-1-1 to 55-3-)
3) is a transfer transistor 54 (54-1-1 through 54-).
This is a part for detecting the charge of the phototransistor 1 (1-1-1 to 1-3-3) transferred to the address capacitor 53 via 3-3) as a voltage.

Next, the operation of such a MOS type solid-state imaging device will be described with reference to the timing chart of FIG. The description of the operation of the noise reduction circuit is omitted.

FIG. 24 shows only the last period of the vertical blanking period (V-BLK) and the first two horizontal periods. The timing chart of FIG.
Although pixels are assumed, there are actually horizontal selection registers for the number of horizontal pixels.

First, in the vertical blanking period V-BLK, transfer pulses 41 (41-1 to 41-3) are added to all transfer signal lines 52 (52-1 to 52-3), and all the pixels are transferred. At the same time, the signal charges of the photodiode 1 are detected by the detection unit 55.
(53-1-1 to 55-3-3) and store them in the address capacity 53 (53-1-1 to 53-3-3).

As a result, it is possible to prevent a time difference from occurring in the imaging timing of each pixel. The method of simultaneously adding transfer pulses to all the transfer signal lines may be realized by connecting the transfer signal lines to each other to form one transfer signal line, or may be realized by each transfer signal line 52 (5
A pulse signal may be added simultaneously to 2-1 to 52-3).

Next, the first horizontal blanking period (H-BL
K) through the horizontal address line 6-1 in the first row,
The address pulse 42-1 is converted to an address capacity 53-1-1,
53-1-2 and 53-1-3.

The address capacity 53 (53-1-1 to 53-
By applying an address pulse to 1-3),
The potentials of the channels of the amplification transistors 2-1-1 to 2-1-3 increase as compared with the other lines, and the load transistors 9 (9-1 to 9-3) and the amplification transistor 2 (2-1-2-1).
1-2-1-3) constitute a source follower circuit.

Therefore, the photodiode 1 (1-1-1)
To 1-1-3) is detected by the detection unit 55 (55-1-1).
To 55-1-3), a voltage substantially equal to the signal voltage subjected to impedance conversion is applied to the clamp capacitor 60 (60-1 to 60-1).
-3) appears at the end.

Next, in order to sample the "0" level of the signal, a reset pulse 43-1 is applied to the reset line 7-1 of the first row to reset the reset transistor 4 (4-1-4-1).
1-4-1-3) is turned on, the reset gate is opened, and the signal charges of the detection unit 55 (55-1-1 to 55-1-3) are swept out to the drain.

Next, the reset is turned off and the reset level is sampled by the sample and hold circuit. next,
During the horizontal effective period, the horizontal shift register 13 applies the horizontal selection pulse 46 (46-1 to 46-3) to the horizontal selection transistor 18 (18-1 to 18-3) in order.
Photodiodes 1-1-1 to 1-1-3 for one line
Are sequentially output to the horizontal signal line 64.

After the output voltages of the photodiodes 1 (1-1-1 to 1-1-3) in the first row are sampled in this manner, the second voltage is similarly set in the next horizontal flyback period. An address pulse 41-2 is applied to the horizontal address line 6-2 of the line to apply a photodiode (1-2-1) of the second line.
１1-2-3) are read out, and output signals are sequentially output to the horizontal signal line 15.

By repeating the above-described operation sequentially for each line, the signals of all the two-dimensionally arranged photodiodes can be read. FIG.
FIG. 24 is a diagram showing a detailed configuration of a unit cell of the MOS solid-state imaging device shown in FIG. 23.

As shown in FIG.
1-1 is provided with an overflow control gate 71, and when the signal of the photodiode is saturated, the signal is discharged through the overflow control gate 71.

[0035]

However, FIG.
In a MOS solid-state imaging device as shown in FIG. 23, when resetting a detection unit and a photodiode connected to the detection unit by a reset transistor, thermal noise is superimposed on electric charges remaining in these portions.

The root mean square of the thermal noise charge at this time is Qn2
Is expressed as Qn2〓kTC (1), where C is the capacity of the region where the remaining charge is stored, T is the temperature at this time, and k is the Boltzmann constant, and is proportional to the storage capacity. However, FIG.
In a MOS solid-state imaging device as shown in FIG. 23, the area of a photodiode serving as a photoelectric conversion unit in a unit cell is increased in order to increase photoelectric efficiency.

For this reason, there has been a problem that since the charge storage capacity is increased, thermal noise at the time of reset is increased, and the image quality of the reproduced screen is deteriorated. In addition, the leak current generated in the depletion layer of the photodiode and the detection unit, particularly the leak current generated in the depletion layer at the interface of the semiconductor substrate, is accumulated together with the signal charge during the accumulation period, and is superimposed on the signal as noise. Therefore, there is a problem that the image quality of the reproduction screen is deteriorated.

In the MOS type solid-state imaging device shown in FIG. 23, it is necessary to provide four means of amplification, reset, address and transfer in one unit cell. However, when the four means are provided in one unit cell, when the unit cell is miniaturized, the aperture ratio is reduced and the sensitivity of the photodiode in the unit cell is deteriorated. There was a problem.

Further, in the case of providing a high-definition screen in the MOS type solid-state imaging device as shown in FIG. 23, it is naturally necessary to increase the number of pixels by miniaturizing the pixels. However, when pixels are miniaturized, the saturation signal amount of the photodiode decreases. In this state, for example, when strong light enters, the photodiode quickly saturates,
The saturated signal is discharged via charge discharging means such as the overflow control gate 71 shown in FIG. That is, in the conventional MOS-type solid-state imaging device, there is a problem that the dynamic range is reduced when the pixel size is reduced.

The present invention has been made in view of the above circumstances, and provides a MOS-type solid-state imaging device capable of preventing the deterioration of image quality of a reproduced screen caused by noise due to a leak current, and a driving method thereof. With the goal.

Another object of the present invention is to provide a MOS solid-state imaging device capable of realizing miniaturization of a unit cell without reducing the aperture ratio, and a driving method thereof. Further, the present invention provides an M-type memory cell capable of realizing miniaturization of a unit cell without lowering the dynamic range.
An object of the present invention is to provide an OS-type solid-state imaging device and a driving method thereof.

[0042]

Accordingly, to achieve the above object, a first aspect of the present invention is a MOS-type solid-state imaging device having a plurality of unit cells formed on a semiconductor substrate.
The unit cell is formed on a part of the semiconductor substrate,
A first conductivity type photoelectric conversion region that converts light into electric charge, and stores the electric charge converted in the photoelectric conversion region, and the first conductivity type formed on a part of the semiconductor substrate. A second region of a second conductivity type, which is formed on at least a part of the surface of the charge conversion region and the surface of the photoelectric conversion region and has a concentration that does not deplete the interface of the semiconductor substrate and is different from the first conductivity type;
And a conductive type region.

According to a second aspect of the present invention, there is provided a photoelectric conversion region of a first conductivity type formed on a portion of a semiconductor substrate for converting light into electric charge, and storing the electric charge converted in the photoelectric conversion region. And the first substrate formed on a part of the semiconductor substrate.
A charge accumulation region of a second conductivity type, which is formed on at least a part of a surface of the photoelectric conversion region and has a concentration that does not deplete an interface of the semiconductor substrate and a second conductivity type different from the first conductivity type. A plurality of unit cells each including a two-conductivity type region, voltage output means for outputting a voltage corresponding to the charge stored in the charge storage region, and charge discharging means for discharging the charge stored in the charge storage region are provided. In the method for driving a MOS solid-state imaging device, the charge storage region is set to a first potential to store a part of the charge converted in the photoelectric conversion region in the charge storage region, and the voltage output Means for outputting a voltage corresponding to the charge stored in the charge storage region, and setting the charge storage region to a second potential higher than the first potential to reduce the charge remaining in the photoelectric conversion region. Accumulated in the load storage region, characterized by discharging the charges accumulated in the charge storage region by said charge drain means.

According to a third aspect of the present invention, in the MOS type solid-state imaging device having a plurality of unit cells formed on a semiconductor substrate, the unit cells include a photoelectric conversion unit for converting light into a charge, and a photoelectric conversion unit. And an addressing means for transferring the charge converted by the photoelectric conversion means to the charge holding means by a punch-through effect.

Further, the fourth invention is a photoelectric conversion device for converting light into electric charge, a charge holding device for holding the electric charge transferred from the photoelectric conversion device, and a charge conversion device for converting the electric charge converted by the photoelectric conversion device. Addressing means for transferring to the charge holding means by a punch-through effect, voltage output means for outputting a voltage corresponding to the charge transferred to the charge holding means by the addressing means, and charge held by the charge holding means In a MOS-type solid-state imaging device including a plurality of unit cells each including a reset unit for resetting, the reset unit resets a charge held in the charge holding unit, and converts the charge by the photoelectric conversion unit by the address unit. Transferred to the charge holding means by a punch-through effect, and held in the charge holding means by the voltage output means. And outputs a voltage corresponding to the charges.

According to a fifth aspect of the present invention, in the MOS type solid-state imaging device having a plurality of unit cells, the unit cells are a photoelectric conversion means for converting light into electric charges, and a charge transferred from the photoelectric conversion means. When the charge converted by the photoelectric conversion means is equal to or less than a predetermined charge amount, all of the charges converted by the photoelectric conversion means are transferred to the charge holding means, When the charge converted by the photoelectric conversion unit is equal to or more than a predetermined charge amount, a transfer gate that transfers a part of the charge converted by the photoelectric conversion unit to the charge holding unit,
Voltage output means for outputting a voltage corresponding to the charge transferred to the charge holding means.

Next, the operation of each invention will be described. According to a first aspect of the present invention, an interface of a semiconductor substrate is depleted in at least a part of a photoelectric conversion region that converts light into charges and a first conductivity type charge detection region that stores charges converted by the photoelectric conversion region. A second concentration different from the first conductivity type at a concentration that does not
Is formed, the potential of the photoelectric conversion region can be lowered, and all or most of the remaining charge at the time of resetting is accumulated in the detection unit. As a result, the capacitance of the photodiode is substantially reduced, and the thermal noise generated at the time of resetting can be reduced.

According to a second aspect of the present invention, first, the charge storage region is set to the first position.
A part of the electric charge converted in the photoelectric conversion region is accumulated in the electric charge accumulation region by setting the electric potential to the potential, and a voltage corresponding to the electric charge accumulated in the electric charge accumulation region is output by the voltage output means.

Next, the charge remaining in the photoelectric conversion region is stored in the charge storage region by setting the charge storage region to the second potential higher than the first potential, and the charge discharging device stores the charge in the charge storage region. Drain the accumulated charge. As a result, the capacitance of the photodiode is substantially reduced, and the thermal noise generated at the time of resetting can be reduced.

According to the third aspect of the present invention, since the address means transfers the charge converted by the photoelectric conversion means to the charge holding means by a punch-through effect, there is no need to provide a transfer gate. As a result, the unit cell can be miniaturized. Can be realized.

According to the fourth aspect of the invention, first, the electric charge held in the electric charge holding means is reset by the reset means. next,
The charge converted by the photoelectric conversion means by the address means is transferred to the charge holding means by a punch-through effect, and the voltage output means outputs a voltage corresponding to the charge held by the charge holding means. To the charge holding means.

According to a fifth aspect of the present invention, when the charge converted by the photoelectric conversion means is equal to or less than a predetermined charge amount by the transfer gate, all of the charge converted by the photoelectric conversion means is transferred to the charge holding means. When the charge converted by the photoelectric conversion means is equal to or more than a predetermined charge amount, a part of the charge converted by the photoelectric conversion means is transferred to the charge holding means, and the voltage output means transfers the charge to the charge holding means. Since a voltage corresponding to the transferred charges is output, the dynamic range of the MOS solid-state imaging device can be expanded.

[0053]

Embodiments of the present invention will be described below with reference to the drawings. <First Embodiment> FIG. 1 is a diagram showing a layout of a unit cell of a MOS type solid-state imaging device according to a first embodiment of the present invention, and FIG. 2 is a diagram showing the first embodiment. FIG. 3 is a cross-sectional view showing a cross section of a unit cell of the MOS solid-state imaging device in FIG. 20 and FIG. 21 will be described with the same reference numerals.

In the figure, reference numeral 31 denotes an amplification gate which is a control electrode of an amplification transistor; 32, a reset gate;
Reference numeral 3 denotes a detection unit, reference numeral 34 denotes a photodiode serving as a photoelectric conversion unit, reference numeral 35 denotes an electrode connecting the amplification gate and the detection unit, and reference numeral 36 denotes a reset drain.

Reference numeral 37 denotes a p-type substrate; 38, an n-type diffusion layer forming a photodiode; 39, an n-type diffusion layer forming a detecting portion; and 40, an address gate. In the unit cell of the MOS solid-state imaging device according to the present embodiment, a p-type diffusion region 81 is provided on the entire surface of an n-type diffusion layer 38 forming a photodiode. The concentration of this p-type diffusion region is n
It is higher than the concentration of the mold diffusion region, and its potential is fixed to a reference potential (earth potential). Further, the concentration of the p-type diffusion region 81 is such that the interface of the semiconductor substrate is not depleted.

Therefore, a portion of the n-type region where the p-type region is formed on the substrate surface is depleted. As a result, the reset potential can be set higher than the depletion potential.

FIG. 3 is a diagram showing the potential distribution along the line AA 'in FIG. FIG. 3 shows that signal charges are accumulated in the photodiode 34 when t = 1. Also, in the state of t = 2, the state at the time of reset is shown.

At this time, the depletion potential of the n-type diffusion layer 38 forming the photodiode 34 is made lower than the reset potential by the p-type diffusion region 81 formed on the surface of the photodiode 34. Has no residual charge, and most of the charge is stored in the detection unit 39.
As a result, the capacitance of the photodiode 34 can be neglected, and the thermal noise is significantly reduced. In the state of t = 3, the state after reset is shown.

FIG. 4 is a diagram showing another layout of the unit cell. As shown in the drawing, the difference from the unit cell shown in FIG. 1 is that a p-type diffusion region 81 is formed in a part of the photodiode 34. FIG. 5 is a sectional view taken along line A- in FIG.
It is a figure which shows the electric potential distribution at the time of reset of A '.

As shown in the drawing, in the unit cell having such a configuration, the photodiode 3
Only a part of the potential of 4 becomes high, and the electric charge is accumulated in the portion where this potential is high and in the detection unit. Even in the unit cell having such a configuration, the capacity of the photodiode can be reduced, so that it is possible to prevent deterioration in image quality of a reproduced screen caused by thermal noise.

FIG. 6 is a diagram showing a layout of another unit cell. As shown in the figure, the difference from the unit cell shown in FIG. 1 is that a p-type diffusion region 81 is formed on the entire substrate surface of the photodiode 34 and a part of the substrate surface of the detection unit. FIG. 7 is a diagram showing a potential distribution at the time of resetting of the arrow line AA 'in FIG.

As shown in the figure, in the unit cell having such a configuration, at the time of resetting, only a part of the potential of the detecting section becomes high, and electric charges are accumulated in this detecting section. Even in the unit cell having such a configuration, the capacity of the photodiode can be neglected, so that it is possible to prevent the deterioration of the image quality of the reproduced screen caused by the thermal noise.

FIG. 8 is a diagram showing a layout of another unit cell. FIG. 9 is a diagram showing a potential distribution at the time of reset of the arrow line AA 'in FIG. As shown in FIGS. 8 and 9,
The difference from the unit cell shown in FIG.
A photodiode 34 is arranged between the detection unit 35 and
The p-type diffusion region 81 is formed on the surface of the photodiode.

In FIG. 9, during the signal charge accumulation period (t
= 1) and the potential at the time of reset (t = 2). Even in the unit cell having such a configuration, the capacity of the photodiode can be neglected, so that it is possible to prevent the deterioration of the image quality of the reproduced screen caused by the thermal noise.

FIG. 10 is a diagram showing a circuit configuration of such a unit cell. As shown in FIG.
A photodiode 94 having a p-type diffusion layer formed on the surface of the n-type diffusion region, an amplification transistor 93 for amplifying a detection signal of the photodiode 94, an address capacitor 95 for selecting a line from which a signal is read, and a detection unit 93 The reset transistor 96 resets signal charges.

In the figure, only one unit cell is shown, but actually more unit cells are arranged two-dimensionally. Next, regarding the operation of the unit cell having the photodiode 94 in which the p-type diffusion layer is formed on the surface of the n-type diffusion region forming such a photodiode, the timing chart of FIG. 11 and the potential distribution diagram of FIG. Reference and description will be given.

First, in FIG. 11, at t = 1, as shown in FIG.
Signal charges are stored in the memory. Next, when an address pulse having a first potential is applied to the address line 97 from the vertical shift register, a part of the electric charge accumulated in the photodiode 94 is applied to the detection unit as shown in FIG. The voltage corresponding to the stored charge (t = 2) and the charge stored in the detection unit 93 is applied to the signal line 9 via the amplification transistor 92.
1 is output.

Next, a second potential higher than the first potential is applied to the address line 97 and the photodiode 94
Is stored in the detection unit. Then, when a reset pulse is applied to the reset line 98 in a state where the second potential is applied to the address line 97, as shown in FIG. 12C, the charges accumulated in the detection unit are reset. It is discharged to the drain line via the transistor 96.

Therefore, according to the MOS type solid-state imaging device of the present embodiment, the p-type diffusion region 81 is formed on the entire surface of the n-type diffusion layer 38 forming the photodiode, so that the n-type diffusion layer 38 is formed. Can be lowered, all or most of the charge remaining at the time of resetting is accumulated in the detection unit, and as a result, the capacitance of the photodiode is substantially reduced, and the thermal noise generated at the time of resetting is reduced. be able to.

Further, since the p-type diffusion layer has such a concentration that the semiconductor substrate is not depleted, the dark current generated at the substrate interface is suppressed, and the S / N ratio is improved. Further, by forming the p-type diffusion region 81 on the entire surface of the n-type diffusion layer 38 forming the photodiode, the charge remaining in the photodiode at the time of signal reading and resetting is small, and as a result, the signal straight line Is guaranteed.

In the above description of the operation, the case where the p-type diffusion region is formed in all of the n-type diffusion regions forming the photodiode has been described. However, as shown in FIG. In the case where a p-type diffusion region is formed in a part of the photodiode, and as shown in FIG.
As shown in FIG. 8, it is needless to say that a similar effect can be obtained also when a photodiode is arranged between the reset gate and the detection unit and a p-type diffusion region 81 is formed on the surface of the photodiode. Nor. <Second Embodiment> Next, a MOS type solid-state imaging device according to a second embodiment of the present invention will be described.

FIGS. 13 (a) and 13 (b) are cross-sectional views of a photodiode and a detector of a unit cell of the MOS solid-state imaging device according to the present embodiment. In the figure, 101 is an n-type diffusion layer forming a photodiode,
Reference numeral 102 denotes a p-type diffusion region formed on the entire surface of the photodiode 101; 103, an n-type diffusion layer forming a detection unit; 104, a p-type substrate; 105, a signal stored in the photodiode 101; Address capacity for

Although the photodiode is floating, it has a BPD structure in which a p-type diffusion region is formed on the surface of the photodiode 101, so that the interface becomes zero.
Fixed to [v].

In the MOS-type solid-state imaging device according to the present embodiment, the photodiode 101 and the detection unit 103 correspond to a short-channel MOS-type transistor.
That is, the photodiode 101 corresponds to the source,
The detecting unit 103 corresponds to the drain. At this time,
The area between the photodiode 101 and the detection unit 103 corresponds to the transfer gate 106. This transfer gate 10
6, a predetermined bias voltage is applied, but the magnitude of the bias voltage is not a voltage large enough to transfer the charges accumulated in the photodiode 101 to the detection unit 103.

FIG. 13A is a cross-sectional view of a semiconductor substrate showing a case where a small voltage is applied to the address capacitor 105, and FIG. 13B is a diagram showing a case where a large voltage is applied to the address capacitor 105. It is sectional drawing of the semiconductor substrate which shows a situation.

FIG. 14 shows the photodiode 101 and the photodiode 101 when such a voltage is applied to the address capacitor 105.
FIG. 3 is a diagram illustrating a potential distribution of a detection unit 103. FIG. 13 (a)
As shown in FIG. 14, when the voltage applied to the address capacitor 105 is small, the electric charge accumulated in the photodiode does not reach the detection unit 103.

However, as shown in FIGS. 13B and 14, when the voltage applied to the address capacitor 105 is large, the depletion layer below the detection unit 103 (corresponding to the drain) is formed by the two-dimensional effect. It reaches the 101 end (source end). At this time, the potential barrier at the end of the photodiode 101 is modulated by the drain voltage, and the height of the barrier decreases. This is called the drain organic barrier lowering phenomenon (DIBI; Drain-Induced Barrier lower).
ing).

The signal charge of the photodiode 101 is completely transferred to the detection unit 103 due to the drain organic barrier lowering phenomenon. That is, in the unit cell of the MOS type solid-state imaging device according to the present embodiment, by applying a large voltage to the address capacitance, the photodiode 101
The signal charge is transferred from the (source) to the detection unit (drain) by a punch-through effect.

The operation of discharging the electric charge accumulated in the detecting section to the drain line via the reset transistor and the operation of outputting the electric charge accumulated in the detecting section to the signal line via the amplifying transistor are described above. The operation is the same as that described in the first embodiment.

In the above description, the gate 10
Although the case where a predetermined bias voltage is applied to 6 has been described, the gate 106 may be omitted. Therefore, according to the MOS-type solid-state imaging device of the present embodiment, the charge accumulated in the photodiode 101 is transferred to the detection unit 103 by the punch-through effect, so that there is no need to provide a transfer gate. The miniaturization of the unit cell can be realized without reducing the rate. <Third Embodiment> Next, a MOS type solid-state imaging device according to a third embodiment of the present invention will be described. The unit cell of the MOS type solid-state imaging device according to the present embodiment has a configuration including a transfer transistor as shown in FIG.

FIGS. 15A and 15B show a photodiode (PD), a transfer gate (TG), a detector, and a reset gate (RS) of a unit cell of the MOS solid-state imaging device according to the present embodiment. FIG. 4 is a potential distribution diagram of a reset drain (RD).

FIG. 15A shows the potential distribution when signal charges of low illuminance are accumulated, and FIG. 15B shows the potential distribution after the transfer gate is turned on. As shown in FIG. 15B, in the case of low illuminance, the signal charge is completely transferred to the detection unit. Here, assuming that the capacitance of the photodiode is Cp and the capacitance of the detection unit (including the transfer gate capacitance) is Cd, the charge-voltage conversion is performed at Cd at low illuminance.

The voltage Ssmal of the light-generated signal charge Qsmall
The conversion to l is performed by Ssmall = Qsm by the detection unit capacitance Cd.
all / Cd. FIG. 16A shows a potential distribution when a high-luminance signal charge is accumulated.
(B) is a diagram showing a potential distribution after the transfer gate is turned on.

In this state, since a large amount of signal charges are accumulated, during the transfer of the signal charges from the photodiode to the detection unit, the potential of the detection unit and the potential of the photodiode are in an equilibrium state. No more signal charges can be transferred to the detector.

That is, the signal is compressed by an amount corresponding to the signal charge remaining in the photodiode. The compression ratio is determined by the photodiode capacitance Cp and the detection unit capacitance Cd.
If the capacitance when C and C are connected in parallel is C (= Cp + Cd), a potential change represented by Q = CV is transmitted to the gate of the amplification transistor.

The signal charge remaining in the photodiode after transferring the high-brightness signal is injected into the photodiode from the drain via the detection unit after signal sampling, and is slice-reset by the transfer gate and the reset transistor. Is performed, the reset can be performed without leaving the residual charge in the photodiode.

FIG. 17 is a diagram showing the photoelectric conversion characteristics when such signal charges are transferred. As shown in the drawing, on the low illuminance side, charge-voltage conversion is performed by the detection unit capacitance Cd, and on the high luminance side, voltage conversion is performed by (Cp + Cd) by the sum of the photodiode capacitance Cp and the detection unit capacitance Cd. The signal is compressed on the high luminance side. Thereby, the dynamic range of the sensor can be expanded.

The switching point between high luminance and low illuminance (Knee
Point) is defined by the depletion potential of the photodiode, but can also be similarly defined by the reset gate voltage when resetting the detection unit.

Therefore, according to the MOS type solid-state imaging device of the present embodiment, the charge-voltage conversion is performed by the detection unit capacitance Cd on the low illuminance side, and the photodiode capacitance Cd on the high luminance side.
Since the voltage conversion is performed by (Cp + Cd) by the sum of p and the detection unit capacitance Cd, the dynamic range of the MOS solid-state imaging device can be expanded.

In the case of low illuminance, the charge of the photodiode is completely transferred to the detection unit, so that random noise does not occur. In the case of high luminance, the mode is set to the weak inversion mode at the end of the transfer of the signal charge from the photodiode to the detection unit, and random noise is generated due to channel noise. There is no problem with luminance.

[0091]

As described above in detail, according to the present invention,
It is possible to prevent the deterioration of the image quality of the reproduced screen caused by the noise due to the leak current. Further, according to the present invention, miniaturization of a unit cell can be realized without reducing the aperture ratio. Furthermore, according to the present invention, miniaturization of a unit cell can be realized without lowering the dynamic range.

[Brief description of the drawings]

FIG. 1 is a diagram showing a layout of a unit cell of a MOS solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a section of a unit cell of the MOS type solid-state imaging device according to the first embodiment;

FIG. 3 is a diagram showing a potential distribution of a unit cell of the MOS solid-state imaging device according to the first embodiment;

FIG. 4 is a diagram showing another layout of the unit cell of the MOS solid-state imaging device according to the first embodiment;

FIG. 5 is a diagram showing a potential distribution of a unit cell of the MOS solid-state imaging device according to the first embodiment.

FIG. 6 is a diagram showing another layout of the unit cell of the MOS solid-state imaging device according to the first embodiment;

FIG. 7 is a diagram showing a potential distribution of a unit cell of the MOS solid-state imaging device according to the first embodiment.

FIG. 8 is a diagram showing another layout of the unit cell of the MOS solid-state imaging device according to the first embodiment.

FIG. 9 is a diagram showing a potential distribution of a unit cell of the MOS solid-state imaging device according to the first embodiment.

FIG. 10 is a diagram showing a circuit configuration of a unit cell of the MOS solid-state imaging device according to the first embodiment.

FIG. 11 is a timing chart for explaining an operation of a unit cell of the MOS solid-state imaging device according to the first embodiment.

FIG. 12 is a diagram showing a potential distribution of a unit cell of the MOS solid-state imaging device according to the first embodiment.

FIG. 13 is a sectional view of a unit cell of a MOS solid-state imaging device according to a second embodiment of the present invention.

FIG. 14 is a diagram showing a potential distribution of a unit cell of the MOS solid-state imaging device according to the second embodiment.

FIG. 15 is a diagram showing a potential distribution of a unit cell of a MOS solid-state imaging device according to a third embodiment of the present invention.

FIG. 16 is a diagram showing a potential distribution of a unit cell of the MOS solid-state imaging device according to the third embodiment.

FIG. 17 is a diagram illustrating a photoelectric conversion characteristic of the MOS solid-state imaging device according to the third embodiment.

FIG. 18 is a diagram illustrating a circuit configuration of a conventional MOS-type solid-state imaging device.

FIG. 19 is a timing chart showing the operation of a conventional MOS solid-state imaging device.

FIG. 20 is a diagram showing a planar structure of a unit cell of a conventional MOS solid-state imaging device.

FIG. 21 is a diagram showing a cross-sectional structure of a unit cell of a conventional MOS solid-state imaging device.

FIG. 22 is a diagram showing a potential distribution of a conventional MOS solid-state imaging device.

FIG. 23 is a diagram showing a circuit configuration of a conventional MOS-type solid-state imaging device.

FIG. 24 is a timing chart showing the operation of a conventional MOS solid-state imaging device.

FIG. 25 is a diagram showing a detailed configuration of a unit cell of a conventional MOS solid-state imaging device.

[Explanation of symbols]

1-1-1, 1-1-2, ..., 1-2-2 ... photodiode, 2-1-1, 1-2-1, ..., 2-2-2 ... amplification transistor, 3-1 1, 3-1-2, ..., 3-2-2 ... vertical selection transistor 4-1-1, 4-1-2, ..., 4-2-2 ... reset transistor, 5 ... vertical shift register, 6 -1, 6-2: horizontal address line, 7-1, 7-2: reset line, 8-1, 8-2: vertical signal line, 9-1, 9-2: load transistor, 10-1, 10 -2: Signal capture transistor, 11-1, 11-2: Amplified signal storage capacity, 12-1, 12-2: Horizontal selection transistor, 13: Horizontal shift register, 14: Common gate of signal capture transistor, 15: Horizontal Signal lines, 21-1, 21-2 ... address pulses, 22-1, 22-2 ... Reset pulse, 23-1, 23-2 ... horizontal selection pulse, 24-1, 24-2 ... output signal, 31 ... amplification gate which is a control electrode of an amplification transistor, 32 ... reset gate, 33 ... detection unit, 34 ... Photodiodes, 35 electrodes, 36 reset drains, 37 p-type substrates, 39 n-type diffusion layers, 40 address gates, 41 transfer pulses, 42 address pulses, 43 reset pulses, 44 clamp pulses, 45: sample hold pulse, 46: horizontal selection pulse, 51: power supply line, 52: transfer signal line, 53: address capacity, 54: transfer transistor, 55: detector, 60: clamp capacity, 61: clamp transistor, 62 ... Sample-and-hold transistor, 63: sample-and-hold capacitance, 64: horizontal signal line, 65 ... Lamp node 66 Clamp power supply 67 Horizontal selection transistor 71 Overflow control gate 81 P-type diffusion region 91 Signal line 92 Amplification transistor 93 Detection unit 94 Photodiode 95 Address 96: reset transistor, 97: address line, 98: reset line, 101: n-type diffusion layer, 102: n-type diffusion layer, 103: n-type diffusion layer, 104: p-type substrate, 105: address capacitance, 106 ... Transfer gate.

Continuing from the front page (72) Inventor Keiji Mabuchi 1 Toshiba R & D Center, Komukai-ku, Kawasaki-shi, Kanagawa Prefecture (72) Inventor Ryohei Miyakawa 1 Kotomu-Toshiba-cho, Koyuki-ku, Kawasaki-shi, Kanagawa In the Toshiba R & D Center (72) Inventor Yoshinori Iida 1 in Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture In-Toshiba R & D Center

Claims (5)

[Claims] 1. A MOS-type solid-state imaging device in which a plurality of unit cells are formed on a semiconductor substrate, wherein the unit cells are formed on a part of the semiconductor substrate and convert first light into electric charges. Type photoelectric conversion region, formed on at least a part of the surface of the photoelectric conversion region,
A concentration of the first not depleting the interface of the semiconductor substrate;
And a second conductivity type region having a second conductivity type different from the first conductivity type. 2. A first conductivity type photoelectric conversion region formed on a part of a semiconductor substrate to convert light into electric charge; and storing the electric charge converted in the photoelectric conversion region; An upper part of the first conductivity type charge accumulation region, and at least a part of the surface of the photoelectric conversion region,
A concentration of the first not depleting the interface of the semiconductor substrate;
A second conductivity type region of a second conductivity type different from the conductivity type of: a voltage output unit that outputs a voltage corresponding to the charge stored in the charge storage region; In a method for driving a MOS solid-state imaging device including a plurality of unit cells each including a charge discharging unit for discharging, one of the charges converted in the photoelectric conversion region by setting the charge storage region to a first potential. Storing a portion in the charge storage region, outputting a voltage corresponding to the charge stored in the charge storage region by the voltage output unit, and setting the charge storage region to a second potential higher than the first potential The charge remaining in the photoelectric conversion region is stored in the charge storage region, and the charge discharging device discharges the charge stored in the charge storage region. Driving method. 3. A MOS-type solid-state imaging device in which a plurality of unit cells are formed on a semiconductor substrate, wherein the unit cell includes a photoelectric conversion unit that converts light into a charge, and a charge output from the photoelectric conversion unit. A MOS-type solid-state imaging device comprising: a charge holding means for holding; and an address means for transferring the charge converted by the photoelectric conversion means to the charge holding means by a punch-through effect. 4. A photoelectric conversion unit for converting light into charges, a charge holding unit for holding charges transferred from the photoelectric conversion unit, and a charge converted by the photoelectric conversion unit by a punch-through effect. Address means for transferring to the holding means, voltage output means for outputting a voltage corresponding to the charge transferred to the charge holding means by the address means, and reset means for resetting the charge held in the charge holding means. In a MOS type solid-state imaging device having a plurality of unit cells, the reset means resets the charge held in the charge holding means, and the address means converts the charge converted by the photoelectric conversion means into a punch-through effect. Corresponding to the charge held by the charge holding means by the voltage output means. MOS characterized by outputting that voltage
For driving a solid-state imaging device. 5. A MOS-type solid-state imaging device having a plurality of unit cells, wherein the unit cells are photoelectric conversion means for converting light into charges, and charge holding means for holding charges transferred from the photoelectric conversion means. When the charge converted by the photoelectric conversion unit is equal to or less than a predetermined charge amount, all of the charge converted by the photoelectric conversion unit is transferred to the charge holding unit, and converted by the photoelectric conversion unit. A transfer gate that transfers a part of the charge converted by the photoelectric conversion unit to the charge holding unit, when the charge transferred is equal to or more than the predetermined charge amount, and corresponds to the charge transferred to the charge holding unit. And a voltage output means for outputting a voltage to
S-type solid-state imaging device.