JPH1093917A - Picture processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To abolish unnecessary data before it is written into a decoding memory and to realize the fast-forward reproduction of a video without excessively reading/writing data by providing a header detection unit immediately after a stream decomposition unit and writing only necessary data in a data stream into the decoding memory. SOLUTION: The header detection unit 40 is provided immediately after the stream decomposition unit 10. The MPEG video stream outputted from the stream decomposition unit 10 is supplied to the header detection unit 40. The header detection unit 40 selects only the data stream to which a prescribed header is given and it is stored in a prescribed area in the VBV buffer 17-1 of the MPEG decoding memory 17. Thus, the speed of data writing/reading, which is required by the MPEG decoding memory 17, can be reduced since unnecessary data can be abolished before it is written into the MPEG decoding memory 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to an image processing apparatus, and for example, relates to an MPEG (Moving Picture Expert Group).
p) The present invention relates to an image processing device that performs moving image decoding using digital compression.

[0002]

2. Description of the Related Art FIG. 8 shows an example of a conventional image processing apparatus for receiving a MPEG stream and displaying a moving image on a display.
Shown in The image processing apparatus in FIG. 8 includes a stream decomposition unit 10 and an inverse variable length
code) unit 11, inverse quantization unit 12, inverse DCT
(Discrete Cosine Transform) unit 13, adder 14, prediction unit 15, memory controller 16, M
It includes a PEG decoding memory 17, an output circuit 18, a display 19, an MPEG audio decoder 20, and a speaker 21. Here, the variable length decoding unit 11
Is a header detection circuit 11-1 and a variable length inverse encoding circuit 1
1-2. Also, the MPEG decoding memory 17
VBV buffer 17-1, I / P picture buffer 1
7-2, a P picture buffer 17-3, a B picture buffer 17-4, and another buffer 17-5. Other buffers 17-5 include an audio buffer, a general digital information stream buffer, and the like.

[0003] The stream decomposing unit 10
The stream is received from a DVD (Digital Video Disc) or a hard disk of a personal computer. The MPEG stream contains MPEG compressed video information, MPEG compressed audio information, and general digital information including various programs and data used by the user in a time-division multiplexed manner. This is generally ISO (International
Standard Organization) It is defined by the international standard MPEG system stream standard. MPEG-compressed video information is represented by variable-length encoding in which frequently appearing numerical values are represented by short codes and rarely appearing numerical values are represented by long codes to reduce the number of bits in the entire numerical sequence. DCT for converting to a component, quantization for quantizing DCT coefficients with the number of bits according to the image content, and DPCM (Differenti) for compressing image information by transmitting a difference from a past image.
al Pulse Code Modulation)
It is compressed according to the G International Image Compression Standard.

[0004] The stream decomposing unit 10 converts the transmitted MPEG stream into an MPEG video stream,
Decompose into an MPEG audio stream and a general digital information stream. The MPEG video stream is transmitted to the VBV buffer 1 of the MPEG decoding memory 17 via the bus 30 and the memory controller 16.
7-1 is temporarily stored in a predetermined area. Also MP
The EG audio stream and the general digital information stream are stored in another buffer 17-5. Of the compressed information stored in the buffer 17-5, for example, audio information is read by the memory controller 16 and supplied to the MPEG audio decoder 20. The MPEG audio decoder 20 decodes the audio information, and the speaker 21 outputs the decoded audio information.

Hereinafter, processing of video information (image information) related to the present invention out of video information, audio information, and general digital information will be described in detail. MPE
The image information compressed according to G is represented by a different number of bits for each frame. That is, some frames are represented by a relatively small number of bits, and some frames are represented by a relatively large number of bits. Since image information having a different number of bits per frame is transmitted at a fixed bit rate (transmission speed), the image information received by the stream decomposition unit 10 has a different transmission time for each frame. The VBV buffer 17-1 is required to absorb the difference in transmission time for each frame. VBV
The buffer 17-1 converts the image information transmitted at a fixed bit rate (transmission speed) into a stream decomposition unit 1
0 and temporarily store the data, thereby absorbing the difference in transmission time for each frame. VBV buffer 1
Each frame of the image information stored in 7-1 is read out every display time of one frame on the display 19, and is subjected to subsequent decoding processing. VBV buffer 17-1
It is defined by international standards that the number of bits in the buffer is controlled within a range in which no overflow / underflow occurs, and the capacity of the VBV buffer 17-1 is also defined by international standards.

[0006] The image stored in the VBV buffer 17-1 is read out to the variable length decoding unit 11 via the memory controller 16 and the bus 30. The variable-length inverse encoding unit 11 inversely encodes the variable-length code into a fixed-length code to extract a motion vector, a quantized DCT coefficient, and the like.
The inverse quantization unit 12 receives the quantized DCT coefficients, inversely quantizes them, and outputs DCT coefficients. Inverse DCT
Unit 13 receives the DCT coefficients and converts them to the inverse DCT
Then, the image information in the frequency domain is returned to the image information in the spatial domain.

[0007] Encoding on the transmitting side and decoding (image restoration) on the receiving side are performed for each block by dividing one image into blocks of 16x16 pixels (called macroblocks). A motion vector between images is also determined for each block. In addition, the DCT on the transmitting side and the inverse DCT on the receiving side divide each block (macroblock) into 8 × 8 pixel blocks, and
This is performed for each block of 8 pixels.

In MPEG digital image compression, an I picture (In Picture) which has been predictively coded in the current frame is used.
tra Picture) and a P-picture (Predictive Picture) in which a motion vector of the current frame is obtained using a certain past frame as a reference image, and the current frame is subjected to predictive coding as a difference from the reference image based on the motion vector.
And the motion vector of the current frame is determined using both the future frame and the past frame as reference images, and the current frame is subjected to predictive encoding as a difference from the reference image based on the motion vector. Picture (Bidi
rectionally Predictive Picture). Here, the past reference picture is a past I picture or a past P picture, and the future reference picture is a future P picture. Actually, when encoding a B picture, a future P picture to be a future reference picture is first predictively encoded and transmitted.
Thereafter, the B picture is encoded and transmitted. On the decoding side, the current B picture is de-encoded using the past I picture or P picture and the previously transmitted future P picture. The prediction unit 15 performs decoding using such a motion vector.

When the currently decoded image is an I picture, the adder 14 passes the image information from the inverse DCT unit 13 without change. The I picture is stored in the I / P picture buffer 17-2 of the MPEG decoding memory 17 via the bus 30 and the memory controller 16. The I picture stored in the I / P picture buffer 17-2 is used in restoring a subsequent P picture or B picture. The I picture is supplied to the output circuit 18 via the bus 30 for image display.

If the currently decoded image is a P-picture, the current frame (P-picture) stored in the VBV buffer 17-1 is read into the variable-length inverse coding unit 11, and is decoded by the inverse quantization unit 12 and the inverse quantization unit 12. The signal is supplied to the adder 14 via the DCT unit 13. Each block of the current frame is a difference from the corresponding block of the past reference image. The past reference image (P picture or I picture) has already been decoded and stored in the I / P picture buffer 17-2 or the P picture buffer 17-3. The past reference image is supplied to the prediction unit 15 via the memory controller 16 and the bus 30. The prediction unit 15 is further supplied with the motion vector extracted in the variable length decoding unit 11. The prediction unit 15 supplies a corresponding portion of the past reference image corresponding to each block of the current frame to the adder 14 based on the supplied motion vector. As a result, each block of the current frame is added to the corresponding location of the past reference image, and a restored image of the current frame is obtained. The restored P picture is stored in the I / P picture buffer 17-2 or the P picture buffer 17-3. The stored P picture is used in the subsequent restoration of the P picture or B picture. In addition, this P picture is used for image display,
It is supplied to the output circuit 18 via the bus 30.

When the currently decoded image is a B picture, the current frame (B picture) stored in the VBV buffer 17-1 is read into the variable length decoding unit 11, and is decoded by the inverse quantization unit 12 and the inverse quantization unit 12. The signal is supplied to the adder 14 via the DCT unit 13. Each block of the current frame is a difference from the corresponding block of the past and future reference images. The past and future reference images (P picture or I picture) have already been decoded and stored in the I / P picture buffer 17-2 or the P picture buffer 17-3. The past and future reference images are supplied to the prediction unit 15 via the memory controller 16 and the bus 30. The prediction unit 15 is further supplied with the motion vector extracted in the variable length decoding unit 11. Prediction unit 15
Supplies the adder 14 with the past and future reference image portions corresponding to each block of the current frame based on the supplied motion vector. As a result, each block of the current frame is added to the corresponding image portion of the past and future reference images, and a restored image of the current frame is obtained. The restored B picture is supplied to the output circuit 18 via the bus 30 for image display. The B picture buffer 17-4 is used for storing an image being decoded.

The I picture, P picture, and B picture supplied to the output circuit 18 are supplied to the display 19 as video signals for display. The display 19 displays the supplied video signal on a screen. Generally, I-pictures are
It is transmitted once every 0.5 seconds (one frame every 15 frames). Although depending on the magnitude of the correlation between images in the time direction, the I-picture generally has the lowest compression ratio and the largest amount of information (number of bits) required for image representation. The B picture has the highest compression ratio and the smallest amount of information (the number of bits) required for image representation. The P picture has a higher compression rate than the I picture, and has a lower compression rate than the B picture.

The I / P / B picture can be identified by referring to the picture header and thereafter extracted by the variable length decoding unit 11 from the MPEG data stream. FIG. 9 shows a variable-length inverse coding unit 11.
3 is a diagram showing details of a header detection circuit 11-1 of FIG. FIG.
As shown in (1), the header detection circuit 11-1 includes a picture header storage register 31, a shift register 32, and a comparator 33. Generally, an MPEG stream is transmitted serially, so in the example of FIG. 9, it is assumed that the video stream supplied from the VBV buffer 17-1 is also serial. The shift register 32 converts the serial video stream into parallel data.
This serial-parallel conversion is not essential. Assuming that the video stream supplied from the VBV buffer 17-1 is parallel, a simple register may be used instead of the shift register 32.

The picture header storage register 31 stores an I / O
Picture header information for identifying a P / B picture is stored. The comparator 33 compares the data supplied from the shift register 32 with the picture header information stored in the picture header storage register 31 to determine whether the currently supplied picture is I / P / B. judge. The comparator 33 can be configured by using, for example, an XOR circuit or the like.

The MPEG video stream includes a sequence header code indicating a start point of data of each layer, a group start code, a picture start code, a slice start code, etc.
01xx ". Therefore, all start codes are
23 consecutive "0" s in binary number followed by "1". The video stream is coded so that the pattern of 23 consecutive "0s" followed by a "1" does not exist except for these start codes. Also, the type of start code is specified by “xx”, and in the case of a picture start code, xx =
00. Following this picture start code, I
A code indicating the picture type of / P / B is sent.
Therefore, the picture start code and the picture type can be considered together as a picture header, the start of the picture can be determined based on the bit pattern of the picture header, and the picture type can be identified. In the example of FIG. 9, the comparator 33 inputs an activation signal to the variable length decoding circuit 11-2 after identifying the picture header, and starts the decoding processing for the picture.

When fast-forwarding video is realized in the image processing apparatus shown in FIG. 8, fast-forward playback using only I-pictures or fast-forward playback using B-picture skipping is generally performed as processing of an MPEG stream supplied from a DVD or the like. It is a target. Playback of I picture only or B
The reason why picture skip reproduction is common is described below.

For example, an MPEG video decoder (variable-length inverse coding unit 11, inverse quantization unit 12, inverse DCT unit 13, adder 14, and prediction unit 15) all processes a video stream fast-forwarded at a speed of, for example, five times. For processing, five times the processing speed is required. Such a processing speed is difficult to realize in view of economic requirements. In addition, since it is impossible for the display 19 to display image information at five times speed, it is meaningless to process all MPEG video streams at five times speed.

In consideration of the display capability of the display 19, what is meaningful as fast-forward reproduction is that image frames are displayed intermittently. Therefore, the MPEG video decoder also has to process one frame for every five frames instead of processing at five times the speed. However, since the I picture is intra-coded,
Although it can be decoded even if given alone, it cannot be decoded if given alone because it is inter-coded for P-pictures or B-pictures. That is, the P picture depends on the past I picture or the past P picture, and the past P picture further depends on the past picture. Therefore, if the processing of a certain P picture is skipped once, the subsequent P picture processing becomes impossible. Similarly, B pictures that depend on past and future I / P pictures cannot be restored if the P picture processing is skipped.

Therefore, the first method of executing fast-forward playback is to play back only I pictures that can be restored alone. The second method is to skip a part or all of the B picture and reproduce the I picture and the P picture or a part of the B picture in addition to the I picture and the P picture.

[0020]

However, in the conventional image processing apparatus shown in FIG. 8, the picture type necessary for the above-mentioned two fast-forward reproduction processes is identified by the header detection circuit 11-1. . In this case, the header detection circuit 1 from the VBV buffer 17-1 via the bus 30
The video stream supplied to 1-1 is a stream including all pictures. In addition, the VBV buffer 17-1 from the stream decomposition unit 10 via the bus 30.
Is a stream including all pictures.

Therefore, in the case of fast-forward playback, the process of reading and writing a video stream to and from the MPEG decode memory 17 via the bus 30 requires a large amount of high-speed data transfer. Therefore, a great load is imposed on the data transfer capability of the bus 30, and the speed of the video stream may exceed the limit of the write / read access speed to the memory.

Accordingly, an object of the present invention is to provide an image processing apparatus which realizes fast-forward playback of a video without excessively reading / writing data from / to an MPEG decoding memory.

[0023]

According to a first aspect of the present invention, an image processing apparatus for decoding a video stream in a multiplexed data stream and displaying image information receives the data stream. A stream decomposing unit for extracting the video stream, receiving the video stream from the stream decomposing unit, detecting a predetermined header from the video stream, and selecting a predetermined header and data accompanying the predetermined header. A header detection unit that outputs the selected video stream, a memory that stores the selected video stream, and a video decoder that decodes the selected video stream stored in the memory.

In the above invention, by providing the header detection unit immediately after the stream decomposing unit,
Only necessary data in the data stream is written to the decoding memory. As a result, unnecessary data can be discarded before writing to the decoding memory, so that the data writing / reading speed required for the decoding memory can be reduced.

According to a second aspect of the present invention, in the image processing apparatus according to the first aspect, the data stream is supplied at a data rate faster than normal reproduction for fast-forward reproduction of the image information. It is characterized by. In the above-mentioned invention, in the fast-forward reproduction of an image, unnecessary data of the video stream is discarded before writing to the decoding memory, so that the data writing / reading speed required for the decoding memory at the time of fast-forward reproduction is performed. Can be reduced.

According to a third aspect of the present invention, in the image processing apparatus according to the second aspect, the header detection unit detects an I picture header as the predetermined header and discards a P picture and a B picture. And outputting the selected video stream consisting of only I pictures.

According to the above-mentioned invention, it is possible to perform fast-forward reproduction of an image using only I-pictures without excessively requesting the decoding memory for data writing / reading speed. According to a fourth aspect of the present invention, in the image processing apparatus according to the third aspect, the header detection unit includes an I picture header detector, a P picture header detector, a B picture header detector, A header code detector and a group start code detector, wherein when the P picture header and the B picture header are detected, the video is continued until one of the I picture header, the sequence header code and the group start code is detected next. The stream is discarded.

In the above-mentioned invention, by detecting each header of the video stream, fast-forwarding of an image using only I-pictures without excessively requesting the data write / read speed to the decoding memory. Playback becomes possible. In the invention of claim 5, claim 2
In the above image processing apparatus, the header detection unit detects an I picture header and a P picture header as the predetermined header, discards a part or all of the B picture, and discards the I picture, the P picture, and the B picture. Outputting the selected video stream composed of a part.

According to the above-mentioned invention, it is possible to perform fast-forward reproduction of an image using only I-pictures and P-pictures without excessively requesting the decoding memory for data writing / reading speed. According to a sixth aspect of the present invention, in the image processing apparatus according to the fifth aspect, the header detection unit includes an I picture header detector, a P picture header detector, a B picture header detector, and a sequencer. A header code detector and a group start code detector, wherein when a B picture header is detected, the I picture header, the P picture header, a sequence header code, and one of group start codes are detected until the B picture header is detected. The video stream is discarded.

In the above invention, by detecting each header of the video stream, only the I picture and the P picture are used without excessively requesting the data write / read speed for the decoding memory. Fast forward playback of images becomes possible.

According to the seventh aspect of the present invention,
3. The image processing apparatus according to claim 3, wherein the header detection unit detects at least one of a user data start code and an extension start code as the predetermined header, and detects at least one of the user data and the extension data. Outputting the one selected video stream.

In the above invention, at least one of the user data and the extension data of the video stream is selected and stored in the memory, so that the user data or the extension data can be handled separately from the other data. At the same time, the data write / read speed required for the decoding memory can be reduced.

According to an eighth aspect of the present invention, in the image processing apparatus according to the seventh aspect, the header detection unit includes an I picture header detector, a P picture header detector, and a B picture header detector. And a sequence header code detector, a group start code detector, and a user data start code detector. When the user data start code is detected, a header detected before that is an I picture header. Depending on which of the P picture header, the B picture header, the sequence header code, and the group start code, whether the detected user data start code is of the sequence layer, the group of picture layer, or the picture layer Is determined from the user data of a predetermined hierarchy. And outputs the selected video stream that.

In the above invention, by detecting each header of the video stream, the user data can be handled separately from other data, and the data writing / reading required for the decoding memory can be performed. Speed can be reduced.

[0035]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows an embodiment of the image processing apparatus according to the present invention. 1, the same components as those of FIG. 8 are referred to by the same numerals, and a detailed description thereof will be omitted. In the image processing apparatus according to the present invention, by providing the header detection unit immediately after the stream decomposing unit, only necessary data in the MPEG stream is written to the MPEG decoding memory.
As a result, unnecessary data can be discarded before writing to the MPEG decoding memory.
Data writing / reading speed required for the G decoding memory can be reduced.

The image processing apparatus shown in FIG. 1 comprises a stream decomposition unit 10, a header detection unit 40, a variable-length inverse encoding unit 11, an inverse quantization unit 12, an inverse DCT unit 13, an adder 14, a prediction unit 15, a memory controller 16, an MPEG decoding memory 17, an output circuit 18, a display 19, an MPEG audio decoder 20, and a speaker 21.

The stream decomposing unit 10 is adapted to transmit the MPEG transmitted from an MPEG stream generator such as a DVD.
Decompose the stream into an MPEG video stream, an MPEG audio stream, and a general digital information stream. The MPEG audio stream and the general digital information stream output from the stream disassembling unit 10 are transmitted via the bus 30 and the memory controller 16 to predetermined streams in the VBV buffer 17-1 of the MPEG decoding memory 17 and other buffers 17-5. Temporarily stored in the area. This VBV buffer 17-1
Out of the compressed information stored in the buffer 17-5 and other information, for example, the audio information is stored in the memory controller 1
6 and supplied to the MPEG audio decoder 20. The MPEG audio decoder 20 decodes the audio information, and the speaker 21 outputs the decoded audio information.

The MPEG video stream output from the stream decomposing unit 10 is
0 is supplied. The header detection unit 40 selects only the data stream with a predetermined header,
The data is stored in a predetermined area in the VBV buffer 17-1 of the G decoding memory 17.

Fast forward reproduction by selecting only I pictures is realized as follows. Header detection unit 4
0 receives the MPEG video stream corresponding to the fast forward speed from the stream decomposition unit 10. From the supplied MPEG video stream, the header detection unit 40 detects a sequence header code, a group start code, and a picture header.

FIG. 2 schematically shows the outline of an MPEG video stream. Although the actual MPEG video stream is defined in more detail, for the sake of explanation, only the parts relevant to the present invention are simplified and shown in FIG. As shown in FIG. 2, an MPEG video stream starts with a sequence header code, and a region following the sequence header code includes various parameters that define an image sequence in a long time unit. Examples of these parameters include the number of vertical lines of an image, the number of horizontal pixels, the aspect ratio, the size of a VBV buffer, and the like. Following these parameters, a user data start code indicating the start of user data that can be freely used by the user and user data are transmitted in the sequence hierarchy.

Subsequently, a time unit of about 0.5 second (1
A group start code indicating the start of a group of pictures (group of pictures: GOP) of about 0 to 20 frames is transmitted. The area following the group start code contains various parameters defined for the group of pictures. For example, a parameter indicating the time from the beginning of the sequence is included. Following these parameters, a user data start code indicating the start of user data that can be freely used by the user and user data are transmitted in the group of pictures hierarchy.

Subsequently, a picture start code indicating the start of one frame or one field is transmitted. The area following the picture start code contains various parameters defined for the picture. Examples of these parameters include a parameter indicating the accuracy of the motion vector, a picture coding type indicating the I / P / B picture type, and the like. Here, the picture start code and the subsequent picture coding type are collectively called a picture head.
Following these parameters, in the picture hierarchy:
A user data start code indicating the start of user data that can be freely used by the user and user data are transmitted.

Subsequently, the image data divided by the slice start code is transmitted. Referring again to FIG. 1, when detecting the sequence header code or the group start code, the header detection unit 40 detects the picture header while storing the subsequent MPEG stream in the VBV buffer 17-1. If the detected picture header is an I-picture header, the subsequent MPEG stream is stored in the VBV buffer 17-1. If the detected picture header is a P picture header or a B picture header, the MP
The EG stream is discarded until the next sequence header code, group start code, or picture header comes. As a result, of the I / P / B pictures, only the I picture is stored in a predetermined area in the VBV buffer 17-1 of the MPEG decoding memory 17.
The I picture stored in the VBV buffer 17-1 is
The data is read out to the variable length decoding unit 11 via the memory controller 16 and the bus 30. The variable-length inverse encoding unit 11 performs inverse encoding, converts the variable-length code into a fixed-length code, and extracts quantized DCT coefficients and the like.

The inverse quantization unit 12 receives the quantized DCT coefficients, inversely quantizes them, and outputs DCT coefficients. The inverse DCT unit 13 receives the DCT coefficient, performs inverse DCT on the DCT coefficient, and returns image information in the frequency domain to image information in the spatial domain. In this case, since the processing target is an I picture, a prediction unit 1 that performs processing for inter-picture prediction
5 does not work. The adder 14 passes the image information of the spatial region supplied from the inverse DCT unit 13 as it is. The image information of this space area is once supplied to an output circuit 18 via a memory 17 for MPEG decoding. The output circuit 18 outputs a fast-forward video signal, which is displayed on the display 19 as a fast-forward image.

As described above, by providing the header detection unit 40 immediately after the stream decomposing unit 10, only the necessary data in the MPEG stream can be transmitted to the MP stream.
Writing to the EG decoding memory 17 is performed. This makes it possible to discard unnecessary data before writing to the MPEG decoding memory 17.
Data writing required for the G decoding memory 17 /
The reading speed can be reduced. Note that only the I picture is selected and the MPEG decoding memory 17 is selected.
In the header detection unit 40, only the I picture and the P picture, or the I picture, the P picture and a part of the B picture are selected (that is, the B picture is skipped or the B picture is partially (Skip) and writing to the MPEG decoding memory 17. Further, the header detection unit 40 may include a circuit that identifies a user data start code and selects user data for each layer.

FIG. 3 shows a circuit example of the first embodiment of the header detection unit 40 for selecting only I pictures. The header detection unit 40 of FIG.
Octal counter 42, comparator 43, delay circuit 44, registers 45 and 46, sequence header comparator 47, GOP
Header comparator 48, I picture header comparator 49, P
Picture header comparator 50, B picture header comparator 51, RS flip-flop 52, AND circuit 53,
It includes a FIFO memory 54, an up / down counter 55, a comparator 56, and a memory interface circuit 57.
FIG. 4 shows a time chart of the header detection unit 40 of FIG. Hereinafter, the operation of the header detection unit 40 of FIG. 3 will be described with reference to FIGS.

The MPEG video stream supplied from the stream decomposition unit 40 is stored in the delay circuit 44 and the register 46. The register 46 stores data of 48 bits, and the 48 bits correspond to the length of each header (start code). Actually, the picture start code and the picture type shown in FIG. 2 are represented by a bit string of 48 bits or less in total. However, since the MPEG video stream is supplied in units of 8 bits, the register 46 has a 48-bit length so as to be divided in units of 8 bits.

As shown in FIG. 4, the MPEG video stream input to the delay circuit 44 is output after being delayed by 48 clocks. 48 stored in the register 46
The bit data is sent to the sequence header comparator 47, GO
P header comparator 48, I picture header comparator 49,
It is supplied to the P picture header comparator 50 and the B picture header comparator 51, and is compared with each header (start code). Each of the comparators 47 to 51 has a register 4
When the 48-bit data stored in No. 6 matches the corresponding header pattern, a HIGH signal is output.
Sequence header comparator 47, GOP header comparator 4
8 and the output of the I picture header comparator 49 are supplied to the set input of the flip-flop 52, and the P picture header comparator 50 and the B picture header comparator 51
Is supplied to the reset input of the flip-flop 52.

It takes 48 clocks to store 48-bit data in the register 46. Therefore,
The I picture head of the MPEG video stream is detected and the output of the I picture header comparator 49 is HIGH.
Becomes 48 clocks after the beginning of the I picture header of the MPEG video stream. Therefore, as shown in FIG. 4, the head of the I picture header delayed by 48 clocks by the delay circuit 44 and the output of the I picture header comparator 48 temporally match. The output of the flip-flop 52 changes so as to match the head of the I picture header delayed by the delay circuit 44. In this case, since an I-picture header has been detected, its output becomes HIGH.

Delayed M output from delay circuit 44
The PEG video stream is serial data, which is stored in an 8-bit register 45 and is converted from serial to parallel into 8-bit parallel data. The MPEG video stream converted into 8-bit parallel data is written to the FIFO memory 54. On this occasion,
Until data of 8 bits accumulates in the register 45, data cannot be written from the register 45 to the FIFO memory 54. Therefore, the comparator 43 and the AND circuit 53 are used to control the timing.

The outputs a to e of the comparators 47 to 51 are supplied to an OR circuit 41, and reset the octal counter 42 at the timing when any of the headers is detected. The reset octal counter 42 counts the number of clock pulses from 0, and supplies the counting result to the comparator 43. The comparator 43 compares the fixed input “7” with the count result,
When both are the same, a HIGH signal is output. That is, as shown in FIG. 4, when the count result of the octal counter 42 is 7, the output of the comparator 43 becomes HIGH. This comparator 4
The output of 3 becomes HIGH at the timing when the 8-bit data is stored in the register 45 and the 8-bit parallel data can be read.

The output of the comparator 43 is applied to one input of an AND circuit 53, and the output of the flip-flop 52 is applied to the other input of the AND circuit 53. Therefore, when a sequence header, a GOP header (group start code), or an I picture header is detected, the AND circuit 53 outputs a HIGH signal at a timing at which the octal counter counts seven. This AND circuit 53
Is applied to a write input of the FIFO memory 54. Therefore, as shown in FIG. 4, the write input of the FIFO memory 54 is given at the timing when 8-bit parallel data can be read from the register 45.

Thus, the 8-bit data serial-parallel converted by the register 45 is written to the FIFO memory 54. The output of the AND circuit 53 is
It is provided to the up-count input of the up-down counter 55. That is, each time 8-bit data is written to the FIFO memory 54 once, the count value output of the up / down counter 55 increases by one. This is shown in FIG. The comparator 56 receives the count value output of the up / down counter 55 and the fixed value “0”, compares them, and
When the count value is 0 or more, a HIGH signal is output.

When the HIGH signal is supplied from the comparator 56, the memory interface circuit 57 supplies a read request signal to the FIFO memory 54 and reads out 8-bit data from the FIFO memory 54. The read request signal from the memory interface circuit 57 to the FIFO memory 54 is also supplied to a down count input of the up / down counter 55. Therefore, each time the memory interface circuit 57 reads out the 8-bit data from the FIFO memory 54 once, the count value of the up / down counter 55 decreases by one. That is, the up-down counter 55
Indicates the number of 8-bit data stored in the FIFO memory 54. In this way, the interface circuit 57
As long as the data is stored in, the data is continuously read. The data read by the memory interface circuit 57 is stored in the VBV of the MPEG decoding memory 17 shown in FIG.
It is stored in the buffer 17-1.

As shown in FIG. 4, when the next picture header is a P picture header, the output of the P picture header comparator 50 becomes HIGH, the flip-flop 52 is reset and its output becomes LOW. Therefore, the data after the P picture header is not written in the FIFO memory 54 until the next sequence header, GOP header or I picture header comes.

As described above, only the I picture can be selected and stored in a predetermined area of the MPEG decoding memory 17. Therefore, when performing fast-forward playback, only I pictures can be played back without requiring excessive writing / reading to the MPEG decoding memory 17.

FIG. 5 shows a circuit example of a second embodiment of the header detection unit 40 for selecting only I / P pictures. The header detection unit 40 shown in FIG.
1, octal counter 42, comparator 43, delay circuit 44, registers 45 and 46, sequence header comparator 47, G
OP header comparator 48, I picture header comparator 4
9, P picture header comparator 50, B picture header comparator 51, RS flip-flop 52A, AND circuit 53, FIFO memory 54, up / down counter 5
5, comparator 56, and memory interface circuit 57
including. The header detection unit 40 in FIG. 5 is the same as the header detection unit in FIG. 3 except for the RS flip-flop 52A.

That is, in the header detection unit 40 for selecting an I / P picture and skipping a B picture,
The RS flip-flop 52A includes a sequence header G
The flip-flop 52A is set when an OP header, an I-picture header, or a P-picture header comes, and the flip-flop 52A is reset only when a B-picture header comes. In this way, only the I and P pictures are selected and the MPEG decoding memory 1 is selected.
7 can be stored in a predetermined area. Therefore, when performing fast-forward playback, there is no need to request the MPEG decoding memory 17 for excessive writing / reading.
Only I and P pictures can be reproduced.

FIG. 6 shows a circuit example of a third embodiment of the header detection unit 40 for selecting user data.
6 includes an OR circuit 41, an octal counter 42, a comparator 43, a delay circuit 44, a register 4
5 and 46, a sequence header comparator 47, a GOP header comparator 48, an I picture header comparator 49, a P picture header comparator 50, and a B picture header comparator 5.
1, RS flip-flop 52A, AND circuit 53A,
It includes a FIFO memory 54, an up / down counter 55, a comparator 56, and a memory interface circuit 57. The above elements are the header detection unit shown in FIG.
Identical except for 3A. The AND circuit 53A is a three-input AND circuit that receives inputs from the added circuit part in addition to the two inputs in FIG. The header detection unit 40 of FIG. 6 further includes a user header comparator 60 as an additional part for identifying user data.
, RS flip-flops 61 and 62, an AND circuit 63, an inverter 64, and a FIFO circuit 71.
The FIFO circuit 71 has the same configuration as the FIFO circuit 70 including the FIFO memory 54, the up / down counter 55, and the comparator 56.

The header detection unit 40 shown in FIG. 6 detects a sequence header user header (user data start code) in the MPEG video stream shown in FIG. 2 and converts the sequence hierarchy user data to other data. Are supplied to the memory interface circuit 57 separately. By adopting such a configuration, FIG.
VBV buffer 17 of MPEG decoding memory 17
Within -1, the user data of the sequence hierarchy can be stored in a dedicated area different from other data.

In the header detection unit 40 shown in FIG. 6, the user header comparing section 60
It detects whether the 8-bit data matches the bit pattern of the user data start code. If they match, a HIGH signal is output and flip-flop 6
Set 2 This flip-flop 62 is reset when the next header comes. Therefore, flip-flop 6
The output of 2 becomes HIGH only during the period of the user header and the following user data.

In the MPEG video stream, the user data start code (user header) has the same bit pattern regardless of the sequence layer, GOP (group of data) layer, and picture layer. Therefore, if only the user header comparator 60 is used, it is not possible to know which layer the detected user header and the following user data belong to.

The flip-flop 61 is for identifying to which layer the user header detected by the user header comparator 60 belongs. Flip-flop 61
, The output (a) of the sequence header comparator 47 is given, and the reset input is a GOP header comparator 48, an I picture header comparator 49, a P picture header comparator 50, and a B picture header comparator 51.
(B to e) are provided. Therefore, the flip-flop 61 supplies a HIGH signal as an output only when the current layer is the sequence layer.

Therefore, by performing an AND operation between the output of the flip-flop 61 and the output of the flip-flop 62, the user header of the sequence layer can be detected. That is, the AND circuit 63 that receives the output of the flip-flop 61 and the output of the flip-flop 62 outputs the output to H only when the user header of the sequence layer arrives.
Set to IGH.

The FIFO circuit 71 receives a signal indicating the detection of the user header in the sequence layer as a write signal write, and stores the 8-bit parallel data stored in the register 45. The FIFO circuit 71 reads the user data of the sequence layer one after another, and continues to supply the write request signal to the memory interface circuit 57 as long as there is data held. When receiving the write request signal, the memory interface circuit 57 supplies a read request signal read to the FIFO circuit 71 to read data. The output of the AND circuit 63 is
The signal is input to the AND circuit 53A via the inverter 64. Therefore, the user data of the sequence layer is not written in the FIFO circuit 70.

In this manner, the sequence layer user data can be supplied to the memory interface circuit 57 separately from other MPEG video streams.
Therefore, in the VBV buffer 17-1 of the MPEG decoding memory 17 of FIG. 1, the user data of the sequence hierarchy can be stored in a dedicated area different from other data.

In the above-described third embodiment, an example in which user data in the sequence layer is selected has been described. However, it is clear that user data in an arbitrary layer can be selected by a configuration similar to that shown in FIG. . FIG. 7 shows a circuit example of a fourth embodiment of the header detection unit 40 for selecting user data in the GOP layer. The header detection unit in FIG.
Only the combination of the set signal and the reset signal supplied to the flip-flop 61 is different from the header detection unit in FIG. In FIG. 7, the flip-flop 61 is a GO
It is set only when a P header is detected, and reset when other headers are detected. Therefore, the output of the flip-flop 61 becomes HIGH only when the current layer is the GOP layer. The output of the flip-flop 62 becomes HIGH when a user header is detected. Therefore,
By taking the AND of the output of the flip-flop 61 and the output of the flip-flop 62, only the user header and user data of the GOP layer can be detected.

The GOP layer user data selection circuit shown in FIG. 7 may be added to the circuit shown in FIG. 6 so that user data in the sequence layer and user data in the GOP layer can be individually selected. A similarly configured picture layer user data selection circuit may be further added so that user data of each of the sequence layer, the GOP layer, and the picture layer can be separately selected.

For example, user data in the GOP layer can be used for text-type digital data transfer such as teletext. As a result, text information related to the picture group of the GOP can be displayed on the screen. Specifically, for example, in a cooking program, cooking ingredients can be transmitted as text data in association with a screen, and the cooking ingredients can be displayed in characters along with the corresponding screen. If the viewer thinks the text is in the way, the text can be turned off. In a normal television image or the like, character information is transmitted as a television signal together with image information, and thus only character display cannot be erased. In addition, texts of various languages are transmitted as character information, and the viewer can display text information of his / her favorite language or native language.

In the third and fourth embodiments, when such processing is performed by fast forward reproduction, unnecessary user data is discarded and only necessary user data is stored in the MPEG decoding memory 17. Can be stored. Therefore,
The speed of writing / reading data to / from the MPEG decoding memory 17 can be reduced. Also, even in the case of normal-speed playback processing instead of fast-forward playback, discarding unnecessary data allows MP
This is useful because the reading speed can be reduced when reading the stream from the EG decoding memory 17.

Further, with the same configuration, not only the user data but also the extension start code and the extension data following the extension start code may be selected. Although the present invention has been described based on the embodiment in which MPEG is applied, the present invention is not limited to MPEG but can be applied to various types of image information multiplexed data. Further, the present invention is not limited to the above-described embodiment, and various changes and modifications can be made without departing from the scope of the present invention described in the appended claims.

[0072]

According to the first aspect of the present invention, only the necessary data in the data stream is written to the decoding memory by providing the header detection unit immediately after the stream decomposition unit. by this,
Unnecessary data can be discarded before writing to the decoding memory, so that the data writing / reading speed required for the decoding memory can be reduced.

According to the second aspect of the present invention, in fast-forward reproduction of an image, unnecessary data of a video stream is discarded before writing to the decoding memory, thereby requesting the decoding memory at the time of fast-forward reproduction. Data writing / reading speed can be reduced.

According to the third aspect of the present invention, it is possible to perform fast-forward reproduction of an image using only I-pictures without excessively requesting the decoding memory for data writing / reading speed. According to the fourth aspect of the present invention, by detecting each header of a video stream, fast-forwarding of an image using only I-pictures without excessively requesting the data write / read speed to the decoding memory. Playback becomes possible.

According to the fifth aspect of the present invention, the I / P picture alone or the I / P picture and the B picture can be used without excessively requiring the data write / read speed for the decoding memory. Fast forward reproduction of an image using a part of the image can be performed.

According to the sixth aspect of the present invention, by detecting each header of the video stream, the I / P picture and the P picture can be used without excessively requesting the data write / read speed for the decoding memory. Alternatively, fast forward reproduction of an image using part of an I picture, a P picture, and a B picture becomes possible.

According to the present invention, at least one of the user data and the extension data of the video stream is selected and stored in the memory, so that the user data or the extension data is handled separately from other data. In addition, the speed of data writing / reading required for the decoding memory can be reduced.

According to the eighth aspect of the present invention, by detecting each header of a video stream, user data can be handled separately from other data, and data writing required for a decoding memory can be performed. / The reading speed can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an image processing apparatus for an MPEG stream according to the present invention.

FIG. 2 is a diagram illustrating a header included in an MPEG stream.

FIG. 3 is a configuration diagram of a first embodiment of the header detection unit of FIG. 1;

FIG. 4 is a time chart for explaining the operation of the header detection unit in FIG. 3;

FIG. 5 is a configuration diagram of a second embodiment of the header detection unit of FIG. 1;

FIG. 6 is a configuration diagram of a third embodiment of the header detection unit of FIG. 1;

FIG. 7 is a configuration diagram of a fourth embodiment of the header detection unit of FIG. 1;

FIG. 8 is a configuration diagram of a conventional image processing apparatus for an MPEG stream.

FIG. 9 is a configuration diagram of the variable-length inverse coding unit of FIG. 7;

[Explanation of symbols]

 Reference Signs List 10 stream decomposition unit 11 variable-length inverse coding unit 12 inverse quantization unit 13 inverse DCT unit 14 adder 15 prediction unit 16 memory controller 17 MPEG decoding memory 18 output circuit 19 display 20 MPEG audio decoder 21 speaker 31 picture header storage register 32 shift register 33 comparator 41 OR circuit 42 octal counter 43 comparator 44 delay circuit 45, 46 register 47 sequence header comparator 48 GOP header comparator 49 I picture header comparator 50 P picture header comparator 51 B picture header comparison Device 52 RS flip-flop 53 AND circuit 54 FIFO memory 55 up / down counter 56 comparator 57 memory interface circuit 60 Zahedda comparator 61, 62 RS flip-flop 63 and circuit 64 inverter 70, 71 FIFO circuit

Claims (8)

[Claims] An image processing apparatus for decoding a video stream in a multiplexed data stream to display image information, comprising: a stream decomposition unit that receives the data stream and extracts the video stream; A header detection unit that receives the video stream from the stream decomposition unit, detects a predetermined header from the video stream, and outputs a selected video stream including the predetermined header and data associated with the predetermined header; An image processing apparatus, comprising: a memory for storing the selected video stream; and a video decoder for decoding the selected video stream stored in the memory. 2. The image processing apparatus according to claim 1, wherein the data stream is supplied at a data rate faster than normal reproduction for fast-forward reproduction of the image information. 3. The header detection unit detects an I-picture header as the predetermined header, discards P-pictures and B-pictures, and outputs the selected video stream consisting of only I-pictures. The image processing apparatus according to claim 2. 4. The P picture header, comprising: an I picture header detector, a P picture header detector, a B picture header detector, a sequence header code detector, and a group start code detector. 4. The image processing apparatus according to claim 3, wherein when the video stream is detected, the video stream is discarded until one of the I picture header, the sequence header code, and the group start code is detected next. . 5. The header detection unit detects an I-picture header and a P-picture header as the predetermined header, and discards all or part of a B-picture to obtain an I-picture header.
The image processing apparatus according to claim 2, wherein the selected video stream including a picture and a P picture is output. 6. The B picture header, comprising: an I picture header detector, a P picture header detector, a B picture header detector, a sequence header code detector, and a group start code detector. Is detected, the B picture is selectively or entirely discarded, and then the I picture header and the P picture are discarded.
6. The image processing apparatus according to claim 5, wherein the video stream is completely or partially discarded until one of a picture header, a sequence header code, and a group start code is detected. 7. The header detection unit detects at least one of a user data start code and an extension start code as the predetermined header, and decodes the selected video stream including at least one of user data and extension data. The image processing device according to claim 1, wherein the image is output. 8. The header detection unit includes an I picture header detector, a P picture header detector, a B picture header detector, a sequence header code detector, a group start code detector, and a user data start code. A detector, and when the user data start code is detected, whether the previously detected header is an I picture header, a P picture header, a B picture header, a sequence header code, or a group start code. Determines whether the detected user data start code is of a sequence layer, a group of picture layer, or a picture layer, and converts the selected video stream composed of the user data of a predetermined hierarchy to the selected video stream. Feature to output The image processing apparatus according to claim 7, wherein: