JP2008236784A - Mpeg video decoder and mpeg video decoding method - Google Patents

Mpeg video decoder and mpeg video decoding method Download PDF

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JP2008236784A
JP2008236784A JP2008119912A JP2008119912A JP2008236784A JP 2008236784 A JP2008236784 A JP 2008236784A JP 2008119912 A JP2008119912 A JP 2008119912A JP 2008119912 A JP2008119912 A JP 2008119912A JP 2008236784 A JP2008236784 A JP 2008236784A
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picture
decoding
display
control unit
register
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JP4769268B2 (en
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Hirohiko Inagaki
Tadami Kono
Mitsuhiko Ota
光彦 太田
忠美 河野
博彦 稲垣
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Fujitsu Ltd
富士通株式会社
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T9/00Image coding
    • G06T9/007Transform coding, e.g. discrete cosine transform

Abstract

An MPEG video decoder and an MPEG video decoding method capable of using slow playback in combination with video display by 3-2 pull-down are provided.
An image decoding unit 112 starts decoding an MPEG bitstream in response to a decoding start command, and a decoded frame buffer 113 stores decoded picture data. The display control unit 115 analyzes the parameters of the picture data decoded by the image decoding unit 112, and controls the transfer of the picture data from the decoded frame buffer 113 to the display device according to the result. The decoding control unit 114 outputs a decoding start command based on the picture data parameter.
[Selection] Figure 5

Description

  The present invention relates to an MPEG video decoder and an MPEG video decoding method for decoding a bitstream encoded in accordance with the MPEG (Moving Picture Experts Group) standard.

  MPEG is used as an international standard for high-efficiency bit rate reduction of image data. A moving picture encoding technique and a moving picture decoding technique compliant with the MPEG standard are indispensable techniques in recent multimedia environments. Many moving picture encoding apparatuses and moving picture decoding apparatuses adopting the MPEG standard have been developed.

  For high-efficiency coding according to the MPEG standard, there is a constant bit rate (hereinafter referred to as CBR coding) in which the data generation amount (data rate) after coding is substantially constant, and a data rate after coding. There is non-constant variable rate coding (variable bitrate: hereinafter referred to as VBR coding).

  CBR encoding is used when the transmission path is STM (Synchronus Transfer Mode). VBR encoding is used when the transmission path is ATM (Asynchronus Transfer Mode) or storage media such as DVD (Digtal Video Disc).

  Hereinafter, picture types, bit streams, MPEG video encoders and conventional MPEG video decoders used in MPEG will be described.

(1) Picture type In MPEG, for high-efficiency encoding, an intra picture (intre-coded picture: hereinafter referred to as I picture), a predictive coded picture (hereinafter referred to as P picture), and bidirectional Three types of pictures called predictive-coded pictures (hereinafter referred to as B pictures) are used.

  An I picture is encoded using only information of its own picture without using information of other pictures. A P picture is encoded using a past I picture or P picture as a reference picture. A B picture is encoded using a past and future I picture or P picture as a reference picture.

  Although the I picture has a low compression rate, it can be encoded independently of other pictures, and is therefore used as an access point during random access. No other picture information is required for decoding the I picture. Although the P picture has a higher compression rate than the I picture, information on the past I picture is required for decoding. In addition, the B picture has the highest compression rate, but decoding thereof requires information on past and future I pictures or P pictures.

(2) Bitstream FIG. 14 is a schematic diagram showing the structure of an MPEG bitstream. The bit stream is composed of a sequence header 31, a GOP header (groupof pictures header) 32, a picture header 33, picture data 34, and a sequence end code 35. . In addition to these, the bitstream includes a sequence extension, an extension, and user data (extension and user data).

  The sequence header 31 is always present at the beginning of the bit stream. The sequence header 31 includes the number of pixels in the horizontal and vertical directions (horizontal size value, vertical size value) of the image, parameters (aspect ratio information) indicating the pixel aspect ratio, and the like.

  The GOP header 32 is added to the bit stream when a large number of pictures are managed for each GOP. The GOP is composed of a plurality of types of pictures, and the first picture of the GOP is always an I picture. GOP is essential in MPEG1, but is optional in MPEG2.

  The picture header 33 represents the start of encoded data for one picture. The picture header 33 includes a parameter (temporal reference) indicating the order of pictures, a picture type, and the like.

  The picture data 34 is encoded data for one picture. The picture data 34 is followed by a GOP header 32, a next picture header 33 or a sequence end code 35. The sequence end code 35 indicates the end of the bit stream.

(3) Configuration of MPEG Video Encoder FIG. 15 is a block diagram showing an MPEG video encoder.

  The MPEG video encoder includes a picture rearrangement unit 41, a motion estimation unit 42, an adder 43, a discrete cosine transform (hereinafter referred to as DCT) unit 44, a quantization unit 45, a variable length encoding unit 46, a multiplexing unit. A unit 47, a buffer 48, an inverse quantization unit 49, an inverse discrete cosine transform (hereinafter referred to as IDCT) unit 50, an adder 51, a picture storage unit 52, and a motion prediction unit 53 are configured.

  In MPEG, there are B pictures that are decoded with reference to past and future pictures, so it is necessary to process future pictures first. The picture rearrangement unit 41 rearranges the pictures in the processing order.

  The motion estimation unit 42 receives a picture from the picture rearrangement unit 41, and various parameters necessary for decoding, such as a picture type, a presentation time stamp (PTS), a quantization step size, a motion vector, and a code Output the mode. These parameters are input to the motion prediction unit 53 and added to the bit stream by the multiplexing unit 47.

  The adder 43 calculates a difference between the picture output from the motion estimation unit 42 and the reference picture output from the motion prediction unit 53. When processing an I picture, no reference picture is output from the motion prediction unit 53, so the picture output from the motion estimation unit 42 is input to the DCT unit 44 through the adder 43. Further, when processing a P picture or a B picture, the adding unit 43 calculates and outputs the difference between the picture output from the motion estimation unit 42 and the reference picture output from the motion prediction unit 53.

  The DCT unit 44 performs discrete cosine transform on the input data and divides it into frequency components, and removes high frequency components, thereby reducing the data amount. The quantization unit 45 removes less important information by quantization, which is an irreversible process. The variable length encoding unit 46 performs variable length encoding by zigzag scanning the quantized data, and further reduces the data amount.

  On the other hand, the inverse quantization unit 49 and the IDCT unit 50 perform the discrete cosine transform and the inverse quantization on the data obtained by the discrete cosine transform and the quantization performed by the DCT unit 44 and the quantization unit 45. The adder 51 adds the data output from the IDCT unit 50 and the reference picture output from the motion prediction unit 53 to restore the picture, and stores it in the picture storage unit 52. The motion prediction unit 53 performs motion prediction based on the motion vector output from the motion estimation unit 42, the output of the adder 51, and the picture stored in the picture storage unit 52. Also, the motion prediction unit 53 uses the output of the adder 51 or the picture stored in the picture storage unit 52 as a reference picture, and outputs the reference picture to the adder 43.

  The multiplexing unit 47 multiplexes the data output from the variable length encoding unit 46 and the parameters such as the encoding mode and the motion vector output from the motion estimation unit 42 to create a bit stream. The buffer 48 temporarily stores the created bit stream.

(4) Configuration of MPEG video decoder (part 1)
FIG. 16 is a block diagram showing a conventional MPEG video decoder.

  The MPEG video decoder includes a bit stream input terminal 60, a bit stream buffer 61, an image decoding unit 62, a decoded frame buffer 63, a decoding switch 64, and a picture data output unit 65. The picture data output unit 65 includes a display control unit 65a, a display switch 65b, and a display buffer 65c.

  The bit stream buffer 61 stores the bit stream input from the input terminal 60 and sequentially outputs it to the image decoding unit 62. The decoding switch 64 outputs a decoding start command 72 when the vertical synchronization signal V-Sync 71 is input from the display control unit 65a. When the decoding start command 72 is input from the decoding switch 64, the image decoding unit 62 inputs a bit stream for one picture from the bit stream buffer 61, and performs variable decoding processing, inverse quantization processing, inverse discrete cosine transform processing, and Perform motion prediction. The pictures decoded by the image decoding unit 62 in this way are sequentially stored in the decoded frame buffer 63. Note that the image decoding unit 62 refers to the picture previously stored in the decoded frame buffer 63 as necessary when decoding the bitstream. Therefore, the decoded frame buffer 63 needs to hold the decoded picture at least until it is not referred to for decoding other pictures. Further, when decoding the bit stream, the image decoding unit 62 extracts a display time stamp (PTS) 76 from the bit stream and outputs it to the picture data output unit 65.

  The display control unit 65a compares the display time stamp PTS of the decoded picture with its own reference clock (STC), and outputs a transfer instruction 73 to the display switch 65b when the two match. When the transfer command 73 is input, the display switch 65b transfers data for one picture (picture data) from the decoded frame buffer 63 to the display buffer 65c. The picture data stored in the display buffer 65c is transmitted to the display device 66 in synchronization with the vertical synchronization signal V-Sync 71 output from the display control unit 65a.

  In this way, in the conventional MPEG video decoder, the bit stream is read out from the bit stream buffer 61 for one picture at a timing synchronized with the vertical synchronization signal V-Sync 71 and decoded, and the vertical synchronization signal V-Sync 71 is converted into the vertical synchronization signal V-Sync 71. The picture is transmitted from the display buffer 65c to the display device 66 at the synchronized timing. Thereby, the image displayed on the display device 66 is updated at the timing synchronized with the vertical synchronization signal V-Sync, and the moving image is displayed on the display device 66.

  By the way, in order to reproduce a smooth moving image, an MPEG video decoder is required to decode a bit stream in real time. In order to satisfy this requirement, the MPEG video decoder completes decoding of the bit stream for one picture within one frame time (reciprocal of the number of frames per second), and one picture for every frame time. It is necessary to have the ability to output data to a display device. In the conventional MPEG video decoder, the decoding of the bit stream for one picture is completed within one frame time. As described above, the timing at which the MPEG video decoder starts decoding the bit stream for one picture and the timing at which data for one picture is output from the MPEG video decoder to the display device are both vertical. It is synchronized with the synchronization signal V-Sync.

(Other conventional technologies)
In MPEG, when a video with a frame rate of 24 frames / second, such as a movie, is converted into a television video with a frame rate of 30 frames / second (telecine conversion), a conversion process called 3-2 pull-down is performed. In 3-2 pull-down, a command called repeat first field is used. The repeat first field command is an instruction “display the first displayed field again”.

  FIG. 17 is a schematic diagram showing telecine conversion by 3-2 pull-down. In FIG. 17, * indicates the same image repetition, and * 'indicates the same image repetition by the repeat first field.

  In NTSC (National Television System Committee) television images, one frame is divided into two fields (top field and bottom field). Accordingly, a television image for one second is composed of images for 60 fields.

  As shown in FIG. 17, when converting a movie image to a television image, image data for 24 frames is generated by assigning one image to the top field (T) and bottom field (B) of each frame. Is done. However, as it is, image data for 6 frames (12 fields) is insufficient. Therefore, in telecine conversion, repeat first field commands are added to 12 out of 24 frames to generate image data for 12 fields. That is, for example, by adding a repeat first field command to an odd-numbered frame, an image of the odd-numbered frame is displayed three times (for three fields). In FIG. 17, an arrow (↓) indicates an image that is repeatedly displayed by the repeat first field command. In this way, with 3-2 pull-down, a video of 24 frames / second can be converted into a video of 30 frames / second.

(5) Configuration of MPEG video decoder (part 2)
FIG. 18 is a block diagram showing an MPEG video decoder corresponding to 3-2 pull-down. The MPEG video decoder includes a bit stream input terminal 160, a bit stream buffer 161, an image decoding unit 162, a decoded frame buffer 163, a decoding control unit 164, and a display control unit 165.

  The bit stream buffer 161 stores the bit stream input from the input terminal 160 and sequentially outputs it to the image decoding unit 162 for each picture. The image decoding unit 162 decodes the bit stream sent from the bit stream buffer 161. The picture decoded by the image decoding unit 162 is transferred to the decoded frame buffer 163.

  The decoded frame buffer 163 has a storage area for three pictures, for example, and the storage area is divided for each picture. A storage area partitioned for each picture is called a bank. Each bank has a unique address (bank address).

  The decoding control unit 164 includes a V-Sync generator (not shown) that generates a vertical synchronization signal (V-Sync), and is synchronized with the V-Sync output from the V-Sync generator. A decryption start instruction 172 is issued. The image decoding unit 162 starts decoding a picture in response to a decoding start instruction 172. The issuing period of the decoding start instruction 172 is basically once every two field times, that is, once every one frame time. This is because the display speed is one picture per frame, so that the decoding speed matches the display speed.

  In addition, the decoding control unit 164 issues an initial decoding start instruction 171 when a certain amount of bit stream is stored in the bit stream buffer 161 after power-on (after a cold start). The timing at which this initial decoding start instruction 171 is issued is not related to V-Sync.

  The display control unit 165 has four registers: a reorder register 165a, a current register 165b, a field delay register 165c, and a display register 165c. The display control unit 165 receives the decoding start command 172, the V-Sync 175, and the bank address 176 from the decoding control unit 164, and the sequence parameters and picture parameters obtained by decoding the bitstream from the image decoding unit 162, etc. These parameters 173 are input. The bank address 176 is data indicating in which bank of the decoded frame buffer 163 the decoded picture is stored. The display control unit 165 outputs a field wait instruction 174 to the decoding control unit 164 when conditions described later are met. The field wait instruction 174 is an instruction for waiting for the issuance of the decoding start instruction 172 for one field period.

  Further, the display control unit 165 issues a display start command 178 when a condition described later is satisfied. In response to a display start instruction 178 issued from the display control unit 165, a predetermined picture is transferred from the decoded frame buffer 163 to the display device, and an image is displayed on the display device.

  Hereinafter, the four registers 165a to 165d of the display control unit 165 will be described with reference to the schematic diagram of FIG.

(1) Reorder register 165a
The reorder register 165a stores I picture and P picture parameters and bank addresses. The I picture and the P picture are not displayed immediately after the decoding is completed, and it is necessary to rearrange (reorder) the B picture. Therefore, the I picture and P picture parameters and the bank address are temporarily saved in the reorder register 165a.

(2) Current register 165b
The current register 165b stores a parameter and a bank address of a picture to be displayed. Since the B picture is displayed immediately after the decoding is completed, the B picture parameter and bank address are not stored in the reorder register 165a but directly in the current register 165b.

  The display control unit 165 analyzes the parameter stored in the current register 165b, and issues a field wait instruction 174 to the decoding control unit 164 if the repeat first field flag is “1”.

(3) Field delay register 165c
The field delay register 165c delays the bank address transferred from the current register 165c by one field time in order to set the decoding time to one frame time, and transfers it to the next display register 165d. If the field delay register 165c is not provided, the field slot at the display timing becomes the field slot immediately after the field slot at the decoding timing, and display cannot be performed at the correct timing. Only the bank address 176 is stored in the field delay register 165c.

(4) Display register 165d
The display register 165d stores the bank address of the picture currently being displayed. In other words, the display control unit 165 issues a display start command so as to display the picture indicated by the bank address stored in the display register 165d. Only the bank address 176 is stored in the display register 165d.

  These four registers 165a to 165d have a shift register structure as shown in FIG. The shift pulse of the reorder register 165a and the current register 165b is a decoding start instruction 172, and the shift pulse of the field delay register 165c and the display register 165d is V-Sync 175. The bank address 176 is completely shifted from the reorder register 165a to the display register 165d, while the parameter 173 is shifted only to the current register 165b.

  Next, the operation of the above-described MPEG video decoder will be described with reference to the time charts of FIGS. However, in this example, a bit stream is input in the order of I picture I2, B picture B0, B picture B1, P picture P5, B picture B3, B picture B4,..., Picture B0, picture B1, picture I2, picture Assume that B3, picture B4, picture P5,... Are displayed in this order. It is assumed that a repeat first field command is added to the B pictures B0, B4 and the I picture I2.

  The MPEG bit stream sent from the transmission path or the storage medium is first stored in the bit stream buffer 161. When a certain amount of data (for example, data for one picture) is accumulated in the bit stream buffer 161, the decoding control unit 164 issues an initial decoding start instruction 171. When receiving the initial decoding start instruction 171, the image decoding unit 162 decodes only the picture header (I 2) of the first picture I 2, and stops the decoding process when the decoding of the picture header (I 2) is completed (time t 0).

  Thereafter, the decoding control unit 164 issues a decoding start instruction 172 at a timing synchronized with V-Sync (time t1). Upon receiving the decoding start instruction 172, the image decoding unit 162 starts decoding the “coefficient” of the picture I2. When the coefficient decoding of the picture I2 is completed, the picture decoding unit 162 subsequently decodes the picture header (B0) of the next picture B0. . When the decoding of the picture header (B0) of the picture B0 is completed, the decoding process is stopped (time t2).

  On the other hand, the display control unit 165 receives the parameter of the picture I2 from the image decoding unit 164 at time t1, and stores it in the reorder register 165a. At this time, the reorder register 165a stores the parameter of the picture I2 at a timing synchronized with the decoding start instruction 172 using the decoding start instruction 172 as a latch pulse.

  At time t3, the decoding control unit 164 issues a decoding start command 172 again in synchronization with the V-Sync 175, whereby the image decoding unit 162 removes the picture header from the data for one picture of the picture B0. Decoding of the coefficients (hereinafter simply referred to as “coefficients”) is started. At the same time, the parameter 173 of the picture B0 is stored in the current register 165b.

  When the parameter of the picture B0 is stored in the current register 165b at time t3, the display control unit 165 analyzes the parameter stored in the current register 165b. As a result, since the repeat first field flag of the picture B0 is “1”, the display control unit 165 issues a field wait instruction 174 to the decoding control unit 164 (time t3.5).

  When receiving the field wait instruction 174, the decoding control unit 164 waits for a time corresponding to one field for the decoding start instruction 172 for the picture B1 that should be issued at time t5, and issues it at time t6.

  When a decoding start instruction 172 for the picture B1 is issued by the decoding control unit 164 at time t6, the image decoding unit 162 starts coefficient decoding of the picture B1, and the current register 165b of the display control unit 165 stores the picture B1. Stores parameters. The display control unit 165 analyzes the parameters stored in the current register 165b. As a result, the repeat first field flag of the picture B1 is “0”, so the field wait instruction 174 is not issued.

  Since the field wait instruction is not issued, the decoding control unit 164 issues the decoding start instruction 172 for the next picture P5 picture at time t7 without waiting for one field time.

  When the decoding start instruction 172 for the picture P5 is issued at time t7, the parameter of the picture I2 that has been in the reorder register 165a until then is shifted to the current register 165b, and the parameter of the picture P5 is stored in the reorder register 165a.

  As a result of analysis of the current register 165b by the display control unit 165, the repeat first field flag of the picture I2 is “1”, so the field wait instruction 174 is issued.

Hereinafter, if the current register 165b is checked and the repeat first field flag of the next picture to be displayed is “1”, the field wait instruction 174 is issued, and the decoding start instruction 172 is issued after waiting for one field time. By repeating this sequence, 3-2 pulldown is realized. That is, in the conventional MPEG video decoder, 3-2 pull-down is realized by a method of resting decoding for one frame time by a repeat first field command.
Japanese Patent Laid-Open No. 10-093917 Japanese Patent Laid-Open No. 05-122538 Japanese Patent Application Laid-Open No. 08-12585 JP 09-009258 A JP 09-093577 A

  If the data rate is almost constant as in CBR encoding, the time required to decode a bit stream for one picture is almost uniform, and decoding a bit stream for one picture within one frame time is It is relatively easy. However, when a VBR encoded bit stream is decoded as in an ATM terminal or a DVD player, the data rate changes greatly, and therefore it is often impossible to decode a bit stream for one picture within one frame time. Become. When the bit stream for one picture cannot be decoded within one frame time, the decoding of the bit stream is completed using the time for the next one frame. Then, the picture data to be output to the display device is subtracted for one frame, and the reproduction time is adjusted. Adjusting the playback time by thinning out picture data in this way is called error concealment.

  When decoding a VBR encoded bit stream such as an ATM terminal or a DVD player, as described above, since the data rate is not constant, it often takes one frame time or more to decode a bit stream for one picture. Error concealment frequently occurs, making smooth video playback difficult.

  In addition, in the conventional MPEG video decoder described above, inconvenience arises if 3-2 pull-down and slow playback such as 1/2 times speed and 1/4 times speed are realized simultaneously. As described above, in the conventional MPEG video decoder, 3-2 pull-down is realized by a method of “resting decoding for one frame time”, but slow playback also performs decoding for “one frame time”. This is because it is realized by the method of "rest". The above inconvenience will be described in more detail with reference to the timing charts of FIGS.

  Assume that a ½ double speed display command (hereinafter, ½ slow playback command) is issued at time t2.2. In the conventional MPEG video decoder, the 1/2 slow playback command is input to the decoding control unit 164. The decoding control unit 164 performs the decoding control by sampling the 1/2 slow reproduction command at the timing of the decoding start command 172 issued by the decoding control unit 164 itself (time t3). That is, if the 1/2 slow playback command is “1” when the decoding start command 172 is issued, the decoding start of the next picture is delayed by one frame time, and the picture that has just started decoding is displayed for two frame times. Take control.

  In normal playback, one picture is displayed for one frame time, so displaying one picture for two frame times means displaying a video at half the speed.

  In this example, the result of sampling the 1/2 slow playback command at time t3 is “1”. Therefore, after the decoding of the picture B0 is completed, the decoding of the next picture B1 is delayed by one frame time, and starts from t6.5.

  By the way, since the repeat first field flag of the picture B0 is “1”, the field wait instruction 174 is issued from the display control unit 165 (time 3.5). Therefore, the decoding control unit 164 executes both “wait for one frame time (2 field times)” by the 1/2 slow playback command and “wait for one field time” by the field wait command 174. At this time, since the latter has a shorter waiting time than the former, the latter is ignored (time t5 to t6). That is, in the conventional MPEG video decoder, although “3-2 pull-down display and 1/2 flow reproduction” should be originally performed, it is merely “1/2 slow reproduction”.

  As shown in FIGS. 22 and 23, assuming that the 1/2 slow playback command is “1” from time t2.2 to t6.7, the picture B0 is originally supposed to be displayed for 6 frame periods. Instead, only two frame periods are displayed.

  An object of the present invention is to provide an MPEG video decoder and an MPEG video decoding method capable of using slow playback together with video display by 3-2 pull-down.

  The purpose described above is to store an image decoding unit 112 that starts decoding an MPEG bitstream by a decoding start instruction 122 and picture data decoded by the image decoding unit 112, as illustrated in FIG. The decoding frame buffer 113 and the parameters of the picture data decoded by the image decoding unit 112 are analyzed for each predetermined picture, and according to the result, the picture data from the decoding frame buffer 113 to the display device is analyzed. This is achieved by an MPEG video decoder including a display control unit 115 that controls transfer and a decoding control unit 114 that outputs the decoding start instruction 122 based on the parameters of the picture data.

  In the present invention, the display control unit 115 analyzes the parameters of the picture data, and controls the transfer of the picture data from the decoded frame buffer 113 to the display device according to the result. For example, for a certain picture, the display control unit 115 determines the number of display fields for each picture from the parameters, and displays the picture on the display device for a time corresponding to the number of display fields, while the parameter of the next picture is displayed. To determine the number of display fields. When the display time of one picture has passed, display of the next picture is started.

  With this configuration, if the relationship between the parameter and the number of display fields is set, special playback such as 3-2 pull-down playback or 1/2 slow playback can be easily handled. For example, FIG. 9 shows the number of display fields when only 3-2 pull-down playback is performed, the number of display fields when only 1/2 slow-down playback, and the number of display fields when 3-2 pull-down playback and 1/2 through playback are performed. The table is stored in the display control unit 115 as illustrated in FIG. When determining the number of display fields, an appropriate number of display fields can be easily determined by referring to this table.

  The display control unit 115 is provided with four shift registers, a reorder register 115a, a current register 115b, a field delay register 115c, and a display register 115d, and the picture data in the decoded frame buffer 113 is received by these registers 115a to 115d. to manage. In this case, it is preferable to provide a status register 116 so that the states of the registers 115a to 115d can be easily understood. The decryption control unit 114 refers to the status of the status register 116 and outputs a decryption start instruction 112 if it is found that no data is stored in the reorder register 115a or the current register 115b. If the display field number calculation unit 115f refers to the status register 116 and finds that data is stored in the display register 115d, the display field number calculation unit 115f determines the number of display fields of the picture corresponding to the data stored in the display register 115d. .

  The timing at which the decoding control unit 114 and the display control unit 115 refer to the status register 116 can be a timing synchronized with, for example, a vertical synchronization signal (V-Sync). Further, in the method of the present invention, since decoding of pictures is continuously performed until a certain amount of picture data is accumulated in the decoding frame buffer, the occurrence of error concealment is suppressed, and smooth video playback is possible. .

  According to the present invention, the display control unit 115 analyzes the “parameters of the picture data, and controls the transfer of the picture data from the decoded frame buffer 113 to the display device according to the result. Special reproduction such as reproduction, 3-2 pull-down reproduction and flow reproduction can be realized.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

(First embodiment)
FIG. 1 is a block diagram showing an MPEG video decoder according to the first embodiment of the present invention. The MPEG video decoder according to the present embodiment includes a bit stream input terminal 10, a bit stream buffer 11, an image decoding unit 12, a decoded frame buffer 13, a decoding start instruction generating unit 14, and a picture data output unit 15. .

  The bit stream input terminal 10 receives an MPEG bit stream from an ATM transmission path or a storage medium such as a DVD. The bit stream buffer 11 is a memory that temporarily stores a bit stream.

  The image decoding unit 12 receives a bit stream from the bit stream buffer 11 and performs decoding by performing variable length decoding processing, inverse quantization processing, inverse discrete cosine transform processing, and motion prediction. When receiving the decoding start command 22 from the decoding start command generating unit 14, the image decoding unit 12 starts decoding a bit stream for one picture. When the decoding for one picture is completed, a decoding completion notification 23 is output to the decoding start instruction generating unit 14. Note that the image decoding unit 12 extracts a display time stamp (PTS) 26 from the bit stream when decoding the bit stream, and outputs it to the picture data output unit 15.

  The decoded frame buffer 13 stores a plurality of decoded pictures. As described above, there are three types of pictures: I picture, P picture, and B picture. When decoding an I picture, the image decoding unit 12 performs decoding without referring to another picture. When decoding a P picture, the image decoding unit 12 refers to a past picture (I picture or P picture) stored in the decoded frame buffer 13. When decoding a B picture, the image decoding unit 12 refers to past and future pictures (I picture and P picture) stored in the decoded frame buffer 13. Accordingly, when the B picture is not used, that is, when only the I picture and the P picture are used, the pictures are decoded in the display order. On the other hand, when a B picture is used, the decoding order and the display order are different, so the pictures are rearranged in the display order in the decoded frame buffer 13.

  It is necessary to hold the decoded picture in the decoded frame buffer 13 until it is not referred to for decoding other pictures. Accordingly, the capacity of the decoded frame buffer 13 needs to be large to some extent. However, for the sake of simplicity of explanation, the decoded frame buffer 13 has a storage capacity for three pictures and decodes a P picture or a B picture. It is assumed that one or two pictures previously decoded are referred to at the time of conversion. When the decoding frame buffer 13 stores a predetermined number (three in this example) of pictures, it outputs a buffer full notification 24.

  The decoding start command generation unit 14 includes a decoding control unit 14a and a decoding switch 14b. The decoding control unit 14a includes a bit stream transfer notification 25 transmitted from the outside (for example, a host computer), a decoding completion notification 23 output from the image decoding unit 12, and a buffer full notification 24 output from the decoding frame buffer 13. Based on the above, the decoding start permission 21 is output. That is, the decoding control unit 14a receives the bitstream transfer notification 25 from the host computer, the decoding completion notification 23 from the image decoding unit 12, and the buffer full notification 24 from the decoding frame buffer 13. Sometimes, the decryption start permission 21 is output. When the decoding start permission 21 is output from the decoding control unit 14a, the decoding switch 14b outputs a decoding start command 22 to the image decoding unit 12.

  In this embodiment, it is assumed that the host computer outputs a bit stream transfer notification when a bit stream of one picture or more is transferred to the bit stream buffer 11. Therefore, the image decoding unit 12 starts decoding the first picture after the bit stream of one picture or more is stored in the bit stream buffer 11.

  The picture data output unit 15 includes a display control unit 15a, a display switch 15b, and a display buffer 15c. When the display time stamp (PTS) 26 of the decoded picture matches its own reference clock (STC), the display control unit 15a outputs a transfer command 29 to the display switch 15b. When the transfer command 29 is input, the display switch 15b transfers picture data from the decoded frame buffer 13 to the display buffer 15c. The picture data stored in the display buffer 15c is transmitted to the display device 16 in synchronization with the vertical synchronization signal V-Sync 28 output from the display control unit 15a. Thereby, an image is displayed on the display device 16.

  The display device 16 may be an NTSC (National Television System Committee) system or a PAL (Phase Alternation Line) system. Further, the image decoding unit 12, the decoding control unit 14a, and the display control unit 15a may all be configured by hardware (semiconductor device), or may be realized by software. .

  FIG. 2 is a timing chart showing the operation of the MPEG video decoder of this embodiment.

  Assume that input of a bit stream from the input terminal 10 to the bit stream buffer 11 is started at time t0. When the storage of the bit stream for one picture is completed in the bit stream buffer 11 at time t1, the bit stream transfer notification 25 is input from the host computer to the decoding control unit 14a. Thereby, the decryption control unit 14a outputs the decryption start permission 21. When receiving the decoding start permission 21 from the decoding control unit 14a, the decoding switch 14b outputs a decoding start command 22 to the image decoding unit 12. Thereby, the image decoding unit 12 starts decoding the first picture data (picture 1), and stores the decoded picture data in the decoded frame buffer 13.

  When decoding of picture 1 is completed at time t2, the image decoding unit 12 outputs a decoding completion notification 23. Thereafter, the storage of picture 1 in the decoded frame buffer 13 is completed slightly after time t2. At this time, since only one storage area of the three storage areas of the decoded frame buffer 13 is used, the buffer full notification 24 is not output from the decoded frame buffer 13. Accordingly, when receiving the decoding completion notification 23 from the image decoding unit 12, the decoding control unit 14a outputs the decoding start permission 21 to the decoding switch 14b. Then, the decoding switch 14 b outputs a decoding start command 22 to the image decoding unit 12. As a result, the image decoding unit 12 starts decoding the second picture data (picture 2).

  When the decoding of picture 2 is completed, the image decoding unit 12 outputs a decoding completion notification 23. Thereby, the decoding control unit 14a outputs a decoding start permission 21 to the decoding switch 14b, and the decoding switch 14b outputs a decoding start command 22 to the image decoding unit 12. Then, the image decoding unit 12 starts decoding the third picture data (picture 3).

  On the other hand, the display control unit 15a outputs a transfer command 29 to the display switch 15b and transfers the first picture data (picture 1) from the decoded frame buffer 13 to the display buffer 15c. Then, the picture 1 is transmitted from the display buffer 15 c to the display device 16 in synchronization with the vertical synchronization signal V-Sync 28. Thereby, the image by the picture 1 is displayed on the display device 16 for one frame period (two vertical synchronization periods).

  When decoding of picture 3 is completed at time t3, a decoding completion notification 22 is output from the image decoding unit 12 to the decoding control unit 14a. As a result, the decoding control unit 14 a outputs the decoding start permission 21, and the decoding switch 14 b outputs the decoding start instruction 22 to the image decoding unit 12. As a result, the image decoding unit 12 starts decoding the fourth picture data (picture 4).

  On the other hand, when the decoding frame buffer 13 starts storing the picture 4 (time t4), it outputs a buffer full notification 24 to the decoding control unit 14a.

  When decoding of picture 4 is completed at time t5, the image decoding unit 12 outputs a decoding completion notification 23 to the decoding control unit 14a. However, the decoding control unit 14 a does not output the decoding start permission 21 because the buffer full notification 24 is output from the decoding frame buffer 13. Therefore, the image decoding unit 12 interrupts decoding of the picture data.

  When the display of the image by picture 1 is completed at time t6, the display control unit 15a compares the display time stamp (PTS) of the picture data stored in the decoded frame buffer 13 with its own reference clock (SCR). Thus, since it is understood that it is time to output picture 2, display control unit 15a outputs transfer command 29 to display switch 15b, and transfers picture 2 from decoded frame buffer 13 to display buffer 15c. Then, the picture 2 is transmitted from the display buffer 15 c to the display device 16 in synchronization with the vertical synchronization signal V-Sync 28. Thereby, the image by the picture 2 is displayed on the display device 16.

  On the other hand, in the decoded frame buffer 13, the picture 2 is transferred to the display buffer 15c, so that a storage area is vacant. As a result, the buffer full notification 24 is canceled. Accordingly, the decoding start permission 21 is output from the decoding control unit 14a to the decoding switch 14b, and the decoding start instruction 22 is output from the decoding switch 14b to the image decoding unit 12. In response to the decoding start instruction 22, the image decoding unit 12 starts decoding the fifth picture data (picture 5).

  When the storage of the picture 5 is started in the decoded frame buffer 13 at time t7, the decoded frame buffer 13 outputs a buffer full notification 24 to the decoding control unit 14a. Thus, even when the decoding of the picture 5 is completed and the decoding completion notification 23 is output from the image decoding unit 12 to the decoding control unit 14a, the decoding control unit 14a does not output the decoding start permission 21. Therefore, after the decoding of the picture 5 is completed, the image decoding unit 12 interrupts the decoding process.

  When the display of the picture by picture 2 is completed at time t8, display control unit 15a turns on display switch 15b and transfers picture 3 from decoded frame buffer 13 to display buffer 15c. The display control unit 15a transmits the picture 3 from the display buffer 15c to the display device 16 in synchronization with the vertical synchronization signal V-Sync28. Thereby, the image by the picture 3 is displayed on the display device 16.

  Further, since picture 3 is transferred from the decoded frame buffer 13 to the display buffer 15c, a space is generated in the decoded frame buffer 13, and the buffer full notification 24 is released. Accordingly, the decoding start permission 21 is output from the decoding control unit 14a to the decoding switch 14b, and the decoding start instruction 22 is output from the decoding switch 14b to the image decoding unit 12. As a result, the image decoding unit 12 starts decoding the sixth picture data (picture 6).

  In this way, the MPEG video decoder according to the present embodiment performs picture decoding at a timing corresponding to the decoding completion notification 23 output from the image decoding unit 12 and the buffer full notification 24 output from the decoded frame buffer 13. Start decrypting data.

  FIG. 3 compares the likelihood of occurrence of error concealment between the conventional MPEG video decoder that starts decoding picture data in synchronization with the vertical synchronization signal V-Sync and the MPEG video decoder of this embodiment. It is a figure for doing. In FIG. 3, hatching indicates a frame in which error concealment occurs.

  As shown in FIG. 3, in the case of a bitstream including many pictures (P3, P6, and P7 in FIG. 3) that cannot be decoded within one frame time, decoding is started in synchronization with the vertical synchronization signal V-Sync. In such a conventional MPEG video decoder, an error concealment occurs whenever decoding of data for one picture is not completed within one frame time (two vertical synchronization periods). On the other hand, in the MPEG video decoder according to the present embodiment, if there is an empty storage area in the decoding frame buffer 13, pictures are continuously decoded. Therefore, decoding of data for one picture is completed within one frame time. Even if not, error concealment may be avoided. In the example shown in FIG. 3, error concealment occurs only once.

  As described above, in the MPEG video decoder according to the present embodiment, the decoding start timing is not synchronized with the vertical synchronization signal V-Sync28. That is, if there is an empty storage area in the decoded frame buffer 13, the image decoding unit 12 continuously decodes the bit stream. As a result, even if it takes more than one frame time to decode the data for one picture, the occurrence of error concealment is avoided and the moving image can be reproduced smoothly.

  FIG. 4 is a timing chart showing the operation at the display pause of the MPEG video decoder according to the embodiment of the present invention.

  It is assumed that a pause command 27 (see FIG. 1) is output from the host computer to the display control unit 15a from time t5 to time t7.5. At time t5, an image based on picture 1 is displayed on the display device. The decoded frame buffer 13 stores pictures 2 and 3. The image decoding unit 12 is immediately after the decoding of the picture 4 is completed, and the picture 4 is being stored in the decoded frame buffer 13.

  When the pause command 27 is input from the host computer to the display control unit 15a, the display control unit 15a matches the display time stamp (PTS) of the picture stored in the decoded frame buffer 13 with its own reference clock (SCR). However, the display switch 15b is not turned on. Therefore, the data in the display buffer 45c is not updated even at time t6, and the display control unit 15a transmits the picture 1 to the display device 16 again in synchronization with the vertical synchronization signal V-Sync28. As a result, the display device 16 displays the image of the picture 1 again. Further, since the decoded frame buffer 13 stores three pictures, the buffer full notification 24 remains output. Accordingly, the decoding start permission 21 is not output from the decoding control unit 14a, and the image decoding unit 12 interrupts decoding of the next picture.

  When the pause command 27 is canceled at time t7.5, the display control unit 15a outputs a transfer command 29 to the display switch 15b to transfer the picture 2 from the decoding buffer frame 13 to the display buffer 15c. Then, the display control unit 15a transmits the picture 2 to the display device 16 in synchronization with the next frame start vertical synchronization signal V-Sync28. Further, since the storage area of the decoded buffer frame 13 is empty, the buffer full notification 24 is canceled. Thereby, the decoding control unit 14a outputs a decoding start permission 21 to the decoding switch 14b, and the decoding switch 14b outputs a decoding start command 22 to the image decoding unit 12. In response to the decoding start instruction 22, the image decoding unit 12 starts decoding picture 5. In this way, the display pose is realized.

  In the above-described embodiment, the case where decoding is started when a bit stream of one picture or more is transferred to the bit stream buffer 11 is described. However, the condition for starting decoding is limited to this. Not what you want.

  Further, instead of the bit stream transfer notification 25 input from the host computer, when a certain amount of bit stream is accumulated in the bit stream buffer 11, a signal (bit stream accumulation signal) is transmitted from the bit stream 11 to the decoding control unit 14a. May be output. In this case, the decoding control unit 14a receives the bit stream accumulation signal input from the bit stream buffer 11, the decoding completion notification 23 output from the image decoding unit 12, and the buffer full notification 24 output from the decoding frame buffer 13. In response to this, the decoding start permission 21 is output.

(Second Embodiment)
FIG. 5 is a block diagram showing an MPEG video decoder according to the second embodiment of the present invention. The MPEG video decoder according to the present embodiment includes a bit stream input terminal 110, a bit stream buffer 111, an image decoding unit 112, a decoding frame buffer 113, a decoding control unit 114, a display control unit 115, and a status register 116. Yes.

  The bit stream buffer 111 stores the bit stream input from the input terminal 110 and sequentially outputs it to the image decoding unit 112 for each picture. When the decoding start instruction 122 is issued by the decoding control unit 114, the image decoding unit 112 starts decoding the bitstream sent from the bitstream buffer 111. The picture decoded by the image decoding unit 112 is stored in the decoded frame buffer 113.

  The decoded frame buffer 113 has a storage area for three pictures, for example. The storage area is divided into a plurality of banks, and one picture is stored in one bank. In addition, when a display start command 127 is issued by the display control unit 115, the decoded frame buffer 113 transfers the picture at the bank address included in the display start command 127 to the display device.

  The decoding control unit 114 issues a decoding start command 122 to the image decoding unit 112 in synchronization with V-Sync output from a built-in V-Sync generator (not shown). The issuance cycle of the decoding start instruction 122 is basically once every two field times, that is, once every one frame time.

  In addition, when a certain amount of bit stream is stored in the bit stream buffer 111 after power is turned on (after a cold start), the decoding control unit 114 issues an initial decoding start instruction 121 regardless of V-Sync.

  The display control unit 115 includes a V-Sync count counter 115e and a display field number calculation unit 115f in addition to the four registers of the reorder register 115a, the current register 115b, the field delay register 115c, and the display register 115d.

  In the present embodiment, parameters are transferred to the display register 115d as shown in FIG. In this embodiment, since the display control unit 115 needs to determine the number of fields to be displayed for each picture, the repeat first field flag is transferred to the display register 115d. Also, the 1/2 slow playback command flag is transferred as a parameter to the display register 115d. The display control unit 115 samples an external slow playback command 129 using a decoding start command as a trigger, and if the slow playback command 129 is “1”, transfers it to the display register 115d as a slow playback flag.

  The display field number calculation unit 115 f is for managing the number of image fields to be displayed in the display control unit 115. The operation for calculating the number of display fields will be described later. The V-Sync count counter 115e counts V-Sync pulses for the number of fields determined by the display field number calculation unit 115f, and is used for managing the number of fields in the display field number calculation unit 115f.

  The status register 116 monitors the states of the reorder register 115a, the current register 115b, the field delay register 115c, and the display register 115d and expresses them by a 4-bit signal. That is, if data such as parameters and bank addresses are stored in these registers 115a to 115d, the value of the bit corresponding to the register is set to “1”, and if not stored, “0” is set. The order of bits is from MSB (Most Significant Bit) to the reorder / current / field delay / display. For example, if any of the four registers 115a to 115d stores data, the value of the status register 116 is “1111”. If no data is stored in any of the four registers 115a to 115d, the status is stored. The value of the register 116 is “0000”.

  FIG. 7 is a flowchart showing the operation of the decoding control unit 114. First, in step S11, the falling timing of V-Sync generated by the built-in V-Sync generator is detected. Then, the process proceeds to step S12 due to the fall of V-Sync, and it is determined whether or not the picture to be decoded is a B picture. If the picture is not a B picture, that is, if it is an I picture or a P picture, the process proceeds to step S13 to determine whether or not bit 3 of the status register 116 is “1”. When bit 3 is “1”, that is, when data is stored in the reorder register 115a, the process returns from step S13 to step S11. When bit 3 is “0” in step S13, that is, when data is not stored in the reorder register 115a, the process proceeds to step S15 to issue a decoding start instruction, and then returns to step S11. The decoded I picture or P picture parameter is stored in the reorder register 115a.

  On the other hand, if the picture to be decoded in step S12 is a B picture, the process proceeds to step S14 to determine whether bit 2 of the status register 116 is “1”. When bit 2 of the status register 116 is “1”, that is, when data is stored in the current register 115b, the process returns from step S14 to step S11. When bit 2 of the status register 116 is “0” in step S14, that is, when data is not stored in the current register 115b, the process proceeds to step S15 to issue a decoding start instruction, and then returns to step S11. . The parameters of the decoded B picture are stored in the current register 115b.

  FIG. 8 is a flowchart showing the operation of the display control unit 115. In step S21, the falling timing of V-Sync is detected. Then, the process proceeds to step S22 due to the fall of V-Sync, and it is determined whether or not bit 0 of the status register 116 is “1”. When the LSB (Least Significant Bit: bit 0) of the status register 116 is “0”, that is, when data is not stored in the display register 115d, the process returns to step S21.

  On the other hand, when bit 0 of the status register is “1” in step S22, that is, when data is stored in the display register 115d, the process proceeds to step S23 to analyze the data stored in the display register 115d. To do. Then, the process proceeds to step S24, and the number of display fields is determined according to the repeat first field flag and the slow playback command flag. When the number of display fields is determined, the process proceeds to step S25, and a display start instruction 127 is issued.

  Thereafter, the process proceeds to step S26, where the V-Sync count counter 115e starts counting V-Sync. In step S27, the process waits until the V-Sync count value matches the number of display fields. If the V-Sync count value matches the display field count, the process proceeds to step S28 and a display completion notification 128 is issued.

  FIG. 9 is a diagram illustrating a display field number calculation method by the display field calculation unit 115f. As shown in FIG. 9, the display control unit 115 stores a table (lookup table) indicating the relationship between the repeat first field flag, the 1/2 slow playback command flag, and the number of display fields. The display field number calculation unit 115f refers to the table and determines the number of display fields from the state of the repeat first field flag and the 1/2 slow playback flag. For example, when the repeat first field flag and the 1/2 slow playback flag are both “0”, the number of display fields is 2, and when both the repeat first field flag and the 1/2 slow playback flag are “1”, the display is performed. The number of fields is 6.

  10 and 11 are timing charts showing the operation of the MPEG video decoder of this embodiment. However, in this example, a bit stream is input in the order of I picture I2, B picture B0, B picture B1, P picture P5, B picture B3, B picture B4,..., Picture B0, picture B1, picture I2, picture Assume that B3, picture B4, picture P5,... Are displayed in this order. It is assumed that a repeat first field command is added to the B pictures B0, B4 and the I picture I2.

  For example, when the power is turned on at time t0, the decoding control unit 114 issues an initial decoding start instruction 122. Thereby, the image decoding unit 112 decodes the picture header (I2) of the picture I2.

  Next, at time t1, the decoding control unit 114 checks the register data 124a output from the status register 116. At this time, since the value of the status register 116 is “0000”, the decoding control unit 114 issues a decoding start instruction 122, whereby the image decoding unit 112 starts the coefficient decoding of the picture I2, and the coefficient of the picture I2 When the decoding is completed, the picture header (B0) of the picture B0 is continuously decoded.

  The parameter and bank address of the picture I2 are stored in the reorder register 115a. As a result, the value of the status register 116 becomes “1000” (time t1.5).

  Further, at time t2, the decoding control unit 114 checks the register data 124a output from the status register 116. At this time, since the value of the register data 124a is “1000”, the decoding control unit 114 issues the decoding start instruction 112 at a timing synchronized with V-Sync. Thereby, the image decoding unit 112 starts the coefficient decoding of the picture B0. At this time, the display control unit 115 samples the 1/2 slow playback command 128 using the falling edge of the decoding start command 122 as a trigger, and the 1/2 slow playback command 128 is “1”. The slow reproduction flag is set to “1” and stored in the current register 115b. In this example, since the repeat first field command is added to the picture B0, the repeat first field flag is set to “1” and stored in the current register 115b.

  Therefore, in this case, the value of “1” is stored in the current register 115b for both the 1/2 slow playback command flag and the repeat first field flag.

  Since the data of the picture B0 is stored in the current register 115b, the value of the bank status register 116 becomes “1100” (time t2.5).

  Similarly, the decoding control unit 114 checks the value of the bank status register 116 at the fall of V-Sync, and issues a decoding start instruction 122 if there is a register of “0”. When the decoding start command 122 is issued by the decoding control unit 114, the image decoding unit 112 starts coefficient decoding, and continues decoding the picture header of the next picture when coefficient decoding is completed.

  In this way, the picture B1 and the picture P5 are decoded, but the value of the bank status register 116 becomes “1111” at the time t5. Therefore, the decryption control unit 114 stops issuing the decryption start instruction 122. Thereby, the image decoding unit 112 pauses decoding.

  On the other hand, the fact that the bank status register 116 is “1111” means that there is a picture to be displayed in the display register 115d, and therefore the display control unit 115 analyzes the parameters of the display register 115d. As a result, since the repeat first field flag and the 1/2 slow playback flag are both “1”, the display field number calculation unit 115f sets the display field number to 6 (see FIG. 9). Then, the display control unit 115 issues a display start instruction 127 at time t5.5. Thereby, the picture B0 is transferred to the display device, and the display of the picture B0 is started. Thereafter, the display control unit 115 counts V-Sync pulses five times to display six fields, and issues a display completion notification 128 to the status register 116 when the time for six field periods has elapsed. Then, the display control unit 115 shifts the contents of the current register 115b and the field delay register 115c to the field delay register 115c and the display register 115d, respectively. As a result, a space is generated in the current register 115b, and the value of the status register 116 becomes “1011” (time t5.9).

  The decoding control unit 114 checks the value of the status register 116 at time t6, and since it is “1011”, it issues a decoding start command. Thereby, the image decoding unit 112 starts the coefficient decoding of the picture B3. The parameter of the picture B3 is stored in the current register 115b. As a result, the value of the status register 116 becomes “1111”.

  Further, the display control unit 115 examines the parameter of the picture B1 transferred to the display register 115d, and the repeat first field flag is “0” and the 1/2 slow playback command flag is “1”. 4. Then, the display start instruction 127 is issued, and the display of the picture B1 is started (time t6.5). When the display period of the picture B1 ends, the display control unit 115 issues a display completion notification 128 and shifts the data in the current register 115b and the field delay register 115c to the field delay register 115c and the display register 115d.

  In this way, the MPEG video decoder according to the present embodiment correctly executes 3-2 pulldown and 1/2 slow playback. As described above, the display control unit 115 has conventionally determined the number of display fields, whereas in the present embodiment, the display control unit 115 uses the table shown in FIG. decide. Accordingly, special playback such as 3-2 pull-down playback, 1/2 slow playback, 3-3 pull-down playback and 1/2 slow playback can be supported.

  A PTS (Presentation Time Stamp) is superimposed on each MPEG picture. The PTS is data indicating the time for displaying the picture. In general, an MPEG video decoder performs playback time management using a PTS and an STC (System Time Clock) inside the decoder.

  FIG. 12 is a diagram showing time-dependent changes in STC during normal playback and special playback (3-2 pull-down playback and 1/2 through playback), with time on the horizontal axis and STC on the vertical axis. As shown in FIG. 12, the STC normally increases monotonically with time. If the slope of the STC increase during normal playback (normal play) is 1, the slope is 2/3 during 3-2 pull-down playback, and the slope 1/2 and 3-2 pull-down during 1/2 slow playback. And at 1/2 slow playback, it must be 1/3.

  However, in the conventional decoder, 3-2 pull-down and 1/2 slow playback becomes 1/2 slow playback, so that the STC increase amount is larger than the original by ΔSTC. Therefore, when 1/2 slow playback is canceled at time t and 3-2 pull-down and 1/2 "slow playback is switched to 3-2 pull-down playback, subtract ΔSTC or use a new PTS. It was necessary to forcibly correct the STC. In the present embodiment, it is not necessary to correct the STC when returning from slow playback to normal playback, and an extra process of correcting the STC when the playback speed is returned is unnecessary.

  In the above example, only the case of 1/2 slow playback has been described. However, for example, the number of display fields is determined using a table showing the relationship between the repeat first field flag and slow playback command flag and the number of display fields shown in FIG. By determining, 3-2 pull-down playback, 1/2 slow playback, 1/3 slow playback, 1/4 slow playback, and 1/8 slow playback are possible.

  In the above embodiment, the picture is decoded in synchronization with V-Sync. However, it is not necessary to synchronize with V-Sync as shown in the first embodiment.

FIG. 1 is a block diagram showing an MPEG video decoder according to the first embodiment of the present invention. FIG. 2 is a timing chart showing the operation of the MPEG video decoder according to the first embodiment of the present invention. FIG. 3 shows that error concealment easily occurs between the MPEG video decoder that starts decoding of a bit stream in synchronization with the vertical synchronization signal V-Sync and the MPEG video decoder according to the first embodiment of the present invention. It is a figure for comparing. FIG. 4 is a timing chart showing the operation at the display pause of the MPEG video decoder according to the first embodiment of the present invention. FIG. 5 is a block diagram showing an MPEG video decoder according to the second embodiment of the present invention. FIG. 6 is a block diagram illustrating a display control unit according to the second embodiment of the present invention. FIG. 7 is a flowchart illustrating the operation of the decoding control unit according to the second embodiment of this invention. FIG. 8 is a flowchart showing the operation of the display control unit according to the second embodiment of the present invention. FIG. 9 is a diagram illustrating a display field number calculation method according to the second embodiment of this invention. FIG. 10 is a timing chart (part 1) showing the operation of the MPEG video decoder according to the second embodiment of the present invention. FIG. 11 is a timing chart (part 2) showing the operation of the MPEG video decoder according to the second embodiment of the present invention. FIG. 12 is a diagram showing a change with time of STC during normal reproduction and special reproduction (3-2 pull-down reproduction and 1/2 through reproduction). FIG. 13 is a diagram showing a table for realizing 3-2 pull-down playback, 1/2 slow playback, 1/3 slow playback, 1/4 slow playback, and 1/8 slow playback. FIG. 14 is a schematic diagram showing the structure of an MPEG bit stream. FIG. 15 is a block diagram showing an MPEG video encoder. FIG. 16 is a block diagram showing a conventional MPEG video decoder (part 1). FIG. 17 is a schematic diagram showing telecine conversion by 3-2 pull-down. FIG. 18 is a block diagram showing a conventional MPEG video decoder (part 2). FIG. 19 is a block diagram showing the configuration of the display control unit of the MPEG video decoder of FIG. FIG. 20 is a timing chart (part 1) showing the operation of the MPEG video decoder of FIG. FIG. 21 is a timing chart (part 2) showing the operation of the MPEG video decoder of FIG. FIG. 22 is a timing chart (part 1) showing the operation when 3-2 pull-down playback and 1/2 through playback are executed by the MPEG video decoder of FIG. FIG. 23 is a timing chart (part 2) showing the operation when 3-2 pull-down playback and 1/2 through playback are executed in the MPEG video decoder of FIG.

Explanation of symbols

10, 60, 110, 160 ... input terminals,
11, 61, 111, 161... Bitstream buffer,
12, 62, 112, 162 ... image decoding unit,
13, 63, 113, 163 ... decoded frame buffer,
14: Decoding start command generation unit,
14a ... Decoding control unit,
14b, 64 ... Decoding switch,
15, 65 ... picture data output unit,
15a, 65a ... display control unit,
15b, 65b ... display switches,
15c, 65c ... display buffer,
16, 66 ... display device,
21 ... Decryption start permission,
22, 72 ... Decryption start instruction,
23: Decoding completion notification,
24 ... Buffer full notification,
25 ... Bitstream transfer notification,
26, 76 ... display time stamp (PTS),
27 ... Pause command,
28, 71 ... vertical synchronization signal V-Sync,
29, 73 ... Transfer command,
31 ... Sequence header,
32 ... GOP header,
33 ... Picture header,
34. Picture data,
35 ... Sequence end code,
41 ... Picture rearrangement unit,
42 ... a motion estimation unit,
43, 51 ... adder,
44. Discrete cosine transform unit (DCT),
45. Quantization unit,
46: Variable length encoding unit,
47. Multiplexer,
49. Inverse quantization unit,
50. Inverse discrete cosine transform unit (IDCT),
52. Picture storage unit,
53. Motion prediction unit,
114,164 ... Decoding control unit,
115,165 ... display control unit,
115a, 165a ... reorder register,
115b, 165b ... current register,
115c, 165c ... field delay register,
115d, 165d ... display register,
115e ... V-Sync counter,
115f: Display field number calculation section,
116: Status register.

Claims (12)

  1. An image decoding unit that starts decoding of the MPEG bitstream in response to a decoding start instruction;
    A decoded frame buffer for storing the picture data decoded by the image decoding unit;
    A display control unit that analyzes a parameter of picture data decoded by the image decoding unit for each predetermined picture, and controls transfer of the picture data from the decoded frame buffer to a display device according to a result thereof; ,
    An MPEG video decoder, comprising: a decoding control unit that outputs the decoding start command based on the parameter of the picture data.
  2.   The display control unit determines the number of display fields of the picture for each predetermined picture from the parameters, and causes the display device to display the picture for a time corresponding to the number of display fields. MPEG video decoder as described in 1.
  3.   3. The MPEG video decoder according to claim 2, wherein the parameter of the picture data includes a special reproduction flag.
  4.   3. The MPEG video decoder according to claim 2, wherein the display control unit stores a table indicating a relationship between the parameter of the picture data and the number of display fields.
  5.   The display control unit includes a reorder register that stores parameters and bank addresses of I pictures or P pictures, a current register that stores parameters and bank addresses of pictures to be displayed next, and parameters and banks shifted from the current registers. 3. The MPEG video decoding according to claim 2, comprising four shift registers: a field delay register for delaying an address by one field time, and a display register for storing a parameter and a bank address of a picture currently being displayed. vessel.
  6.   6. The MPEG video decoder according to claim 5, wherein the reorder register and the current register use the decoding start command as a shift pulse, and the field delay register and the display register use a vertical synchronization signal as a shift pulse.
  7.   6. The MPEG video decoder according to claim 5, further comprising a status register indicating a status of the reorder register, the current register, the field delay register, and the display register.
  8.   8. The MPEG according to claim 7, wherein the decoding control unit issues the decoding start command when data is not stored in the reorder register or the current register with reference to a status of the status register. Video decoder.
  9.   9. The MPEG video decoder according to claim 8, wherein the decoding control unit refers to the status register at a timing synchronized with a vertical synchronizing signal.
  10.   8. The display control unit according to claim 7, wherein the display control unit determines the number of display fields from the parameter when a parameter and a bank address are stored in the display register with reference to a status of the status register. MPEG video decoder.
  11.   11. The MPEG video decoder according to claim 10, wherein the display control unit refers to the status register at a timing synchronized with a vertical synchronization signal.
  12. The decoding of the MPEG bit stream is started by a decoding start command output from the decoding control unit,
    Store the decoded picture data in the decoded frame buffer,
    The decoded picture data parameters are stored in a display control unit, the display control unit determines the number of display fields for each picture from the parameters, and each picture is displayed on the display device for a time corresponding to the number of display fields An MPEG video decoding method characterized by:
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