JPH1093461A - Receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the receiver with an excellent intermodulation distortion characteristic, a small circuit scale and less current consumption. SOLUTION: A digital signal processing section 6 demodulates a desired signal to decode required transmission information and detects a secondary intermodulation distortion component in existence at the outside of a desired signal band included in an input signal and generators an intermodulation distortion control signal based on the amplitude of the detected secondary intermodulation distortion. The intermodulation distortion control signal is given to a frequency conversion section 3 and an intermodulation distortion control means 7 controls the intermodulation of the frequency control section 3. That is, the receiver with less sensitivity deterioration due to a string input of adjacent channels is provided by generating the intermodulation distortion control signal to generate the intermodulation distortion control signal to minimize the secondary intermodulation distortion in the digital signal processing section 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver used for wireless communication, and more particularly to a receiver capable of avoiding sensitivity degradation due to secondary intermodulation distortion.

[0002]

2. Description of the Related Art Asad. A. Abidi, "Low-
Power Radio-Frequency IC '
s for Portable Communicat
ions ”(procedings of IEEE
Vol. 83, no. 4, April 1995)
, The direct conversion (Direct-Con
version or zero-IF) is a method suitable for miniaturization of radio receivers and integration into integrated circuits.
In the case of a modulation method involving amplitude modulation such as shift QPSK, there is a problem unique to the direct conversion reception method. That is, if there is a strong signal at a frequency different from the desired signal frequency, secondary intermodulation distortion of the signal is generated in the desired signal frequency range and becomes an interference signal. This secondary intermodulation distortion not only degrades the error rate when the desired signal is weak, but also causes the receiver to use an originally unused channel when searching for a free channel at the start of communication. There is a problem that communication cannot be started by erroneously judging.

In order to solve such a problem, the present inventors generate a test signal inside a receiver, detect secondary intermodulation distortion in a frequency converter, and use the frequency converter based on the detected signal. (Japanese Patent Application No. 6-137614).

[0004]

However, in a radio device configured to generate a test signal as described above,
There are the following problems.

[0005] First, the radio itself requires test signal generating means. In particular, in order to detect the non-linearity of the frequency conversion means, it is necessary to generate a test signal with less noise and less distortion, which increases the circuit scale and the current consumption. One of the reasons for employing the direct conversion method is that it is suitable for miniaturization, so it is not desirable to have a test signal generating means that increases the circuit scale and current consumption. Further, even when a part of the transmitter is used as the test signal generator, if the signal purity required for the test signal generator is more severe than the signal purity required for the transmitter, the circuit scale increases. And increase in current consumption is unavoidable.

Second, the above technique is applicable to a time division multiple access (TDＴA) system or a time division duplex (TDD) system, but cannot be applied to a frequency division system (FDMA or the like). is there. This is because it is necessary to separate the receiver from the antenna and to input a test signal, so that it can be applied only to a method in which there is a time when no signal is received.

The present invention has been made in view of such circumstances, and has as its object to provide a receiver having excellent intermodulation distortion characteristics and a small circuit scale and small current consumption.

Another object of the present invention is to provide a receiver capable of detecting secondary intermodulation distortion even in a system having no time during which no signal is received, such as a frequency division system.

[0009]

In order to solve the above-mentioned problems, a receiver of the present invention suppresses intermodulation distortion according to a control signal and converts a high-frequency signal with amplitude modulation into a low-frequency signal. Conversion means, analog-digital conversion means for converting the low-frequency signal into a digital signal,
Signal processing means for restoring information based on the digital signal and detecting the intermodulation distortion component to generate the control signal. The signal processing means may include means for detecting a clock frequency component included in the digital signal, and means for generating the control signal so that the amplitude of the clock frequency component is reduced, A control signal holding unit for holding the control signal may be further provided, and the control signal holding unit may intermittently detect the intermodulation distortion component while holding the control signal. Further, when used for time division multiplex communication, the signal processing means detects an intermodulation distortion component during reception, generates and holds the control signal, and controls the control signal held after the end of a reception slot. May be configured to be updated. Further, the signal processing means may be configured to stop the detection of the intermodulation distortion when the amplitude of the desired signal is larger than a predetermined value, and the operation clock frequency supplied to the signal processing unit is equal to the code clock frequency. In an integer multiple receiver, the signal processing section may include a clock frequency dividing means, and may stop the output of the code clock frequency of the clock frequency dividing means during the detection of the intermodulation distortion. Further, the frequency conversion means may include a harmonic mixer.

In wireless communication, a frequency band corresponding to the amount of information is required for transmitting information. If a signal having a frequency band of ± 10 kHz around the carrier frequency fc is input to the frequency converter, the second-order intermodulation distortion component is distributed between DC and 20 kHz. −
On the other hand, the desired signal output of the direct conversion system is 10 kHz from DC.
Shall exist between

When a radio signal having a signal frequency band of 20 kHz is used, the channel interval is set wider than 20 kHz. This is because a guard band is provided so that an adjacent channel and a desired signal can be separated by a feasible filter instead of an ideal filter that cannot be realized. Therefore, it is possible to determine the magnitude of the second-order intermodulation distortion by detecting a signal component existing in the guard band with a narrow-band filter. Such a narrow-band filter is difficult to realize as an analog circuit in terms of accuracy, but can be relatively easily realized as a digital circuit. In the present invention, it is particularly convenient to apply to a digital signal transmission system. This is because, in the digital signal transmission system, since the code clock frequency component appears strongly in the secondary intermodulation distortion, it is easy to detect this.

An amplitude / phase modulated signal including a π / 4 shift QPSK can be generally expressed by the following equation.

Ι (t) cos (ωt) -Q (t) sin (ωt) (Equation 1) Here, the second-order distortion is 2α ｛I (t) cos (ωt) -Q (t) sin (ωt )｝ ² = α ｛Ι ² (t) + Q ² (t)｝ + α ｛Ι ² (t) -Q ² (t)｝ cos (2ωt) − {αΙ (t) Q (t) sin (2ωt)｝ / 2 (Equation 2). Here, α is a coefficient determined by the circuit.

The second-order intermodulation distortion in question is the first term on the right side of Equation 2.

FIG. 14 shows "ΤDM" by Heiichi Yamamoto and Shuzo Kato.
A-Communication "(The Institute of Electronics, Information and Communication Engineers, 1989, p. 86)
It is a block diagram which shows the structure of the "clock recovery circuit" of description. In the circuit shown in the figure, the first term on the right side of Equation 2 is generated from the input signal using the demodulator 100 and the squaring circuits 101 and 102, and the result synthesized by the synthesizer 103 is subjected to only a clock component by the single tuning filter 104. Take out, limiter 1
The reproduced clock is output via the 05 and divide-by-2 circuits 106.

FIG. 15 shows the spectrum of 変 調² (t) + Q ² (t), the secondary intermodulation distortion of the π / 4 shifted QPSK signal obtained by computer simulation.
The horizontal axis is the frequency normalized by the code clock frequency. It can be seen that the peak is at the frequency "1", that is, the clock signal clearly appears (FIG. 15).

On the other hand, the spectrum of the desired signal is distributed in a portion lower than the clock frequency as shown in FIG. Therefore, the clock component included in the second-order intermodulation distortion can be separated from the desired signal by the filter. In particular, for example, in a system such as a PHS that does not use an adjacent channel but uses a channel farther from the next adjacent channel, there is no extraneous signal near the clock frequency. Therefore, the secondary intermodulation distortion level can be estimated by detecting the signal level of the clock frequency, and can be used for controlling the frequency converter.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a radio receiver according to one embodiment of the present invention. From the signal input from the receiving antenna 1, a signal in a frequency range including a desired signal is selectively amplified in the high-frequency signal processing unit 2. The amplified signal includes a signal of another channel in addition to a desired signal.

The output of the high frequency processing unit 2 is
And converted to a lower frequency. At this time, if the signal amplitude of the other channels is large, distortion occurs. In particular, as in the direct conversion method, the received signal is orthogonalized with the baseband in-phase (In phase) component by orthogonal demodulation.
When converting to a (quadrature-phase) component, secondary intermodulation distortion becomes a problem. This is because the frequency of the second-order intermodulation distortion has the same frequency component as that of the desired signal after frequency conversion, so that when a weak desired signal is received, it becomes an interference signal. However, the secondary intermodulation distortion is distributed in a frequency range wider than the band of the desired signal.

The output signal of the frequency converter 3 is input to the low-frequency signal processor 4. The low-frequency signal processing unit 4 suppresses unnecessary frequency components and amplifies a desired signal to an amplitude required by the analog-digital converter 5. At this time, the secondary intermodulation distortion is also amplified and output.

The output of the low frequency signal processing section 4 is an analog signal.
The digital signal is input to the digital converter 5 and converted into a digital signal.

The output of the analog-to-digital converter is input to the digital signal processor 6. The digital signal processing unit 6 demodulates the desired signal to restore necessary transmission information, detects a secondary intermodulation distortion component outside the desired signal band included in the input signal, and detects the detected secondary intermodulation component. An intermodulation distortion control signal is generated based on the distortion amplitude.
The intermodulation distortion control signal is input to the frequency conversion unit 3,
Intermodulation of the frequency conversion unit 3 is controlled by the intermodulation distortion control means 7. That is, by generating an intermodulation distortion control signal so that the secondary intermodulation distortion in the digital signal processing unit 6 is minimized, it is possible to provide a radio receiver with less sensitivity deterioration due to strong input of an adjacent channel.

FIG. 2 is a diagram showing a more specific configuration of the digital signal processing section 6 shown in FIG. In a method of converting a high-frequency reception signal into a baseband signal and demodulating it, such as a direct conversion method, the digital signal processing unit 6 applies an in-phase (Ιn Phase) input and a quadrature (Quo)
The input of a "phase phase" is input. These are not independent signals, but represent the amplitude and phase information of the received signal with both in-phase and quadrature inputs.

The signal input to the digital signal processing section 6 is input to low-pass filters 8 and 9 and single-tuned filters 10 and 11, respectively.

The low-pass filters 8 and 9 suppress signal components other than the desired wave. If a filter having a roll-off or root roll-off characteristic is required on the receiving side, the low-pass filters 8 and 9 in the drawing may be root roll-off filters. Outputs of the low-pass filters 8 and 9 are input to a demodulation circuit 12. The demodulation circuit 12 transmits the transmission information to the PC
It restores and outputs the M signal and the communication control signal.

On the other hand, since the single tuning filters 10 and 11 are tuned to the code clock frequency, the clock components of the secondary intermodulation distortion can be detected. Particularly, in the PHS, since a base station having a short physical distance does not use an adjacent channel on the frequency axis, no signal exists at a code clock frequency of 192 kHz. Therefore, secondary intermodulation distortion can be detected efficiently. Single tuning filter 1
The secondary intermodulation distortion can be detected by tuning 0 and 11 to the guard band.

The signals detected by the single tuning filters 10 and 11 are input to control signal generating means 13 and 14, respectively. The control signal generation means 13 and 14 detect the detected 2
An intermodulation distortion control signal is generated according to the next intermodulation distortion component. The intermodulation distortion control signal is fed back to the mutual distortion control means 7.

The control signal generating means 13 and 14 adjust the intermodulation distortion control signal to a value that minimizes the secondary intermodulation distortion. FIG. 3 is a flowchart showing an example of the operation of the control signal generation means 13 and 14.

First, the value of the intermodulation distortion control signal is set to the maximum (step 301). Next, it is determined whether or not the outputs of the single tuning filters 10 and 11 are larger than a specified value (step 302). If the value is larger than the specified value, the magnitude of the output of the single tuning filter is recorded (step 303), and the value of the intermodulation distortion control signal is reduced by one step (step 304). It is determined whether the value is smaller than the value recorded before (step 305). The above operation is repeated until the output of the single tuning filter becomes larger than the previously recorded value (steps 301 to 305). When the output of the single tuning filter becomes larger than the value recorded before, the value of the intermodulation distortion control signal is increased by one step (step 306). It is the value of the distortion control signal. When the intermodulation distortion control signal has reached the minimum value in steps 301 to 305 (step 307) or in step 302
When the output of the single tuning filter is equal to or less than the specified value, the value is regarded as the value of the intermodulation distortion control signal for minimizing the secondary intermodulation distortion.

FIG. 4 is a diagram showing a more specific configuration of the mutual distortion control means 7 and the frequency converter 3. Frequency converter 3
Are I-channel and Q-channel high-frequency mixers 15, 16
, A local oscillator 17 and a transfer unit 18, and the mutual distortion control means 7 has D / A converters 19 and 20. I
The intermodulation distortion control signals of the channel and the Q channel are supplied to mixers 15 and 16 via D / A converters 19 and 20, respectively.
Is input to The analog-converted intermodulation distortion control signal varies the parameters of the mixers 15 and 16 to reduce secondary intermodulation distortion. FIG. 5 shows a specific configuration of the mixers 15 and 16. The variable parameters for reducing the second-order intermodulation distortion include the phase 21 of the local balanced input portion, the value of the load resistor 22, and the difference between the mixers. Dynamic pair 23, 2
4 bias voltage and the like.

FIG. 6 shows the single tuned filters 10 and 11 and the control signal generators 13 and 14 in the digital signal processor 6.
FIG. 9 is a diagram illustrating another configuration example. In the case of the time-division multiple access system such as the Japanese @HS, both the desired signal and the signals of other channels are in a burst form. For this reason, the intermodulation also has a burst shape. Only the secondary intermodulation occurring in the time slot to be received interferes with the reception, so that it may be detected. Therefore, as shown in FIG.
And an operation / pause control signal for giving an instruction of operation / pause to the control signal generating means 13 and 14, and an output holding means 25. By using the value held at the start of the operation as an initial value, feedback is promptly performed. The system can be stabilized. The operation / pause control signal may be input from a control unit (not shown) that controls the entire apparatus.

When the level fluctuation of a signal causing secondary intermodulation is sufficiently slow, it is not necessary to detect intermodulation distortion for each burst. For example, it may be sufficient to detect once every ten bursts. . In such a system, the frequency conversion unit 3 can be operated stably by outputting the holding signal of the output holding unit 25 while the detection unit is at rest.

FIG. 7 is a diagram showing another example of the configuration of the digital signal processor 6. Transmission signals are often transmitted with third-order intermodulation distortion. This third-order intermodulation distortion is also distributed near the clock frequency. Therefore, when the desired signal is strong, the third-order intermodulation distortion generated on the transmission side may be stronger than the second-order intermodulation distortion generated on the reception side. In this case, what is detected by the single tuning filters 10 and 11 is distortion generated on the transmission side, and it is inappropriate to control the receiver based on this signal. The digital signal processing unit 6 includes an RSSI (received signal strength detecting means) 26,
When the detected signal amplitude is larger than a predetermined level, the operation of the single tuned filters 10 and 11 and the control signal generating means 13 and 14 is stopped to prevent malfunction due to distortion generated on the transmission side. Can be. In this case, since the desired signal amplitude is large, even if the secondary distortion of the signal of the other channel occurs, it has little effect.

FIG. 8 is a diagram showing still another example of the configuration of the digital signal processing section 6. In FIG. As an operation clock of the digital signal processing unit 6, a clock signal having a frequency that is an integral multiple of the code clock frequency is input. Each digital circuit operates based on this operation clock. For example, since the low-pass filters 8 and 9 handle a signal of about 8 samples during one code period, a clock having a frequency eight times the code clock frequency is supplied. There is a need to. On the other hand, the demodulation circuit 12 only needs to operate at the code clock frequency. Therefore, the clock frequency required by each circuit block of the digital signal processing unit 6 is different. For this reason, the reference operation clock signal is frequency-divided using the frequency dividing circuit 27, and a clock signal required by each block is supplied. The communication device for transmitting digital signals includes a CPU 28 for controlling communication. One of the important functions in communication control is to search for an empty channel. If the received signal level is lower than a predetermined signal level, it is determined that the channel is available. However, if the second-order intermodulation distortion of another channel is detected, the receiver may erroneously determine that the channel is in use. In the present invention, in order to prevent this, secondary intermodulation distortion is detected,
The frequency converter is controlled so as to reduce the second-order distortion. However, if there is a part operating at the clock frequency inside the receiver to detect the clock signal, the clock leaks to the analog-to-digital converter 5. As a result, the detection accuracy may be deteriorated. In order to prevent this, by stopping the output of the code clock frequency of the frequency dividing circuit 27, the secondary intermodulation distortion can be detected accurately.
At this time, since a portion for measuring the signal strength of the desired signal such as RSS # 26 needs to operate, a clock having a higher frequency than the code clock needs to be supplied to a portion operating when searching for an empty channel. As a result, reliable empty channel search can be performed. When it is necessary to receive a particularly weak signal, the supply of the code clock frequency is temporarily stopped to set the intermodulation distortion control signal to an optimal value, and then the original reception and demodulation are performed. Even a weak signal can be received without being disturbed by intermodulation.

FIG. 9 is a configuration diagram of a receiver according to another embodiment of the present invention. The use of the even harmonic frequency converters 29 and 30 in the frequency conversion unit can avoid local signal leakage and self-mixing of local signals, which are problems in direct conversion receivers. "Even-Order Mixing Characteristics of Converter Even Harmonic Mixer" (1995 IEICE General Conference, Lecture No. C-9). An even harmonic frequency converter using a transistor differential pair can be configured as shown in FIG. 10, for example. That is, in the converter shown in FIG. 3, a desired frequency signal can be obtained from the output terminal 154 by inputting RF from the input terminals 151 and 152 and RF inverted from the input terminal 153. These frequency converters can also reduce second-order intermodulation distortion by controlling the amplitude, phase, and bias of the input signal, as in the case shown in FIG. Since the even harmonic frequency converters 29 and 30 have properties suitable for a direct conversion receiver as described above, by applying the second-order intermodulation distortion control method of the present invention, a direct sensitivity with less sensitivity deterioration due to distortion can be obtained. A conversion receiver can be realized.

FIG. 11 is a diagram showing a configuration of an intermodulation distortion detecting means according to another embodiment of the present invention. The receiver has a code clock generation circuit (not shown) for code reproduction. This clock signal is synchronized with the code clock of the desired received signal. On the other hand, the code clock component detected as the intermodulation distortion is the code clock of the wireless station using another channel. If the transmitting station is different, the code clock frequency is slightly shifted due to an error. The output of the single-tuned filter is a mixture of a signal detected by leaking the code clock generated by the receiver itself into the analog section (referred to as clock S) and a clock (referred to as clock I) generated due to intermodulation distortion. It has become.
When this is multiplied by the clock of the receiver, the clock S is converted to DC, but the clock I is converted to the frequency of the error. Both signals can be separated by a filter. FIG.
In the intermodulation distortion detecting means 31 shown in FIG. 1, only the clock I is taken out by the high-pass filter (HPF) 33 and inputted to the control signal generating means 13 and 14. The single tuned filters 10 and 11 and the clock multiplication circuit 32 can be realized as an analog circuit. However, when realized as a digital circuit, only the sign bit of the output signal of the single tuned filters 10 and 11 is inverted according to the clock. And specifically, it can be realized only by an exclusive OR circuit.

FIG. 12 is a block diagram of an intermodulation distortion detecting means according to still another embodiment of the present invention. In the intermodulation distortion detecting means 31 shown in FIG. 11, signal components other than the code clock are first removed by the single-tuned filters 10 and 11. However, since a filter is required for the output of the multiplying circuit 32, the frequency selecting function is provided by this bandpass. Filter (BP
F) 34.

Although the configuration of the receiver has been described in the above embodiments, the present invention is naturally applicable to a transceiver such as a PHS. FIG. 13 shows an example in which the present invention is applied to a transceiver. The signal input from the antenna 35 is transmitted to the high-frequency signal processing unit 36, the frequency converter 37a of the frequency conversion unit 37, and the low-frequency signal processing unit 3
8, input to the digital signal processor 40 via the analog-digital converter 39. On the other hand, the output of the digital signal processing unit 40 is
1. The signal is output as a radio wave from the antenna 35 via the low-frequency signal processing unit 42, the modulator 37b of the frequency conversion unit 37, and the power amplifier 43. In the frequency converter 37, the local oscillator 37c supplies a local oscillation signal to the frequency converter 37a and the modulator 37b, and the intermodulation distortion control means 3
7d is a frequency converter 37a based on the intermodulation distortion control signal.
Are controlled. The digital signal processing unit 40 includes, for example, a single tuning filter and a control signal generation unit as shown in FIG.
d is supplied with an intermodulation distortion control signal.

[0040]

As described in detail above, according to the present invention,
Frequency conversion means for converting a high-frequency signal with amplitude modulation to a low-frequency signal while suppressing intermodulation distortion in accordance with a control signal; analog-to-digital conversion means for converting the low-frequency signal to a digital signal; Signal processing means for restoring information based on the signal and detecting the intermodulation distortion component to generate the control signal, so that the secondary intermodulation distortion in the frequency converter can be reduced without using the test signal generation means. This makes it possible to provide a receiver having excellent intermodulation distortion characteristics and a small circuit size and low current consumption. In addition, it is possible to detect the secondary intermodulation distortion even in a method such as a frequency division method in which there is no time during which no signal is received.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a wireless receiver according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a more specific configuration of a digital signal processing unit illustrated in FIG. 1;

FIG. 3 is a flowchart illustrating an example of an operation of a control signal generation unit illustrated in FIG. 2;

FIG. 4 is a diagram showing a more specific configuration of a mutual distortion control unit and a frequency conversion unit shown in FIG. 1;

5 is a diagram showing a specific configuration of the high-frequency mixer shown in FIG.

FIG. 6 is a diagram illustrating another example of the configuration of the single tuning filter and the control signal generation unit in the digital signal processing unit illustrated in FIG. 1;

FIG. 7 is a diagram illustrating another configuration example of the digital signal processing unit illustrated in FIG. 1;

8 is a diagram illustrating still another example of the configuration of the digital signal processing unit illustrated in FIG. 1;

FIG. 9 is a configuration diagram of a receiver according to another embodiment of the present invention.

FIG. 10 is a configuration diagram of an even harmonic frequency converter using a transistor differential pair.

FIG. 11 is a diagram showing a configuration of an intermodulation distortion detection unit according to another embodiment of the present invention.

FIG. 12 is a configuration diagram of an intermodulation distortion detection unit according to still another embodiment of the present invention.

FIG. 13 is a diagram showing an example in which the present invention is applied to a transceiver.

FIG. 14 is a block diagram illustrating a configuration of a conventional clock recovery circuit.

FIG. 15 shows π / obtained by computer simulation.
FIG. 3 is a diagram illustrating a spectrum of a secondary intermodulation distortion of a 4-shift QPSK signal.

FIG. 16 is a diagram showing a spectrum of a desired signal obtained by computer simulation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Receiving antenna 2 High frequency processing part 3 Frequency conversion part 4 Low frequency signal processing part 5 Analog-digital conversion part 6 Digital signal processing part 7 Intermodulation distortion control means 8, 9 Low-pass filter 10, 11 Single tuning filter 12 Demodulation circuit 13, 14 control signal generating means

Claims (7)

[Claims] 1. A frequency conversion means for converting a high-frequency signal with amplitude modulation into a low-frequency signal while suppressing intermodulation distortion according to a control signal, and an analog-to-digital converter for converting the low-frequency signal into a digital signal.
A receiver comprising: digital conversion means; and signal processing means for restoring information based on the digital signal and detecting an intermodulation distortion component to generate the control signal. 2. The receiver according to claim 1, wherein the signal processing unit detects a clock frequency component included in the digital signal, and the control unit controls the amplitude of the clock frequency component to be small. Means for generating a signal. 3. The receiver according to claim 1, wherein said signal processing means further comprises control signal holding means for holding said control signal, and wherein said control signal holding means holds said control signal. A receiver for intermittently detecting the intermodulation distortion component. 4. The receiver according to claim 3, wherein the receiver is used for time-division multiplex communication, wherein the signal processing unit detects an intermodulation distortion component during reception and generates and holds the control signal. And updating the control signal held after the end of the reception slot. 5. The receiver according to claim 1, wherein the signal processing unit stops detecting the intermodulation distortion when the amplitude of the desired signal is larger than a predetermined value. 6. The receiver according to claim 1, wherein an operation clock frequency supplied to the signal processing unit is an integral multiple of a code clock frequency, wherein the signal processing unit includes a clock frequency dividing unit,
A receiver for stopping output of a code clock frequency of a clock frequency dividing unit during detection of intermodulation distortion. 7. The receiver according to claim 1, wherein the frequency conversion means includes a harmonic mixer.