JPH1093084A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent reduction in a latch-up immunity of an insulated-gate bipolar transistor(IGBT) caused by a temperature increase during operation thereof, while avoiding increase in its on voltage. SOLUTION: Only a cell in the vicinity of an emitter pad 102 having a great current concentration is made to have an intermittent emitter structure 110. The intermittent emitter structure is applied to the vicinity of the emitter pad having the greatest drop of latch-up immunity. Thereby, the latch-up immunity is improved. Further, since the intermittent emitter structure is not applied to the other regions, the on voltage will not be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a voltage-controlled power semiconductor device such as a power field effect transistor or an insulated gate bipolar transistor.

[0002]

2. Description of the Related Art In recent years, a power field effect transistor (hereinafter, referred to as a voltage-controlled element) has been replaced by a current-controlled element such as a bipolar transistor or a GTO thyristor.
MOSFETs and insulated gate bipolar transistors (hereinafter referred to as IGBTs) have been widely used. Voltage-controlled devices are rapidly replacing current-controlled devices because they are easy to drive and can operate at high speeds. Among them, IGBTs are being actively developed as new switching elements having both the high power controllability of bipolar transistors and the high-speed operation of MOSFETs.

FIG. 2 shows a sectional structure of an IGBT. IGB
T denotes a p-type collector layer 201 having a high impurity concentration, an n-type drift layer 202 having a low impurity concentration, and a p-type base layer 20.
3, formed from an n-type emitter layer 204 having a high impurity concentration, a gate insulating film 205, a gate electrode 210, an emitter electrode 211, and a collector electrode 212.

FIG. 3 shows an equivalent circuit of the IGBT. In FIG. 3, reference numeral 301 denotes the gate electrode 210 and the drift layer 20.
2, formed from base layer 203 and emitter layer 204
The MOSFET 302 has a collector layer 201 and a drift layer 20.
2, a pnp transistor formed from the base layer 203 (hereinafter referred to as TR1), and 303 is a drift layer 20.
2, an npn transistor formed of the base layer 203 and the emitter layer 204 (hereinafter referred to as TR2);
Reference numeral 4 denotes a lateral resistance (hereinafter referred to as Rb) of a portion of the base layer 203 below the emitter layer 204.

Next, the operation of the IGBT will be described with reference to FIGS. When a positive voltage is applied to the collector electrode 212 and the gate electrode 210 with respect to the emitter electrode 211, a channel region is formed on the surface of the base layer 203 where the gate electrode 210 is formed via the gate insulating film 205, MOSFET 301 turns on. When the MOSFET 301 is turned on, an electron current Ie1 flows from the emitter layer 204 to the drift layer 202 through the MOSFET 301. Electron current Ie
1 supplies the base current of TR1 and turns on TR1. When TR1 is turned on, hole current Ih flows from collector electrode 212 to emitter electrode 211. The hole current Ih and the electron current Ie1 become the conduction current of the IGBT.

When turning off the IGBT, the potential of the gate electrode 210 is set to 0 or negative. As a result, the channel region below the gate electrode 210 disappears, and the electron current Ie1
Is shut off. When the supply of Ie1 stops, TR1 turns off, Ih is cut off, and the IGBT turns off.

As described above, when the IGBT is on, holes are injected from the collector layer 201 into the drift layer 202 by Ih, and holes are accumulated in the high-resistance drift layer.
This accumulated hole causes a so-called conductivity modulation phenomenon in which the resistance of the high-resistance drift layer is significantly reduced, and has a feature that the on-voltage can be reduced.

However, the IGBT has a problem called latch-up in which the current cannot be controlled by the operation of the parasitic element. The latch-up will be described below with reference to FIG. As Ih increases, the voltage drop Va across Rb increases. When this Va becomes larger than the threshold voltage (about 0.7 V) of the base-emitter junction of TR2, TR2 turns on, and current Ie2 flows. Ie2
Supplies the base current of TR1, the current continues to flow through TR1 and TR2 regardless of MOSFET 301. This is latch-up. When latch-up occurs, the MO
If you try to turn off TR1 by turning off SFET301, TR2
Since TR1 continues to operate due to Ie2 supplied by
The current cannot be cut off by the SFET 301, and the current continues to flow until the IGBT is destroyed.

This latch-up phenomenon is likely to occur as the temperature rises. This is because the resistance value of Rb, which causes latch-up, increases with an increase in temperature. For this reason, latch-up is likely to occur in the IGBT chip at the place where the temperature rise is greatest. FIG.
(A) and (b) show this.

FIG. 4A is a plan view of the IGBT chip viewed from the emitter electrode surface, and FIG. 4B is a plan view of FIG.
3 shows a temperature distribution in a cross section taken along a line AB.

In FIG. 4A, reference numeral 101 denotes a gate pad for connecting a gate wiring from an external circuit; 102, an emitter pad for connecting an emitter wiring from an external circuit;
03 is a withstand voltage holding region provided to hold the withstand voltage of the IGBT, and 104 is a current conduction region.

When the IGBT is on, a current flows from the collector electrode 212 to the emitter electrode 211 shown in FIG. The current flowing into the emitter electrode 211 flows inside the emitter electrode 211 toward the emitter pad 102 in the direction of the arrow shown in FIG. Therefore, current concentrates near the emitter pad 102, and the temperature rises. FIG. 4 shows the temperature distribution on the IGBT chip surface at this time.
(B). The temperature particularly increases around the emitter pad 102 due to current concentration.

As described above, since the IGBT is liable to latch-up when the temperature becomes high, the latch-up is particularly likely to occur around the emitter pad 102 where the temperature is high (hereinafter, the strength against the latch-up is defined as the latch-up tolerance). The larger the latch-up tolerance, the more difficult it is to latch up.)

FIG. 5 shows the distribution of the latch-up tolerance. Around the emitter pad 102 where the temperature rise is large, the latch-up withstand capability is significantly reduced. In the IGBT, when a latch-up occurs in a part of a chip, the latch-up spreads to the entire chip, and a latch-up current flows through the entire chip. For this reason, the latch-up tolerance is determined around the emitter pad 102 where the temperature is highest (the latch-up tolerance is lowest).

In order to prevent latch-up, the voltage drop Va generated across Rb must be reduced. As a means for reducing Va, for example, an intermittent emitter structure disclosed in JP-A-61-164263 is effective.

The intermittent emitter structure will be described below with reference to FIG. FIG. 6 shows an IGB having an intermittent emitter structure.
1 shows a perspective sectional view of T. 6, the same components as those in FIGS. 2 to 5 are denoted by the same reference numerals. In FIG. 6, reference numeral 601 denotes a discontinuous emitter layer. Note that, for convenience of illustration, the emitter electrode 211 is removed and drawn. The intermittent emitter structure is a structure in which the intermittent emitter layers 601 are periodically arranged at a constant interval L. Intermittent emitter layer 60
In the region where there is no 1, Rb is small because Ih flows directly into the emitter electrode 211 without passing under the intermittent emitter layer 601. Therefore, Rb can be reduced when viewed as a whole element. As a result, Va can be reduced, and the latch-up tolerance can be improved.

FIG. 7 shows an IG employing an intermittent emitter structure.
4 shows the distribution of the latch-up tolerance of the BT chip. With the intermittent emitter structure, the latch-up capability can be increased over the entire chip.

[0018]

However, the above-mentioned intermittent emitter structure has a problem that the voltage generated between the collector electrode and the emitter electrode when the IGBT is turned on (hereinafter referred to as on-voltage) is increased. ing. FIG.
As shown in FIG. 2, in the intermittent emitter structure, a portion where the emitter layer is not formed occurs, so that the gate electrode 210,
Intermittent emitter layer 601, base layer 203, drift layer 2
02, the channel width of the MOSFET decreases, and the on-resistance of the MOSFET increases. As a result, the ON voltage of the IGBT also increases.

An object of the present invention is to provide an IGBT having a low on-state voltage, a low loss, and a high resistance to destruction, without reducing the latch-up resistance.

[0020]

Means for Solving the Problems To solve the above problems,
The following means are conceivable as means for achieving the object of the present invention.

That is, at least one pair of main surfaces, a first layer of a first conductivity type adjacent to the first main surface of the pair of main surfaces, and a second layer of a second conductivity type adjacent to the first layer. A second layer, a third layer of a second conductivity type having a lower impurity concentration than the second layer adjacent to the second layer and the other main surface, and a third layer adjacent to the second main surface. A fourth layer of the first conductivity type selectively formed in the first layer, and a fifth layer of the second conductivity type selectively formed in the fourth layer adjacent to the second main surface. A first electrode formed on the first main surface and an insulating film on an exposed portion of the fourth layer in a region adjacent to the third layer and the fifth layer on the second main surface. A unit insulated gate semiconductor element comprising a second electrode formed through the first electrode and a third electrode formed in contact with the fourth layer and the fifth layer on the second main surface is repeatedly arranged and formed. Element area , First the wiring from the control circuit provided in the semiconductor body outside, and the second electrode is connected
And a second terminal to which the third electrode is connected, the second terminal being connected to the third electrode, and a wiring from a power supply circuit provided outside the semiconductor substrate. A fifth layer of the unit insulated gate semiconductor device is formed continuously along the fourth layer, and a fifth layer of the unit insulated gate semiconductor device formed close to a second terminal is the fifth layer. This is a structure formed intermittently along the fourth layer.

The insulated gate semiconductor device is an IG
It is conceivable to use a BT (Insulated Gate Bipolar Transistor).

Further, it is also preferable that the interval between the intermittently formed fifth layers decreases as the distance from the second terminal increases.

[0024] The second layer of the fourth layer formed close to the second terminal is determined from the depth from the second main surface of the fourth layer formed close to the first terminal. A structure having a large depth from the main surface is also preferable.

A unit IGBT formed near the second terminal
By forming the fifth layer intermittently, the latch-up resistance of the unit IGBT formed in the vicinity of the second terminal can be increased. The latch-up withstand capability of the IGBT chip is a unit IGB near the second terminal where the temperature rise is large.
Since it is determined by T, by improving the latch-up tolerance in this region, the latch-up tolerance of the entire chip can be greatly improved. Further, since the fifth layer of the unit IGBT near the first terminal where the latch-up withstand capability is small does not have an intermittent structure, an increase in on-voltage can be suppressed to a minimum.

With the above operation, it is possible to prevent a decrease in the latch-up resistance while minimizing an increase in the on-voltage.

As described above, by using the present invention, it is possible to provide an IGBT which has the same latch-up withstand capability as the conventional intermittent emitter, can reduce the on-voltage, is resistant to breakdown, and has a low on-voltage.

[0028]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 shows an IG to which the present invention is applied.
1 shows a first embodiment of a BT. In FIG. 1, the same components as those in FIGS. 2 to 7 are denoted by the same reference numerals. In FIG. 1, reference numeral 110 denotes an intermittent emitter structure application region. A feature of this embodiment is that a part of the current conduction region around the emitter pad 102 is an intermittent emitter structure application region 110.

Referring to FIG. 8, the operation of the main part according to the present embodiment will be specifically described. FIG. 8A shows the distribution of the latch-up resistance of the IGBT chip according to the present embodiment.
FIG. 8B shows the distribution of the ON voltage. FIGS. 8A and 8B
2 also shows the distribution of the latch-up resistance when the IGBT having the conventional structure is turned on.

As shown in FIG. 8A, according to the structure of the present embodiment, since the intermittent emitter structure is applied only to the periphery of the emitter pad where the latch-up withstand capability is significantly reduced,
In the vicinity of A away from the emitter pad, the latch-up tolerance does not change. However, at the periphery of the emitter pad where the latch-up withstand capability is the lowest, the latch-up withstand capability is improved by the intermittent emitter structure.
The BT chip as a whole has an increased latch-up tolerance.
On the other hand, as shown in FIG. 8B, the ON voltage increases only near the emitter pad to which the intermittent emitter is applied, so that the ON voltage can be reduced as compared with the conventional intermittent emitter structure.

In this embodiment, it is desirable to set the interval L between the intermittent emitter layers 601 to the following value. That is, L is the value at which the minimum value of the latch-up withstand capability in the intermittent emitter structure application region 110 is equal to the minimum value of the latch-up withstand capability of the current conduction region 104.

This will be described in detail with reference to FIG. FIG.
(A) and (b) show the distribution of the latch-up resistance and the ON voltage in the IGBT chip when the interval L of the intermittent emitter layer 601 in the intermittent emitter structure application region 110 is changed. FIG.
In (A), L is small, and (C) is when L is large. (B) is a value between (A) and (C), and is the value of L at which the minimum value of the latch-up withstand capability of the intermittent emitter structure application region 110 is equal to the minimum value of the latch-up withstand capability of the current conduction region 104. Is the case. (A) to (C)
As L increases, the latch-up resistance of the intermittent emitter structure application region 110 increases. This is because the hole bypass between the intermittent emitter layers 601 shown in FIG. 6 becomes large. However, even if L increases, the latch-up tolerance of the entire IGBT chip does not change between (B) and (C). The reason is that in the case of (C), the latch-up withstand capability of the entire IGBT chip is determined by the current conduction region 104.
The location where the latch-up is determined is indicated by an arrow in FIG. On the other hand, the ON voltage is higher in the case of (C) than in the case of (B). Therefore, it is not preferable to make L larger than (B).

As described above, in order to effectively improve the latch-up withstand voltage and minimize the rise of the on-state voltage, the latch-up withstand voltage has a distribution shown by the solid line in FIG. Is most desirable. Since the specific value of L greatly depends on the process of IGBT formation,
Although it cannot be shown generally, it has been experimentally confirmed that it is desirable to set the width of the intermittent emitter layer to be at least 1/3 of the interval L between the intermittent emitter layers.

As described above, according to the present structure, the ON voltage can be significantly reduced while maintaining the same latch-up resistance as that of the conventional intermittent emitter structure.

(Embodiment 2) FIG. 12 shows a second embodiment according to the present invention. This embodiment is characterized in that the intermittent emitter layer 60
1 between the intermittent emitter structure application areas 107 and 10
The point is that X, Y, and Z are set at 8, 109, respectively, so that X>Y> Z. As described above, as L decreases, the latch-up withstand capability decreases, and when L = 0, it can be regarded as a continuous emitter structure. In FIG. 12, the emitter pad 102 is connected to the intermittent emitter structure application region 10.
The distance L is reduced as the distance from 7, 108, 109 increases, and the distribution of the latch-up tolerance is changed stepwise. FIG.
3 (a) and 3 (b) show the distribution of the latch-up resistance and the ON voltage of the IGBT chip according to the present embodiment. By applying this structure, as shown in FIG. 13A, the latch-up tolerance can be made more uniform in the chip. The ON voltage is
As shown in FIG. 13B, the amount increases stepwise, so that it can be more suppressed as compared with the second embodiment. Further, in the present embodiment, the intermittent emitter layer interval L is changed in three stages to form three regions 107, 108, and 109. However, if the division of L is increased and the region is increased, the on-voltage can be further reduced. The increase can be suppressed.

(Embodiment 3) FIG. 14 shows a third embodiment of the present invention.
The following shows an example. In FIG. 14, the same components as those in FIGS. 1 to 13 are denoted by the same reference numerals. In FIG. 14, reference numeral 1401 denotes a deep junction base layer region. The feature of this embodiment is that the base layer 203 of the IGBT disposed in the deep junction base layer region 1401 is formed deep.
FIG. 15 shows a sectional structure of this embodiment. 1 to 14 are denoted by the same reference numerals. FIG. 15 shows a cross-sectional structure around the emitter pad 102. In FIG. 15, reference numeral 1501 denotes a deep junction base layer around the emitter pad 102. According to this, the lateral resistance Rb in the base layer 203 that causes the latch-up is reduced, so that the latch-up withstand capability can be increased. As a result, as shown in FIGS. 16A and 16B, the distribution of the latch-up withstand voltage and the ON voltage in the IGBT chip is similar to that in the first embodiment.

As a method of partially increasing the junction depth of the base layer 203, for example, a deep junction base layer region 140
There is a method such as increasing the concentration at the time of formation of only one base layer, but the method is not limited to this method, and the diffusion depth of the base layer in the deep junction base layer region 1401 can be increased. The same effect can be obtained by the method.

The same concept as in the first and second embodiments can be applied to the latch-up resistance improvement method using the deep junction base layer of the present embodiment. That is, based on the concept described with reference to FIG. 9, it is possible to determine the depth of the base layer that can optimize the relationship between the ON voltage and the latch-up tolerance. Further, according to the concept described in the second embodiment, the depth of the deep junction base layer region is changed stepwise, so that an increase in on-voltage can be suppressed to a minimum.

The embodiments of the present invention have been described above with reference to the first to third embodiments. However, it is needless to say that the present invention is not limited to the above-described structure. It is obvious to those skilled in the art that the effect can be obtained. Similarly, in the present embodiment, a so-called non-punch-through IGBT in which the collector layer 201 and the drift layer 202 are formed adjacent to each other has been described. A similar effect can be obtained for a so-called punch-through IGBT having a buffer layer of a die type.

In the above embodiment, the base layer 203 has p
Although a so-called n-channel IGBT to which a p-type impurity layer is applied has been described, a similar effect can be obtained for a p-channel IGBT.

Further, in this embodiment, a so-called planar type I having a structure in which a gate electrode 211 is formed on a semiconductor substrate is used.
Although the example of the GBT has been described, it is obvious that the present invention is not limited to this, and it is obvious to those skilled in the art that the same effect can be obtained even when applied to an IGBT having a different gate electrode structure, for example, a trench IGBT. is there. Also, as will be apparent to those skilled in the art, the present invention can be similarly implemented for each pad even when a plurality of emitter pads 102 are formed on the IGBT chip.

As an application example of the IGBT to which the present invention is applied, an inverter can be considered.

(Embodiment 4) FIG. 11 shows a fifth embodiment according to the present invention. 11, reference numerals 1701 and 1702 denote DC terminal pairs connected to a DC power supply, and reference numerals 1703 to 1708 denote I / O terminals.
GBT, 1710 to 1715 are feedback diodes, 172
0 to 1721 are AC terminals connected to the load. According to the present embodiment, since the latch-up resistance of the IGBT is increased, the protection circuit can be simplified. In the case of the conventional device, there is a problem that the device is destroyed as soon as an excessive current flows because the latch-up resistance is small, and a high-speed and high-precision device is required for the protection circuit so as to be adapted thereto.
According to the IGBT of the present invention, the high-speed and high-precision protection circuit is not required because the latch-up withstand capability is large and the device is hard to break, and the cost can be reduced in this regard.

In addition, as an application example of the IGBT to which the present invention is applied, an igniter for an automobile or the like can be considered.

When applied to an automotive igniter,
Since the energizing current in a state where a high voltage is applied can be increased, the energy at the time of ignition of the ignition plug can be increased, and a stable ignition system with a large power can be realized.

[0047]

As described above, according to the present invention,
By increasing the latch-up withstand capability around the portion where the temperature rise due to current concentration is large, for example, around the emitter pad, it is possible to increase the latch-up withstand capability of the entire chip while minimizing the increase in on-voltage. This makes it possible to realize an IGBT that is resistant to destruction at a low on-voltage.

[Brief description of the drawings]

FIG. 1 is a plan view showing a first embodiment of the semiconductor device of the present invention.

FIG. 2 is a sectional view showing an IGBT structure.

FIG. 3 is a circuit diagram showing an equivalent circuit of the IGBT.

FIG. 4 is a plan view showing a conventional IGBT and a temperature distribution diagram thereof.

FIG. 5 is a distribution diagram of latch-up withstand capability of a conventional IGBT.

FIG. 6 is a perspective sectional view showing a conventional intermittent emitter structure.

FIG. 7 is a distribution diagram of latch-up withstand capability of a conventional IGBT having an interrupted emitter structure.

FIG. 8 is a distribution diagram of a latch-up resistance and an on-voltage of the IGBT according to the present invention.

FIG. 9 is a distribution diagram of latch-up withstand voltage and on-voltage of the first embodiment of the IGBT according to the present invention.

FIG. 10 is a plan view of a second embodiment of the IGBT according to the present invention.

FIG. 11 is a circuit configuration diagram of an inverter to which the present invention is applied.

FIG. 12 is a plan view of a third embodiment of the IGBT according to the present invention.

FIG. 13 is a distribution diagram of latch-up withstand voltage and on-state voltage of the third embodiment of the IGBT according to the present invention.

FIG. 14 is a plan view of a fifth embodiment of the IGBT according to the present invention.

FIG. 15 is a sectional structural view of a fifth embodiment of the IGBT according to the present invention.

FIG. 16 is a distribution diagram of latch-up withstand voltage and on-state voltage of the fifth embodiment of the IGBT according to the present invention.

[Explanation of symbols]

101: gate pad, 102: emitter pad, 10
3 ... withstand voltage holding region, 104 ... current conduction region, 106, 1
10: Intermittent emitter structure application region, 107: Intermittent emitter structure application region (L = large), 108: Intermittent emitter structure application region (L = medium), intermittent emitter structure application region (L =
Small), 201: collector layer, 202: drift layer, 20
3 Base layer, 204 Emitter layer, 205 Gate insulating film, 210 Gate electrode, 211 Emitter electrode, 2
12 ... collector electrode, 301 ... MOSFET, 302 ... pnp
Transistor, 303 ... npn transistor, 304 ...
Lateral resistance, 601: discontinuous emitter layer, 1401: deep junction base layer region, 1501: deep junction base layer, 1701, 1
702 DC terminal pair connected to DC power supply, 1703 to 17
08 ... IGBT, 1710-1715 ... feedback diode, 1720-1721 ... AC terminal connected to the load.

Claims (5)

[Claims] 1. A first conductive type first layer adjacent to at least a pair of main surfaces, a first main surface of the pair of main surfaces, and a second conductive type adjacent to the first layer. Second layer, second
And a third layer of a second conductivity type having a lower impurity concentration than the second layer adjacent to the second layer and the other main surface; and selectively in the third layer adjacent to the second main surface. A fourth layer of the first conductivity type formed, a fifth layer of the second conductivity type selectively formed in the fourth layer adjacent to the second main surface; A first electrode formed on the main surface, and a second electrode formed on an exposed portion of the fourth layer in a region adjacent to the third and fifth layers on the second main surface via an insulating film. And the third electrode formed in contact with the fourth and fifth layers on the second main surface.
An element region in which unit insulated gate semiconductor elements composed of the following electrodes are repeatedly arranged and formed; a wiring from a control circuit provided outside the semiconductor substrate; a first terminal to which the second electrode is connected; In a semiconductor device having a wiring from a power supply circuit provided outside a semiconductor substrate and a second terminal connected to the third electrode, the unit insulating gate formed near a first terminal A fifth layer of the semiconductor device is formed continuously along the fourth layer, and a fifth layer of the unit insulated gate semiconductor device formed near the second terminal is the fourth layer. Characterized in that the semiconductor device is formed intermittently along the line. 2. The insulated gate semiconductor device according to claim 1, wherein the insulated gate semiconductor device is an IGBT (Insulated Gate Bipolar Transistor).
stor). 3. The semiconductor device according to claim 1, wherein the distance between the fifth layers formed intermittently decreases as the distance from the second terminal increases. 4. A semiconductor device according to claim 1, wherein the fourth layer formed close to the second terminal is closer to the second terminal than the depth of the fourth layer formed close to the first terminal from the second main surface. A semiconductor device, wherein the depth of the layer from the second main surface is deep. 5. A configuration in which two parallel circuits of a switching element and a diode of opposite polarity are connected in series between a pair of DC terminals, the same number of AC terminals as the number of phases of AC output, and a pair of DC terminals. Wherein the switching element is the semiconductor device according to any one of claims 1 to 4, wherein the switching element is a semiconductor device having the same number of inverter units as the number of phases of the AC output connected to different AC terminals at interconnection points of the parallel circuit. A power converter characterized by the above-mentioned.