JPH1093009A - Semiconductor chip module, multi-chip module and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip module having a high processing speed with few signal layers. SOLUTION: The module comprises an MCM structure 1, having surface layer wiring patterns 7, inner layer wiring patterns 8, a chip-mounting parts at specified areas of the surface, and pads 2 connected to the wiring patterns 7, 8 round the chip mounting areas, bare chips LSI 3a, 3b which are mounted on the chip-mounting areas on the substrate 1 and have pads 4a, 4b on the surface, bonding wires 6 which connect the pads 4a, 4b mutually between the chips LSI 3a, 3b, connected to the adjacent chip-mounting parts on the substrate 1, and bonding wires 5 which connect predetermined pads 2 on the substrate 1 to the pads 4a, 4b on the chips LSI 3a, 3b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip module (multi-chip module) including a plurality of semiconductor chips (bare chip LSI) and an electronic apparatus using the same.

[0002]

2. Description of the Related Art In recent years, a plurality of bare chips cut from a wafer are directly mounted on a single substrate for the purpose of improving the mounting density of semiconductor chip modules and improving the processing speed by reducing propagation delay between the plurality of semiconductor chips. Multi-chip modules (hereinafter, referred to as MCMs) have been used.

FIG. 8 shows an example of such an MCM. In this case, two bare chip LSIs 103a and 103b are mounted on the MCM substrate 101, and the bare chip LS
Bare chip LSI pads 104a and 104b in I103a and 103b and a plurality of MCs on MCM substrate 101
M substrate pad 102 and a plurality of bonding wires 10
5, respectively.

Here, a surface layer wiring pattern 106 and an inner layer wiring pattern 107 are provided on the MCM substrate 101, and a plurality of corresponding MCM substrate pads 102 are connected to each other by these wiring patterns 106 and 107. I have. As a result, the corresponding bare chip LSI pads 104a and 104b are
5 and wiring patterns 106 and 107.

[0005] Further, such an MCM is a bare chip LS.
I103a, 103b and bonding wire 105
Is molded with a resin, and then mounted on a system board or the like of an electronic device using a BGA (ball grid array) or a clip lead.

[0006]

As described above, in the conventional MCM, the connection between the bare chip LSIs 103a and 103b is performed through the wiring patterns 106 and 107 of the substrate 101. 104a, 104b and MCM
There is a problem that the substrate pad 102 must be connected.

Further, bare chip LSIs 103a and 103
When the number of pins (number of pads) of b increases, the MCM substrate 1
01, the number of wiring patterns 106 and 107 to be provided increases, and accordingly, the number of signal layers for providing the wiring patterns 106 and 107 increases, resulting in an increase in cost. Further, since the signal propagation time between the bare chip LSIs 103a and 103b increases, there is a problem that the processing speed of the entire MCM is affected. An object of the present invention is to provide a semiconductor chip module, a multi-chip module, and an electronic device capable of high-speed processing with a small number of signal layers.

[0008]

In order to solve the above problems, a semiconductor chip module according to the present invention has a predetermined wiring pattern formed on a surface and an inner layer, and has a plurality of chip mounting portions on a predetermined surface portion of the surface. A substrate provided with a plurality of electrodes connected to a wiring pattern on the periphery of the chip mounting portion, and a plurality of electrodes each mounted on the plurality of chip mounting portions on the substrate and provided with a plurality of electrodes on the surface. A semiconductor chip, a plurality of first connection means respectively connecting a plurality of predetermined electrodes between the plurality of semiconductor chips, a plurality of electrodes on a predetermined substrate, and a plurality of electrodes on the semiconductor chip And a plurality of second connection means for respectively connecting.

In the present invention, since the semiconductor chips are directly connected to each other by the first connection means, the number of wiring patterns to be provided on the substrate is reduced accordingly. Therefore, the number of signal layers on the substrate is reduced, so that the manufacturing cost can be reduced. At this time, if the connection path of the first connection means is three-dimensionally intersected with the wiring path in the wiring pattern on the substrate surface, the wiring pattern which conventionally had to be formed as an inner layer can be provided on the substrate surface. , The number of signal layers can be further reduced.

In addition, since the signal propagation time is reduced between the semiconductor chips connected by the first connecting means, the processing speed is increased. In this case, if the electrodes adjacent to each other are connected to each other between the semiconductor chips mounted on the chip mounting portions adjacent to each other on the substrate, the connection path between them is minimized, and the propagation time is further reduced.

Here, if the first and second connecting means are constituted by a conductor body and an insulating coating covering the conductor body, short-circuiting occurs even when the first and second connecting means come into contact with each other. All the electrodes that need to be connected between the semiconductor chips
Connection means. Therefore, since the number of wiring patterns and signal layers to be provided on the substrate can be further reduced, the manufacturing cost is further reduced.

In another aspect of the present invention, an electronic device is generated by using a semiconductor chip module as one of the constituent elements. A multichip module according to still another aspect of the present invention has a predetermined wiring pattern formed on a surface and an inner layer, a plurality of chip mounting portions on a predetermined surface portion of the surface, and wiring around a periphery of the chip mounting portion. A substrate provided with a plurality of pads connected to a pattern, a plurality of bare chip LSIs respectively mounted on a plurality of chip mounting portions on the substrate and provided with a plurality of pads on the surface, and a chip adjacent to the substrate A plurality of first bonding wires for connecting adjacent electrodes between the bare chip LSIs connected to the mounting portion, and a plurality of pads on a predetermined substrate and a plurality of pads on a semiconductor chip, respectively. A plurality of second bonding wires connected to each other. In the case where the first and second bonding wires are formed by the wire body and the insulating film covering the wire body, not only the electrodes placed adjacent to each other between the bare chip LSIs, but also
Arbitrary electrodes can be connected to each other.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1 is a diagram showing a schematic configuration of an MCM according to a first embodiment of the present invention. This MCM is
The MCM board 1 has two bare chips LSI 3a and 3b mounted thereon.

The MCM substrate 1 has a surface layer wiring pattern 7 and one or more layers based on a predetermined circuit design by an etching process using a copper foil or the like for a surface layer and an inner layer of an insulating substrate such as glass epoxy resin or ceramic. The above inner layer wiring pattern 8 is formed, and a plurality of MCM board pads 2 connected to the surface layer wiring pattern 7 or the inner layer wiring pattern 8 are provided around a predetermined mounting portion of the bare chip LSIs 3a and 3b. is there. The surface layer wiring pattern 7 and the inner layer wiring pattern 8 are connected by through holes (not shown) according to the circuit design.

Here, each wiring path in the surface layer wiring pattern 7 and the inner layer wiring pattern 8 is a bare chip LS
It is desirable that the I-pads 4a and 4b are provided so as to three-dimensionally intersect with the bonding wires 6 connecting the I-pads 4a and 4b to each other.

The bare chip LSIs 3a and 3b are chips having functions of a microprocessor, a memory, and the like, which have just been cut out from a wafer and are not sealed in a package, and are directly mounted on the MCM substrate 1 by processing with an epoxy resin or a silver paste. Has been implemented.

The bare chip LSIs 3a and 3b are provided with a plurality of bare chip LSI pads 4a and 4b as electrodes formed by aluminum evaporation or the like, respectively. The number of the bare chip LSI pads 4a and 4b is determined according to the functions of the bare chip LSIs 3a and 3b.
About one. Further, each bare chip LSI pad 4a,
It is desirable that the size of 4b is about 100 μm square.

Here, the bare chip LS on the MCM substrate 1
Bare chip LSI pad 4a and bare chip LSI pad 4b adjacent to each other between I3a and 3b, that is, bare chip LSI pad 4 on the right periphery of bare chip LSI 3a
a and bare chip L on the left periphery of bare chip LSI 3b
The SI pad 4b is connected to the bare chip L when connected to each other.
It is desirable to form a signal line frequently used between the SIs 3a and 3b, for example, an address bus and a data bus.

On the other hand, bare chip LSI pad 4a and bare chip LSI pad 4b which are not adjacent to each other,
The bare chip LSI pad 4a and the bare chip LSI in the upper, lower, and left peripheral areas of the bare chip LSI 3a
3b bare chip LSI around the top, bottom and right
The pad 4b is connected to a plurality of MCs on the MCM substrate 1 to be connected.
It is arranged so as to correspond to M substrate pad 2.

In this embodiment, the adjacent bare chips LS
The I pad 4a and the bare chip LSI pad 4b are directly connected by a bonding wire 6. On the other hand, the other bare chip LSI pads 4a and the bare chip LSI pads 4b are connected to the corresponding MCM substrate pads 2 by bonding wires 5, so that the bare chip LSI pads 4a and the inner chip Connected.

Here, the bonding wires 5 and 6 are gold wires or aluminum wires having a diameter of about 30 μm, and are connected by various bonding methods such as a thermocompression bonding method and an ultrasonic bonding method.

The length of each bonding wire 6 is determined based on the arrangement of the bare chips LSI 4a and 4b in the bare chips LSI 3a and 3b so that the bonding wires 6 do not come into contact with each other and short-circuit due to resin molding described later. It must be set in advance.

After performing the bonding as described above,
The bare chips LSI 3a and 3b and the bonding wires 5 and 6 on the MCM substrate 1 are molded using a resin such as epoxy. In this case, short-circuiting does not occur due to the bonding wire 6 being crushed by the resin or coming into contact with the surface layer wiring pattern 7 which intersects three-dimensionally.

FIG. 2 is a diagram showing a cross section of the MCM when the molding is performed as described above. Thus, resin 2
1 to perform bare chip LSI
The bonding wires 3a and 3b and the bonding wires 5 and 6 are protected from changes in temperature and humidity and external shocks, and are insulated from each other. FIG. 2 shows the insulating layer 22 on which the inner wiring pattern 8 is provided.

As described above, in the MCM of this embodiment, MC
The bare chip LSI pad 4a and the bare chip LSI pad 4b adjacent to each other on the M substrate 1 are directly connected by only the bonding wires 6 without passing through both the surface layer wiring pattern 7 and the inner layer wiring pattern 8.

Therefore, the number of MCs equal to the number of pairs of adjacent bare chip LSI pads 4a and bare chip LSI pads 4b
The number of wirings to be provided on the M substrate 1 is reduced. In addition, since the bonding wires 6 and the wiring in the surface layer wiring pattern 7 can be three-dimensionally crossed with each other, the wiring that has conventionally been required to be the inner layer wiring pattern 8 is also formed on the MCM substrate 1 as the surface layer wiring pattern 7. Can be provided. As described above, the number of signal layers in the entire MCM substrate 1 is reduced, and the manufacturing cost can be reduced.

Further, the adjacent bare chip LSI pad 4a and bare chip LSI 4b are
Only the connection is made, so that the signal propagation time during this period is shortened, and high-speed processing becomes possible. As described above, if the signal lines frequently used in the MCM are formed by the bonding wires 6, the MCM can be operated efficiently.

Next, three bare chips L are placed on the MCM substrate 1.
A case where the SI is mounted will be described. FIG. 3 is a diagram showing a schematic configuration of such an MCM. In FIG. 3, the surface layer wiring pattern and the inner layer wiring pattern are omitted.

In this case, between the bare chip LSIs mounted adjacently on the MCM substrate, that is, between the bare chip LSIs 3a and 3b and between the bare chip LSIs 3b and 3b,
Bare chip LSI pads 4a, 4b and 4b, 4c adjacent to each other between 3c are directly connected by bonding wires 6, respectively.

Similarly, even when there are more than three bare chip LSIs, adjacent bare chip LSI pads are directly connected to each other by bonding wires between bare chip LSIs mounted adjacently on the MCM substrate.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
It is a figure showing the schematic structure of the MCM concerning the embodiment. In the present embodiment, portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and differences from the first embodiment will be mainly described.

In this embodiment, the connection is made by bonding wires 9 and 10 whose surfaces are covered with an insulating film, instead of the bonding wires 5 and 6 in the first embodiment.

First, any bare chip LSI pads 4 a and 4 b that need to be connected are connected by bonding wires 10. As a result, a portion (hereinafter referred to as an intersecting portion 11) of the plurality of bonding wires 10 is in contact with each other. However, since each bonding wire 10 is covered with the insulating film, no short-circuit occurs at the intersecting portion 11.

On the other hand, the other bare chip LSI pads 4a and 4b are connected to the corresponding MCM board pads 2 by bonding wires 9, respectively.

FIG. 5 shows these bonding wires 9 and 1.
FIG. 2 is a cross-sectional view showing a configuration of a zero. Bonding wire 9,
10 is a wire body 31 made of gold or aluminum
Is covered with an insulating film 32 of formal resin. Here, assuming that the bonding wires 9 and 10 are connected by, for example, a thermocompression bonding method, the bonding wires 9 and 10 are supplied from a bonding tool called a capillary, and the tips of the bonding wires 9 and 10 are discharged by electric discharge or the like. Then, a plastic ball is formed, and the plastic ball is thermocompression-bonded to the connection surface. In this case, since the insulating film 32 covering the wire main body 31 evaporates in forming the plastic ball, the material of the deformed plastic ball is exposed on the connection surface.

FIG. 6 shows such a bonding wire 9.
FIG. 2 is an enlarged view of the connection surface of FIG.
The CM substrate pad 2 and the bonding wire 9 are connected via a deformed plastic ball 33, and the plastic ball 3
The insulating film 32 is peeled off from the surface of the wire 3, and the material of the wire body 32 is exposed. When the diameter of the wire main body 32 is about 30 μm, the diameter of the plastic ball 33 deformed on the connection surface is about 50 to 70 μm.

As described above, in this embodiment, since the bonding wires 9 and 10 are covered with the insulating film and do not short-circuit with each other, the bonding wires 9 and 10 between the adjacent bare chip LSI pads 4a and 4b are different from those in the first embodiment. Not only all necessary bare chip LSI pads 4a, 4
It is possible to connect between b with the bonding wire 10. Accordingly, the number of wiring patterns 7, 8 to be provided on the MCM substrate 1, and further the number of signal layers, is further reduced.
MCM can be manufactured at lower cost.

Unlike the first embodiment, it is not necessary to set the length of each bonding wire 10 in advance, so that the connection can be easily performed. Also,
Since the bare chip LSI pads 4a and 4b can always be connected with the shortest distance, the signal propagation time is shorter.

Furthermore, since the bonding wires 9 and 10 are not crushed and contact each other when the resin molding is performed or short-circuited even when the bonding wires 9 and 10 come into contact with the surface layer wiring pattern 7, the yield at the time of manufacturing the MCM is reduced. improves.

Note that, as shown in FIG.
Even if three bare chip LSIs 3a to 3c are mounted on the semiconductor chip, all the bare chip LSI pads 4a to 4c that need to be directly connected can be connected by the bonding wires 10. In this case, one bare chip LSI
Two or more bare chip LSIs with different pads 4a to 4c
You may make it connect to the pads 4a-4c. Less than,
Even when there are more than three bare chip LSIs, it is possible to directly connect any bare chip LSI pads.

[0041]

As described above, according to the present invention, since the semiconductor chips are directly connected to each other by bonding wires or the like, the number of wiring patterns to be provided on the substrate is reduced, and high-speed processing can be performed with a small number of signal layers. A possible semiconductor chip module can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of an MCM according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a cross section of the MCM molded in the same embodiment.

FIG. 3 is a diagram showing a schematic configuration of another MCM in the embodiment.

FIG. 4 is a diagram showing a schematic configuration of an MCM according to a second embodiment of the present invention;

FIG. 5 is a view showing a cross section of the bonding wire in the embodiment.

FIG. 6 is an enlarged sectional view showing a connection surface of a bonding wire according to the embodiment;

FIG. 7 is a diagram showing a schematic configuration of another MCM in the embodiment.

FIG. 8 is a diagram showing a schematic configuration of a conventional MCM.

[Description of Signs] 1 ... MCM board 2 ... MCM board pad 3a, 3b, 3c ... Bare chip LSI 4a, 4b, 4c ... Bear chip LSI pad 5 ... Bonding wire 6 ... Bonding wire 7 ... Surface layer wiring pattern 8 ... Inner layer wiring pattern 9 bonding wire 10 bonding wire 11 crossing 21 resin 22 insulating layer 31 wire body 32 insulating film 33 plastic ball 101 MCM substrate 102 MCM substrate pad 103a, 103b bare chip LSI 104a, b ... Bare chip LSI pad 105 ... bonding wire 106 ... surface layer wiring pattern 107 ... inner layer wiring pattern

Claims (8)

[Claims] A predetermined wiring pattern is formed on a surface and an inner layer, and a plurality of chip mounting portions are provided on a predetermined surface portion of the surface, and a plurality of chip mounting portions connected to the wiring pattern are provided on a periphery of the chip mounting portion. A substrate on which electrodes are provided, and mounted on a plurality of chip mounting portions on the substrate,
A plurality of semiconductor chips each having a plurality of electrodes on a surface thereof; a plurality of first connection means respectively connecting the plurality of predetermined electrodes between the plurality of semiconductor chips; a predetermined substrate A semiconductor chip module, comprising: a plurality of second connection means for respectively connecting the plurality of electrodes on the semiconductor chip and the plurality of electrodes on the semiconductor chip. A predetermined wiring pattern formed on the surface and the inner layer, a plurality of chip mounting portions on a predetermined surface portion of the surface, and a plurality of chip mounting portions connected to the wiring pattern on the periphery of the chip mounting portion; A substrate on which electrodes are provided, and mounted on a plurality of chip mounting portions on the substrate,
A plurality of semiconductor chips each having a plurality of electrodes on the surface, a conductor body and an insulating coating covering the conductor body,
A plurality of first connection means for respectively connecting the plurality of predetermined electrodes between the plurality of semiconductor chips, a conductor body and an insulating coating covering the conductor body;
A semiconductor chip module comprising: a plurality of second connection means for respectively connecting a plurality of predetermined electrodes on the substrate and a plurality of electrodes on the semiconductor chip. 3. The semiconductor device according to claim 2, wherein the plurality of first connection means respectively connect adjacent electrodes between the semiconductor chips mounted on the adjacent chip mounting portions on the substrate. Item 3. The semiconductor chip module according to item 1 or 2. 4. The apparatus according to claim 1, wherein said plurality of first connection means are connected so as to three-dimensionally intersect a wiring path in a wiring pattern formed on a surface of said substrate. The semiconductor chip module according to the above. 5. A predetermined wiring pattern is formed on the surface and the inner layer, and a plurality of chip mounting portions are provided on a predetermined surface portion of the surface, and a plurality of chip mounting portions connected to the wiring pattern are provided around the chip mounting portion. A substrate provided with pads and mounted on a plurality of chip mounting portions on the substrate,
A plurality of bare chips LSI each having a plurality of pads on the surface thereof; and a plurality of first bondings respectively connecting adjacent pads between the bare chip LSIs respectively mounted on the chip mounting portions adjacent to each other on the substrate. A multi-chip module comprising: a wire; and a plurality of second bonding wires that respectively connect a plurality of predetermined pads on the substrate and a plurality of pads on the bare chip LSI. 6. A predetermined wiring pattern is formed on a surface and an inner layer, and a plurality of chip mounting portions are provided on a predetermined surface portion of the surface, and a plurality of chip mounting portions connected to the wiring pattern are provided around the chip mounting portion. A substrate provided with pads and mounted on a plurality of chip mounting portions on the substrate,
A plurality of bare chip LSIs each having a plurality of pads on the surface thereof; a plurality of wire bodies each comprising a wire body and an insulating coating covering the wire body, each of which connects the plurality of predetermined pads between the plurality of bare chip LSIs; A first bonding wire, a wire body, and a plurality of second wires, each of which comprises a plurality of pads on the substrate and a plurality of pads on the bare chip LSI, each of which is composed of a wire body and an insulating coating covering the wire body. A multi-chip module comprising a bonding wire. 7. A predetermined wiring pattern is formed on each of a surface and an inner layer, and a plurality of chip mounting portions are provided on a predetermined surface portion of the surface, and a plurality of chip mounting portions connected to the wiring pattern are provided on the periphery of the chip mounting portion. A substrate on which electrodes are provided, and mounted on a plurality of chip mounting portions on the substrate,
A plurality of semiconductor chips each having a plurality of electrodes on a surface thereof; a plurality of first connection means respectively connecting the plurality of predetermined electrodes between the plurality of semiconductor chips; a predetermined substrate An electronic device comprising, as constituent elements, a semiconductor chip module including a plurality of upper electrodes and a plurality of second connection means for respectively connecting a plurality of electrodes on the semiconductor chip. 8. A predetermined wiring pattern is formed on a surface and an inner layer, respectively, and a plurality of chip mounting portions are provided on a predetermined surface portion of the surface, and a plurality of chip mounting portions connected to the wiring pattern are provided around the chip mounting portion. A substrate on which electrodes are provided, and mounted on a plurality of chip mounting portions on the substrate,
A plurality of semiconductor chips each having a plurality of electrodes on the surface, a conductor body and an insulating coating covering the conductor body,
A plurality of first connection means for respectively connecting the plurality of predetermined electrodes between the plurality of semiconductor chips, a conductor body and an insulating coating covering the conductor body;
An electronic device comprising, as a constituent element, a semiconductor chip module including a plurality of second connection means for connecting a plurality of predetermined electrodes on the substrate and a plurality of electrodes on the semiconductor chip, respectively. machine.