JPH1092811A - Semiconductor device, its manufacture and reflection type liquid crystal display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a semiconductor chip suitable for a base of a reflection type liquid crystal display. SOLUTION: In a chip 348 wherein an insulating film and a wiring are laminated and formed on a semiconductor substrate 310, a thin uppermost wiring layer 344 composed of TiN/Ti which is resistive to corrosion is formed on an uppermost interlayer insulating film 342 whose upper surface is flatly formed, and the surface of the chip is practically exposed. A protective film composed of P-SiN is stuck on the surface of the uppermost interlayer insulating film 342, and chip protecting property is applied. A thin insulating film 346 having a mirror type flat surface is laminated on the uppermost wiring layer 344.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a method of manufacturing the same, and a reflection type liquid crystal display device. More particularly, the present invention relates to a semiconductor device suitable for directly mounting other components or devices such as liquid crystal on a chip surface. The present invention relates to a device, a manufacturing method thereof, and a reflective liquid crystal display device using the semiconductor device.

[0002]

2. Description of the Related Art Generally, in a semiconductor device such as an LSI, a chip including various elements formed on a semiconductor substrate such as silicon (Si) and a multilayer wiring formed on the substrate for operating these elements is used. Have. This multilayer wiring is usually formed on a substrate by CVD (Chemical Vapor Depos).
After a metal film is formed by laminating an Al-based material such as an Al-Si alloy on an interlayer insulating film such as a silicon oxide film deposited by the above method, the metal film is processed into a predetermined pattern to form a wiring. It is formed by repeating a process of forming and further depositing another interlayer insulating film thereon as necessary.

On the other hand, when a reflective liquid crystal or the like is driven on a semiconductor chip such as a Si chip-based liquid crystal, an interlayer insulating film or a passivation film which is an uppermost insulating film has extremely flatness. There has been a demand for a high mirror finish and as thin as possible.

[0004] Normal interlayer film flattening, for example, SOG (Spi
n On Glass) coating and etchback methods
Although it is possible to smooth the wiring step to such an extent that the wiring in the upper layer becomes easy, it is not possible to bring the state close to a mirror surface and extremely flat. As a method of making the flatness extremely high, CMP (Chemical Mechanical) is used.
There is a case in which this technique is applied to a conventional multi-layer wiring insulating film and the surface thereof is flattened.

FIG. 20 shows a wiring 2 having a thickness T1 formed on a flat insulating film 1 and a flat insulating film 3 having a thickness T2 formed thereon. In order to form the film 3 by the above-mentioned CMP method, first, an insulating material is deposited to a thickness of at least T3 (= T1 + T2) indicated by a two-dot chain line, and then a thickness exceeding T2 (T3-T2). Need to be polished. In other words, in order to planarize the insulating film by the above-mentioned CMP method, it is necessary to deposit an insulating material having a thickness of at least twice the level difference T1 of the wiring 2 and to polish the level difference or more.

On the other hand, the polishing by the CMP method has a large variation, and a variation of 10% or more of the polishing amount (thickness) can occur. Therefore, it is preferable that the polishing amount is as small as possible for flattening.

[0007]

However, the wiring layer has A
When an l-based material is used, in order to function as an electrode or a wiring, it is necessary to increase the thickness to, for example, 0.5 μm or more, and therefore, the polishing amount is also required to be 0.5 μm or more. When the wiring 2 is formed of an Al-based material as described above, the polishing amount is large. Therefore, there is a problem in forming a mirror-like flat surface in consideration of polishing variations.

As described above, when the thin insulating film 3 is formed on the wiring 2 by the CMP method, since the Al-based wiring material which is usually used is relatively soft, the force is applied to the part where the wiring 2 exists and the part where the wiring 2 does not exist. However, there is a drawback that the thickness tends to be non-uniform, probably because of the different degree of application, and complete flattening is also difficult in this regard.

Therefore, an interlayer insulating film or a passivation film having a thin and completely flat mirror-like flat surface is formed on a wiring made of an Al-based material having a film thickness of 0.5 μm or more, as in the prior art. There was a problem that it was extremely difficult.

Further, in recent semiconductor chips, in order to prevent corrosion of wiring, a plasma CVD (Chemical Vapor Deposit) is mainly formed on the uppermost layer as a chip protective film.
ion) (hereinafter referred to as p-SiN).

FIG. 21 schematically shows an enlarged cross section of a main part of an example of such a semiconductor chip. That is, this semiconductor chip is formed on a semiconductor substrate 10 made of silicon (Si) in which sources and drains constituting a so-called MOS transistor are formed, via a LOCOS 12, a first interlayer insulating film 14, and a second interlayer insulating film. 16 and a third interlayer insulating film 18 are sequentially stacked. A first wiring layer 22 connected to a lower gate electrode 20 via a contact hole is provided on the first interlayer insulating film 14, and a second wiring layer 24 is provided on the second interlayer insulating film 16. Are respectively laminated, and a bonding pad 26 made of an exposed second wiring layer 24 is formed in an opening of the third interlayer insulating film 18 of the uppermost layer. In this semiconductor chip, the uppermost third interlayer insulating film 18 is a chip protective film.

By the way, depending on the application, other components or devices are directly mounted on the semiconductor chip, such as a Si chip-based liquid crystal, in addition to the connection by the normal bonding performed through the bonding pad 26. In some cases, electrical connections have been made.

However, as described above, when other components or devices are directly attached to the chip to be electrically connected, as in the case of the semiconductor chip shown in FIG.
There is also a problem that a chip protection film cannot be formed on the uppermost wiring layer.

The present invention has been made to solve the above-mentioned conventional problems, and it is a first object of the present invention to provide a semiconductor device having a chip suitable for mounting a liquid crystal on a surface thereof, and a method of manufacturing the same. I do.

Another object of the present invention is to form a thin insulating film having a mirror-like flat surface with a very flat surface on the uppermost wiring layer.

A third object of the present invention is to sufficiently protect the inside of a chip so that other components or devices can be directly attached to the surface of the chip.

A fourth object of the present invention is to provide a reflective liquid crystal display device formed integrally with a chip.

[0018]

According to a first aspect of the present invention, there is provided a semiconductor device having a chip in which a plurality of insulating films and a wiring layer are stacked on a semiconductor substrate, and an upper interlayer insulating film having a flat upper surface. And an uppermost wiring layer of a predetermined pattern having a thickness of 0.5 μm or less formed of a metal having a higher hardness than an Al-based material laminated on the flat surface of the uppermost interlayer insulating film; The first and second problems have been solved by forming a structure in which a passivation film having a mirror-like flat surface is formed.

That is, on the flat surface of the uppermost interlayer insulating film, a thin uppermost wiring layer having a predetermined pattern and made of, for example, a titanium-based material having a sufficient hardness as compared with an Al-based material usually used as a wiring material is formed. By doing so, the insulating material deposited thereon can be polished to a sufficiently thin and mirror-like flat surface. Here, as a material having sufficient hardness compared to the Al-based material, Ti, Cr, Co,
Ni, Mo, W, Pt, or a silicide thereof, or a composite film of these and TIN formed thereon can be used.

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a chip in which a plurality of insulating films and a wiring layer are laminated on a semiconductor substrate, wherein the deposited insulating material is planarized to form an uppermost interlayer insulating film. Forming, forming the uppermost wiring layer of a predetermined pattern on the flat surface of the uppermost interlayer insulating film, and forming the uppermost insulating film having a mirror-like flat surface on the entire substrate on the uppermost wiring layer By having the above, the semiconductor chip can be reliably manufactured.

According to a second aspect of the present invention, in a semiconductor device having a chip in which an insulating film and a plurality of wiring layers are laminated on a semiconductor substrate, the uppermost interlayer insulating film immediately below the uppermost wiring layer has chip protection. The first and third problems are solved by using a material resistant to corrosion for the uppermost wiring layer and substantially exposing the uppermost wiring layer to the chip surface. Here, chip protection refers to protecting the chip from being affected by various external factors that adversely affect the semiconductor element. The properties required for this are: 1) no pinholes, cracks, and minute defects in the protective film itself; 2) prevention of penetration of moisture which induces corrosion of wiring, particularly Al-based wiring; and 3) semiconductor. This is to prevent the penetration of alkali ions, particularly Na + ions, which degrade the characteristics of transistors and the like formed at the substrate interface. As a protective film having such characteristics, a silicon nitride film, a silicon oxide nitride film, or the like formed by a plasma CVD method is used.

The uppermost wiring layer is made of a material that is more resistant to corrosion than an Al—Si alloy or the like usually used as a wiring material. By providing protection,
After ensuring the reliability of the chip, the uppermost wiring layer can be used in a substantially bare state, and other components and devices can be directly attached to the chip to be electrically connected.

According to a third aspect of the present invention, there is further provided a reflective liquid crystal display device, wherein the uppermost interlayer insulating film having a flat upper surface is laminated on the flat surface of the uppermost interlayer insulating film. Metal with high hardness and a thickness of 0.5
a chip having an uppermost wiring layer having a predetermined pattern of not more than μm and a passivation film having a mirror-like flat surface laminated on the uppermost wiring layer, or an uppermost layer having an upper surface formed flat and having chip protection properties A chip having an insulating film, an uppermost wiring layer made of a material having a property resistant to corrosion laminated on the flat surface of the uppermost interlayer insulating film, and being driven by the chip provided on the chip By providing a reflective liquid crystal section, the fourth problem has been solved.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a preferred embodiment of the first invention, the uppermost insulating film which is made thin and has a mirror-like flat surface is a passivation film. 1) The uppermost interlayer insulating film is flattened by CMP, and (2) The uppermost wiring layer is not made of an Al-based material but made of a metal having a higher hardness than that of an Al-based material. Form.

When performing CMP for forming a passivation film, first, a first insulating film having a sufficiently lower polishing rate than the second insulating film to be polished is deposited, and a second insulating film is formed thereon. Is deposited about twice the thickness of a thin conductive film made of a film having a hardness higher than that of the Al-based material, and the second insulating film is polished by CMP using the first insulating film having a low polishing rate as a stopper. I do.

Further, when the above-mentioned CMP is performed, a minute defect is formed on the surface to be polished, so that a thin insulating film is further deposited on the passivation film in order to ensure the insulating property of the passivation film.
When the passivation film is formed in this way, since the uppermost wiring layer cannot be die-bonded, a lower wiring layer is drawn out to form a bonding pad.

Hereinafter, a more specific embodiment of the first invention applied to the case of four-layer wiring will be described in detail with reference to the drawings. Note that the present invention is characterized by the stacked structure of the chips included in the semiconductor device, and therefore, the description will focus on the wiring process related thereto. Here, a MOS type semiconductor device is taken as an example, but this is not always necessary.

FIGS. 1 to 8 show the first embodiment according to the first invention.
FIG. 7 is a partial cross-sectional view for explaining the method for manufacturing the semiconductor chip according to the embodiment; In FIG. 1, a first interlayer insulating film 114, a second interlayer insulating film 116, and a third interlayer insulating film 116 are formed on a semiconductor substrate 110 made of, for example, Si, on which a source and a drain constituting the element are formed, via a LOCOS 112. Insulating film 1
18 on the first interlayer insulating film 114, a first wiring layer 122 via a via hole to a lower gate electrode 120, and a second wiring layer 122 on the second interlayer insulating film 116. The second wiring layers 124 are shown in a stacked state. Here, the steps up to the step of laminating the third interlayer insulating film 118 are shown.

Incidentally, specifically, the first interlayer insulating film 114
Is NSG (Non-doped Silicon Glass) and BPSG (Boron Phosphorous Silicon Glass) on it.
ss), and the second and third interlayer insulating films 116 and 118 are both TEOS (Tetra Eth).
yl Ortho Silicone) as a raw material
(Hereinafter also referred to as p-TEOS). The gate electrode 120 is made of polysilicon (p
-Si), and the first and second wiring layers 122 and 124 are formed of an Al-Si alloy (although not limited to this), which is an Al-based material. Then, as shown in FIG.
For example, Al-Si is deposited as a third layer metal on the third interlayer insulating film 118, and the third layer metal is patterned by an appropriate method to form a third wiring layer 126. The third wiring layer 126 has a thickness sufficient for bonding, for example, 0.5 μm, because a part of the third wiring layer 126 is used as the bonding pad 126A.
Up to the state shown in FIG. 2, it can be manufactured according to a conventional method.

Next, a fourth interlayer insulating film (uppermost interlayer insulating film) 128 shown in FIG. 3 is formed. This may be formed by any method. For example, the p-TE
An OS is deposited to a thickness of 1.4 μm (not shown), and the thick silicon oxide is polished to a thickness of 0.7 μm using a CMP method to a thickness indicated by a broken line in FIG. Next, an insulating film 128A made of p-TEOS is further deposited thereon by 0.2 μm,
To form a fourth interlayer insulating film 128 having a flat surface. Thereafter, via holes 130 are formed by a conventional method, and the state shown in FIG. 3 is obtained.

At this time, no via hole is formed in the fourth interlayer insulating film 128 in the region (the right side in the drawing) of the third wiring layer 126 that becomes the bonding pad 126A. However, in some cases, the bonding pad 126
A via hole may be formed in the region A, but here, a step in a large region is not formed because the passivation film is flattened by CMP which will be performed later.

Next, as a fourth wiring layer (uppermost wiring layer),
As a material having a higher hardness than the Al-based material,
4 μm, and subsequently, 0.1 μm of TiN is deposited thereon and patterned by an appropriate method to form a fourth wiring layer 13 electrically connected to the third wiring layer 126 as shown in FIG.
Form 2 At this time, since the TiN / Ti film is not suitable for bonding, the TiN / T
The i film is removed by etching.

Next, a passivation film is formed as a thin uppermost insulating film having a mirror-like flat surface. for that reason,
First, a silicon nitride film (hereinafter referred to as p-SiN) formed by a plasma CVD method as a first insulating film 134 is 0.3 μm.
And then p-TEO as a second insulating film 136.
S is deposited to a thickness of about 0.4 μm, and the state shown in FIG. 5 is obtained.

Next, the p-TEOS
Is polished, for example, by 0.5 μm to fill the recesses of the first insulating film 134 with p-TEOS and to form a second flat portion above the fourth wiring layer 132 as shown in FIG.
Of the insulating film 136 is substantially absent. In this step, p-SiN of the first insulating film 134 is p-TEOS
Since the polishing rate by CMP is less than half of that of the first embodiment, the first insulating film 134 can function as a stopper at the time of polishing.
A uniform flat surface mainly composed of N and having a thickness of about 0.3 μm can be stably formed by CMP.

Then, as shown in FIG. 7, p-SiN is deposited to a thickness of 0.2 μm as a third insulating film 138, and
The passivation film 140 is completed by covering and protecting the micro defects caused by P.

Through the above steps, a thin passivation film 140 of about 0.5 μm, which is made of substantially only p-SiN and has a completely flat mirror-like flat surface can be formed. Since the relative permittivity of the silicon oxide film is about 3.9 and the relative permittivity of the silicon nitride film is about 7.5, the equivalent oxide thickness is about 0.5 μm × 3.9 / 7.5 = 0.26 μm. Forming a thin passivation film.

Next, as shown in FIG. 8, an opening is formed in the insulating film on the bonding pad 126A. This is because p-SiN as the third insulating film 138 and the second interlayer insulating film 13
6, p-TEOS, and p-
It can be formed by etching SiN and p-TEOS of the fourth interlayer insulating film 128 in this order. The second p-
In the etching of TEOS, the first insulating film 134 in the bonding pad portion is slightly depressed at the time of deposition.
This is done because there is a possibility that p-TEOS may remain even after CMP in that part. FIG. 8 also shows the meaning of the hatching used to represent the cross section.

As described in detail above, according to the first embodiment, since the material having a higher hardness than the Al-based material is used as the uppermost wiring layer, the wiring layer is less likely to be deformed during the CMP, so that the first embodiment is thin. In addition, the passivation film 140 having a mirror-like flatness could be formed stably. Therefore,
On the passivation film 140, for example, the fourth wiring layer 13
When forming a capacitor having 2 as one electrode,
Since the distance between the two electrodes can be reduced and made uniform in the plane direction, a high-precision capacitor can be formed. Further, when the mirror-like flat surface of the passivation film 140 is used as a light reflecting surface, complete regular reflection can be performed.

In the first embodiment, the TiN / Ti film is used as the uppermost wiring layer. However, the present invention is not limited to this.
i, Cr, Co, Ni, Mo, W, Pt, or a silicide thereof, or a composite film of these and TiN formed thereon can be used.

The specific dimensions are not limited to those described above. The thickness of the passivation film 140 is 0.6 μm or less, and the thickness of the first insulating film 134 for forming the same is 0.4 μm.
μm or less, the thickness of the second insulating film 136 is 0.2 to 0.5 μm,
The third insulating film 138 has a preferable range of 0.1 to 0.3 μm.

The fourth wiring layer 13 made of TiN / Ti
2 is preferably 0.1 to 0.2 μm as a whole, in which case TiN is 0.07 to 0.15 μm and Ti is 0.02 to 0.2 μm.
~ 0.05 μm is preferred.

The thickness of the passivation film 140 is
It is desirable that the thickness be 0.3 μm or less in terms of the oxide film thickness based on the dielectric constant.

Although the first invention has been specifically described above, the first invention is not limited to the first embodiment, and can be variously modified without departing from the gist thereof.

For example, in the first embodiment, the first invention has been described for a passivation film, but may be for an interlayer insulating film. In this case, by placing an electrode on the interlayer insulating film, an accurate capacitor can be formed.

Next, an embodiment of the second invention will be described in detail.

FIGS. 9 to 18 are cross-sectional views of essential parts showing the features of the steps of manufacturing the semiconductor chip of the second embodiment according to the second invention in the order of the steps. Hereinafter, description will be made sequentially according to these drawings.

As shown in FIG. 9, a MOS transistor is formed on a semiconductor substrate 210 made of silicon (Si) by a usual process. This step is substantially the same as that of the conventional semiconductor chip shown in FIG.
A LOCOS 212 is stacked on the gate electrode 10 and polysilicon (p-S) is formed on the gate oxide film between the source and the drain.
The gate electrode 214 of i) is formed.

Next, as shown in FIG. 10, as the first interlayer insulating film 216, for example, 1000 to 20
NSG (Non Silicate Glass) of 00Å and BPSG (Boron Phosp) of 4000 to 8000Å
After depositing horous silicon glass and annealing at, for example, 900 to 950 ° C. for 20 to 60 minutes in order to reduce the surface step, a contact hole 216 A is opened in the first interlayer insulating film 216.

Next, as shown in FIG. 11, a first wiring layer 218 is formed on the first interlayer insulating film 216 by, for example, 0.4 mm.
An Al-Si alloy layer having a thickness of about 1.0 μm is deposited by sputtering, and is formed by patterning the layer by a known method.

Subsequently, a second interlayer insulating film is formed.
For this purpose, first, as shown in FIG.
A silicon oxide film (hereinafter, referred to as a p-TEOS film) 220 deposited by plasma CVD using S (Tetra Ethyl Ortho Silicon) as a raw material is approximately 1.0 to 2.0.
It is formed with a thickness of μm. And CMP (Chemical M)
The surface is flattened by polishing the p-TEOS film 220 by about 0.5 to 1.0 μm by an mechanical polishing method (however, a state immediately after the flattening is not shown). Is). This p-TEOS film 2
The surface of the surface 20 is flattened when another device or the like is adhered on the completed chip and electrically connected to each other to ensure the contact by flattening the surface.

Then, the p-TEOS film 220 having been flattened is applied with a chip protection film 221 of about 0.2 to 0.8.
By depositing p-SiN having a thickness of μm, as shown in FIG. 13, a second interlayer insulating film (uppermost interlayer insulating film) having a two-layer structure including a p-TEOS film 220 and a chip protection film 221
Form 222. The p-SiN deposited here is a material widely used as a chip protection film in a normal semiconductor.

As described above, also in the present embodiment, the chip protection film 221 is formed of p-SiN, and the inside of the chip inside the chip protection film 221 is protected. That is, by laminating the protective film 221, chip protection is imparted to the second interlayer insulating film.

Next, as shown in FIG. 14, a via hole 224 penetrating through the second interlayer insulating film 222 and reaching the first wiring layer 218 is opened at a predetermined position.

Thereafter, as shown in FIG. 15, a second wiring layer (uppermost wiring layer) 226 is formed. This means that about 0.02 to 0.1 μm of Ti (titanium) is placed inside the via hole 224 together with the entire surface of the second interlayer insulating film 222, and then about 0.05 to 0.20 μm of TiN ( After depositing titanium nitride) to form a conductive film having a two-layer structure of TiN / Ti, the conductive film is further patterned by a known method.

In the present embodiment, the second wiring layer 226 is left bare. Thus, TiN / T
The reason why the conductive film made of i is used as a material for wiring exposed on the chip surface is that it is superior in corrosion resistance as compared with an Al-Si alloy or the like.

FIG. 15 shows a state in which the second wiring layer 226 has been formed.
The conduction between the second wiring layer 226 and the first wiring layer 218 is achieved. In the case of a normal chip, an insulating film serving as a protective film such as p-SiN is formed on the second wiring layer 226 which is the uppermost wiring layer. In the present embodiment, such a protective film is used. Does not form.

As described in detail above, in the present embodiment, the second wiring layer 226 made of a material having excellent corrosion resistance is formed as the uppermost wiring layer, and the chip is formed on the second interlayer insulating film 222 immediately below the second wiring layer 226. Since the protection property is provided, the inside of the chip can be reliably protected, and corrosion can be prevented even when the second wiring layer 226 is exposed, so that the reliability of the semiconductor device can be ensured. The device can be directly connected and electrically connected. As described above, as an apparatus (component) directly attached to a chip, for example, there is a liquid crystal that is attached via the dielectric reflection film using the second wiring layer 226 as an electrode.

Therefore, according to the present embodiment, it is possible to provide a highly reliable semiconductor device having excellent corrosion resistance while being able to electrically connect other components and devices directly on the chip.

In the second embodiment, as the material used for the uppermost wiring layer, Ti and Ti formed thereon are used.
Although a two-layer film with N was used, the present invention is not limited to this.
Other materials can be used.

Corrosion can be roughly divided into dry corrosion (mainly oxidation).
And corrosion by aqueous solution. The ease of metal oxidation is determined by the free energy at the time of forming the oxide, and the more negative the free energy, the more easily the metal is oxidized. This value is A
metals that are larger than 1 and hardly oxidized include Ti, Cr, C
o, Ni, Mo, Ag, W, Pt, Au and the like. Corrosion due to an aqueous solution is caused by elution of metal atoms as ions. When two metals are placed in the electrolyte and electrically connected, the metal on the anode side is ionized and moves to the cathode side,
Electrons generated by ionization on the anode side flow to the cathode side through an external connection, and reduce hydrogen ions to generate OH- ions. The work required to transfer electrons from the anode to the cathode is the change in free energy ΔG associated with this reaction. ΔG is proportional to the standard electrode potential E, and the more anodic the metal is, the more likely it is to be corroded. Examples of metals that have a smaller value of E showing the ionization tendency than Al and are less likely to corrode include Ti, Cr, Co, and N.
i, Mo, Ag, W, Pt, Au and the like. Therefore the second
These metals can be used as the corrosion-resistant material of the embodiment.

Here, in the second embodiment, unlike the first embodiment, after forming the uppermost wiring layer, the CMP step is not used, so that even if a soft metal such as Ag or Au is used, there is no problem. Absent. Further, TiN and W are very resistant to corrosion.
A wiring in which at least the upper surface of a wiring including a system material or the like is covered with TiN or W can also be used.

Next, a third embodiment according to the second invention will be described.

FIG. 16 is a partial cross-sectional view showing one of the steps of manufacturing the semiconductor chip of the third embodiment. The state of this cross-sectional view is on the second wiring layer 226 of the second embodiment. And a step of laminating a normal insulating film 228 made of silicon oxide by a known method.

After the above steps, the insulating film 228 is etched back to a substantially same height as the second wiring layer by a known method, and the step formed as a result of the patterning of the second wiring layer 226 is also reduced. The semiconductor chip of the third embodiment having the cross-sectional shape shown in FIG. 17 is obtained by flattening the remaining insulating film 228A.

In the present embodiment, basically, the insulating film 228A does not exist on the second wiring layer 226 except above the via hole 224. However, in this case, as long as it can be electrically connected to another device or the like, some insulating film may remain on the second wiring layer 226.

FIG. 18 is a partial sectional view showing a main part of a semiconductor chip of a fourth embodiment according to the second invention. This chip is formed by bonding pads to the chip of the second embodiment shown in FIG. 230 is added. FIG. 18 also shows the meaning of the hatching used to represent the sectional view.

In the present embodiment, similar to the second embodiment,
For the exchange of electrical signals with the outside, it is assumed that the uppermost wiring layer of the chip is exposed and that it is directly electrically connected to other external devices. Bonding can also be performed. However, since bonding is difficult with TiN / Ti constituting the second wiring layer 226 which is the uppermost wiring layer, the metal layer of the bonding pad portion is formed simultaneously when the lower first wiring layer is formed. The bonding pad 230 is formed by opening the second interlayer insulating film 222 thereabove.

Although the second invention has been specifically described above, the second invention is not limited to those shown in the second to fourth embodiments, and can be variously modified without departing from the gist thereof. It is.

For example, in the above embodiment, the p-TEOS film 220 constituting the second interlayer insulating film 222 is formed by the CMP method.
Although the case where the surface is flattened by the method is shown, the present invention is not limited to this, and the polishing is not necessarily required.

The case where the chip protective film 221 is covered on the surface of the second interlayer insulating film 222 in order to impart chip protection to the second interlayer insulating film 222 is shown.
It may be made of a material having chip protection.

Next, a fifth embodiment according to the third invention will be described in detail.

FIG. 19 is a sectional view showing the structure of a reflection type liquid crystal display device according to the fifth embodiment.

In this embodiment, a P + buried region 312 and an N + buried region 314 are formed, for example, by buried epitaxial on a P-type silicon semiconductor substrate 310, and a P well 316 and an N well are respectively formed thereon. 31
8 are formed. The P well 316 and the N well 31
8 are separated by, for example, a LOCOS 320. On each of the wells 316 and 318, the source region 32 is provided.
2. By forming the drain region 324 and the gate electrode 326, high breakdown voltage transistors are formed in a matrix.

On the first interlayer insulating film 330 covering the transistor portion, a first wiring layer 332 made of, for example, an aluminum (Al) -based material is formed. The first wiring layer 332
A second wiring layer 336 made of, for example, an Al-based material is formed on the second interlayer insulating film 334 that covers the semiconductor device. The second wiring layer 3
A third wiring layer 340 made of, for example, an Al-based material is formed on the third interlayer insulating film 338 that covers the third interlayer insulating film 338. Fourth interlayer insulating film (uppermost interlayer insulating film) 34 covering third wiring layer 340
The surface of No. 2 is polished and flattened by the CMP method according to the first invention, and has chip protection properties according to the second invention.
A fourth wiring layer (uppermost wiring layer) 344 made of a material is formed. The fourth wiring layer 344 serves as a liquid crystal pixel electrode layer disposed on the chip, on which a chip protection film (the uppermost insulating film of the first invention) 346 can be formed. Further, since TiN is a material resistant to corrosion as in the embodiment of the second invention, it is not necessary to form a chip protection film. Furthermore, after forming the uppermost wiring layer 344 as in the third embodiment, an insulating film such as silicon oxide is deposited, the insulating film is removed to substantially the same height as the uppermost wiring layer, and the space between the uppermost wiring is removed. The chip surface may be planarized by forming the insulating film.

A liquid crystal driving chip 348 is formed from the semiconductor substrate 310 to the chip protection film 346 (or to the fourth wiring layer 344 when the chip protection film is not formed). The liquid crystal unit 350 is disposed at the bottom. Specifically, the liquid crystal unit 350 is formed of a protective film (or a fourth wiring layer 344) of the mirror-finished chip 348.
A dielectric reflection film 352 having a flattened reflection surface for reflecting incident light formed thereon, a transparent electrode 354 disposed on the dielectric reflection film 354 at intervals, and the dielectric reflection film 35
A liquid crystal 356 sealed between the second electrode and the transparent electrode 354;
It is configured using a glass 358 for protecting the liquid crystal disposed on the transparent electrode unit 354. Here, for the dielectric reflection film 352, for example, titanium oxide formed by an electron beam evaporation method is used. Titanium oxide has a high refractive index and is suitable for use as a light reflection film. However, titanium oxide is a porous film, has poor insulation properties, and does not function as a chip protection film.

In this liquid crystal display device, when the S-polarized light incident from the glass surface in the direction of arrow A is reflected again by the flattened dielectric reflection film 352 toward the surface, the reflected light of the S + P polarization is reflected. Is changed by changing the driving state of the transistors formed in a matrix for each pixel on the chip 348 to change the arrangement state of the liquid crystal, thereby forming an image.

A chip 348 employing the first and second inventions
Other configurations and operations are the same as those of the known Si chip-based liquid crystal, and a detailed description thereof will be omitted.

In this embodiment, the first and second
Although the invention has been applied to the reflection type liquid crystal display device, the application object of the first and second inventions is not limited to this.

[0079]

According to the first aspect of the present invention, it is possible to provide a semiconductor chip in which a thin insulating film having a mirror-like flat surface whose surface is extremely flat is formed on the uppermost wiring layer.

According to the second aspect of the present invention, there is provided a semiconductor chip excellent in corrosion resistance, in which other parts and devices can be electrically connected directly to the chip and the inside of the chip is sufficiently protected. can do.

Further, according to the third invention, it is possible to provide a reflective liquid crystal display device formed integrally with the chip.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view showing a process of forming up to a third interlayer insulating film in a first embodiment of the present invention.

FIG. 2 is a partial cross-sectional view showing a step of forming a third wiring in the first embodiment.

FIG. 3 is a partial cross-sectional view showing a step of forming a fourth (uppermost) interlayer insulating film, flattening the surface thereof, and forming a via hole in the first embodiment;

FIG. 4 is a partial sectional view showing a step of forming a fourth (uppermost) wiring layer in the first embodiment;

FIG. 5 is a partial cross-sectional view showing a step of forming first and second insulating films in the first embodiment.

FIG. 6 is a partial cross-sectional view showing a step of polishing a second insulating film in the first embodiment.

FIG. 7 is a partial cross-sectional view showing a step of forming a third insulating film in the first embodiment.

FIG. 8 is a partial cross-sectional view showing a step of forming a window in a bonding pad portion in the first embodiment.

FIG. 9 is a partial cross-sectional view showing a step of forming a MOS transistor in a second embodiment of the present invention.

FIG. 10 is a partial cross-sectional view showing a step of forming a first interlayer insulating film in the second embodiment.

FIG. 11 is a partial cross-sectional view showing a step of forming a first wiring layer in the second embodiment.

FIG. 12 is a view showing a p-type semiconductor device according to a second embodiment for forming a second interlayer insulating film;
-Partial sectional view showing a step of depositing a TEOS film

FIG. 13 is a partial cross-sectional view showing a step of forming a chip protective film on a flat surface of a second interlayer insulating film in the second embodiment.

FIG. 14 is a partial cross-sectional view showing a step of forming a via hole in a second interlayer insulating film in the second embodiment.

FIG. 15 is a partial cross-sectional view showing a main part of a semiconductor chip of a second embodiment.

FIG. 16 is a partial cross-sectional view showing one manufacturing step in a third embodiment of the present invention.

FIG. 17 is a partial cross-sectional view illustrating a main part of a semiconductor device according to a third embodiment;

FIG. 18 is a partial sectional view showing a main part of a semiconductor device according to a fourth embodiment of the present invention;

FIG. 19 is a partial sectional view showing a main part of a reflective liquid crystal display device according to a fifth embodiment of the present invention.

FIG. 20 is a partial cross-sectional view for explaining a problem of the conventional method.

FIG. 21 is a partial cross-sectional view showing a main part of a conventional semiconductor device.

[Explanation of symbols]

 110, 210, 310 semiconductor substrate 112, 212, 320 LOCOS 114, 216, 330 first interlayer insulating film 116, 334 second interlayer insulating film 118, 338 third interlayer insulating film 120, 214, 326 ... Gate electrodes 122, 218, 332 ... First wiring layers 124, 226, 336 ... Second wiring layers 126, 340 ... Third wiring layers 126A, 230 ... Bonding pads 128, 222, 342 ... Top interlayer insulating films 130, 224 ... Via holes 132, 226, 344: Top wiring layer 134: First insulating film 136: Second insulating film 138: Third insulating film 140: Passivation film (top insulating film) 220: P-TEOS films 221 and 346 … Chip protection film 228… insulation film 348… chip 350… liquid crystal part 354… liquid crystal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 21/768 H01L 21/90 M (72) Inventor Masanori Iwahashi 2-3-2 Uchisaiwaicho, Chiyoda-ku, Tokyo Kawasaki Steel Corporation Tokyo Main Office (72) Inventor Makoto Mizuno 2-3-2 Uchisaiwaicho, Chiyoda-ku, Tokyo Kawasaki Steel Corporation Tokyo Main Office (72) Inventor Koji Hanihara 465 Osato-cho, Kofu City, Yamanashi Prefecture Inside Pioneer Video Corporation

Claims (5)

[Claims] 1. A semiconductor device having a chip in which a plurality of insulating films and a wiring layer are laminated on a semiconductor substrate, an uppermost interlayer insulating film having a flat upper surface, and a flat surface of the uppermost interlayer insulating film. Is formed of a metal having a higher hardness than the A1-based material, and has a thickness of 0.5 μm.
A semiconductor device, comprising: an uppermost wiring layer having the following predetermined pattern; and a passivation film having a mirror-like flat surface laminated on the uppermost wiring layer. 2. An uppermost interlayer insulating film having a flat upper surface, a layer laminated on a flat surface of the uppermost interlayer insulating film, formed of a metal having a hardness higher than that of an A1-based material, and having a thickness of 0.1 mm. 5 μm
A chip having an uppermost wiring layer having the following predetermined pattern, a passivation film having a mirror-like flat surface laminated on the uppermost wiring layer, and a reflection disposed on the chip and driven by the chip. A reflective liquid crystal display device, comprising: 3. A semiconductor device having a chip in which a plurality of insulating films and wiring layers are laminated on a semiconductor substrate, wherein the uppermost interlayer insulating film immediately below the uppermost wiring layer has chip protection, and the uppermost wiring layer is corroded. A semiconductor device characterized in that the uppermost wiring layer is substantially exposed to the chip surface by using a material that is resistant to heat. 4. An uppermost interlayer insulating film having an upper surface formed flat and having a chip protection property, and an uppermost wiring layer made of a material having a property resistant to corrosion laminated on a flat surface of the uppermost interlayer insulating film. A reflective liquid crystal display device, comprising: a chip having: a reflective liquid crystal unit provided on the chip and driven by the chip. 5. A method of manufacturing a semiconductor device having a chip in which a plurality of insulating films and wiring layers are stacked on a semiconductor substrate, wherein a step of flattening the deposited insulating material to form an uppermost interlayer insulating film; Forming an uppermost wiring layer having a predetermined pattern on the flat surface of the uppermost interlayer insulating film; and forming an uppermost insulating film having a mirror-like flat surface on the entire substrate on the uppermost wiring layer. A method for manufacturing a semiconductor device, comprising: