JPH1090349A - Semiconductor device for evaluation and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need of repeating heat-resistance stress evaluation and to quantitatively estimate the service life of metallic wiring to be evaluated when the wiring is actually used by burying an index test piece and the metallic wiring in the resin of a semiconductor chip and performing arithmetic operation on the data obtained when the resin is heat-treated. SOLUTION: An index test piece 5 having an already known fatigue characteristic is supported by a frame 3 and metallic wiring 6 to be estimated is provided on the interlayer insulating film 8 of a semiconductor chip 9. Then the test piece 5 and wiring 6 are buried in the corner section 2a of a sealing resin body 2 by varying the distances to the piece 5 and wiring 6 from the center of the chip 9 from each other. Then the resin body 2 is expanded and shrunk by performing temperature cycle tests on the device. When the piece 5 is disconnected or the wiring 6 short-circuits, the distance to the disconnected spot of the piece 5 or short-circuiting spot of the wiring 6 from the center of the chip 9 and the number of the expanding and shrinking cycles until the piece 5 is disconnected or the wiring 6 short-circuits are detected. Then the stress distribution curve which acts on the resin body 2 is calculated based on the data of the piece 5 and the fatigue characteristic. Then the service life of the wiring 6 is estimated by calculating the fatigue characteristic of the wiring 6 from the curve.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device for evaluation and a test method thereof.

[0002]

2. Description of the Related Art A semiconductor chip is covered with a sealing resin and hermetically sealed. In a semiconductor chip having this structure, with the miniaturization of wiring, the increase in chip size, the type of hermetic sealing resin, and the like, The stress due to the temperature difference is applied to the corner of the semiconductor chip, and there is a possibility that the wiring located at the corner of the semiconductor chip slides and is broken, which often causes an accident. Therefore, it is necessary to evaluate the slide breakdown of the wiring at the corner of the semiconductor chip.

Conventionally, a method for evaluating heat stress at a corner portion of a semiconductor chip is disclosed in JP-A-2-179486 and JP-A-7-235578.

As shown in FIG. 7, a method for evaluating heat stress disclosed in Japanese Patent Application Laid-Open No. 2-179486 is used as an evaluation semiconductor chip, which is parallel to two sides of a chip 22 and perpendicular to a diagonal line of the chip. A chip in which the L-shaped metal wiring 1 that is bent to be bent repeatedly at a constant interval P from the corner 22a of the chip 22 toward the center is used, and the wiring width of the chip and the gap P between adjacent wirings are used. The chip size is changed variously, and various factors for the crack of the interlayer insulating film provided below the metal wiring 20 and the sliding of the metal wiring 1 are evaluated according to the change of the thermal stress (shear stress) of the hermetic sealing resin. Was.

In the heat stress evaluation method disclosed in Japanese Patent Application Laid-Open No. Hei 7-235578, as shown in FIG. 8, wirings 20 and 21 are vertically stacked on a corner 22a of a semiconductor chip 22 via an interlayer insulating film. The evaluation was performed by electrically detecting that the wirings 20 and 21 were short-circuited through cracks in the interlayer insulating film due to the stress of the formed and hermetic sealing resin.

[0006]

However, the heat stress evaluation methods shown in FIG. 7 and FIG. 8 are all based on the material of the hermetic sealing resin, the resin thickness, the diffusion process, the chip size,
Since the behavior due to the sliding of the metal wiring cannot be predicted every time the ambient temperature condition is changed, there is a problem that the evaluation must be performed again.

It is considered that the reason is that the fatigue characteristics of the semiconductor chip, which is considered to mainly govern the life of the metal wiring to the slide, are not quantitatively evaluated.

It is an object of the present invention to provide a semiconductor device for evaluation which eliminates the need for repetition of heat stress evaluation accompanying a change in diffusion process, resin material, etc., and which quantitatively predicts the slide life of metal wiring in actual use. An object of the present invention is to provide a test method.

[0009]

In order to achieve the above object, an evaluation semiconductor device according to the present invention comprises: a sealing resin body;
An index test piece and an evaluation semiconductor device having an evaluation metal wiring, wherein the sealing resin body covers the semiconductor chip,
The index test piece is subjected to stress deformation due to heat, has a known fatigue property, is embedded in the sealing resin body at a different distance from the center of the semiconductor chip and receives stress, and is used for evaluation. The metal wiring is provided on the interlayer insulating film of the semiconductor chip, is embedded in the sealing resin body at a different distance from the center of the semiconductor chip, and receives a stress.

Further, the semiconductor device for evaluation according to the present invention comprises:
An evaluation semiconductor device having a pair of sealing resin bodies, an index test piece, and a metal wiring for evaluation, wherein the pairing sealing resin bodies are made of the same resin material and are stress-deformed by heat. The index test piece has a known fatigue property, is supported by a frame embedded in the one sealing resin body, and is different in the distance from the center of the sealing resin body. The metal wiring for evaluation is embedded in the body and receives stress, and the metal wiring for evaluation is provided on the interlayer insulating film of the semiconductor chip embedded in the other sealing resin body, and has a different distance from the center of the semiconductor chip. It is embedded in the sealing resin body and receives stress.

Further, the method of testing an evaluation semiconductor device according to the present invention includes performing a heat treatment, a data detection process, a stress calculation process, and a characteristic calculation process to test the evaluation semiconductor device. In a test method, an evaluation semiconductor device includes an index test piece having known fatigue characteristics and a metal wiring to be evaluated embedded in a resin body for encapsulating a semiconductor chip, and a stress due to thermal deformation of the resin body is used as an index. The heat treatment is a process of performing a temperature cycle test on the semiconductor device for evaluation to expand and contract the sealing resin body, and the data detection process is a process of the temperature cycle test described above. As a result, the distance data from the center of the semiconductor chip of the broken index test piece, the number of cycles of expansion and contraction, and the distance data of the shorted metal wiring from the center of the semiconductor chip were evaluated. Data, and a process for detecting expansion and contraction of the number of cycles and, respectively, the stress calculation process, the data of the indicator test pieces obtained in the data detection process,
Based on the known fatigue characteristics of the index test piece, is a process of determining a stress distribution curve acting on the sealing resin body, the characteristic calculation process, the stress distribution curve and the known fatigue characteristics of the index test piece and This is a process of calculating the fatigue characteristics of the metal wiring to be evaluated based on the above, and generalizing it as a life estimation formula.

Further, the stress distribution curve is determined by using the following maximum stress estimation formula. σ = G · {Z · (α ₁ −α ₂ ) · ΔT} · W / t where σ is the resin shear stress, G is the resin rigidity, and Z is the corner of the sealing resin body from the center of the semiconductor chip. the distance to, alpha ₁ is expansion coefficient of the sealing resin member, alpha ₂ is the expansion coefficient of the interlayer insulating film where the metal wiring to be evaluated is provided, [Delta] t is the ambient temperature difference, t is the resin thickness of the sealing resin member, W represents the width of the metal wiring to be evaluated.

[0013] The life estimation equation is expressed as follows. lnN = A−c · lnσ where N is the number of expansion / contraction cycles, A is the intercept obtained from the stress distribution curve, σ is the acting stress, and c is the gradient of the stress distribution curve.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1A is a cross-sectional view showing an evaluation semiconductor device according to Embodiment 1 of the present invention.
FIG. 2B is a vertical sectional view taken along line AA ′ of FIG.

As shown in the figure, the semiconductor device for evaluation according to the first embodiment of the present invention includes a sealing resin body 2 and an index test piece 5.
And a metal wiring 6 for evaluation.

The sealing resin body 2 is made of a resin that covers the semiconductor chip 9 and hermetically seals it, and undergoes stress deformation by heat.

The index test piece 5 has a known fatigue property,
It is supported by the frame 3 embedded in the sealing resin body 2 and is embedded in the corner portion 2a of the sealing resin body 2 at different distances from the center of the semiconductor chip 9 to receive stress. Is provided with a detection terminal 1 by a bonding wire 4. The detection terminal 1 protrudes from the sealing resin body 2 to the outside.

The evaluation metal wiring 6 is provided on the interlayer insulating film 8 of the semiconductor chip 9, is embedded in the corner 2 a of the sealing resin body 2 at different distances from the center of the semiconductor chip 9, and reduces stress. The detection terminal 1 is provided on the bonding pad 7 of the wiring 6. Detection terminal 1
Project outside from the sealing resin body 2.

Further, the method for testing a semiconductor device for evaluation according to the present invention performs a heat treatment, a data detection process, a stress calculation process, and a characteristic calculation process to test the semiconductor device for evaluation.

As described above, in the semiconductor device for evaluation, the index test piece 5 having known fatigue characteristics and the metal wiring 6 to be evaluated are embedded in the resin body 2 for sealing the semiconductor chip 9. Is applied to the index test piece 5 and the metal wiring 6.

The heat treatment is a process in which a temperature cycle test is performed on the semiconductor device for evaluation to expand and contract the sealing resin body. The data detection process is a process in which the index test piece that is disconnected as a result of the temperature cycle test is performed. This is a process of detecting distance data from the center of the semiconductor chip and the number of cycles of expansion and contraction, and distance data from the center of the semiconductor chip of the shorted metal wiring to be evaluated and the number of cycles of expansion and contraction, respectively. The calculation process is a process of determining a stress distribution curve acting on the sealing resin body based on the data of the index test piece obtained in the data detection process and the known fatigue characteristics of the index test piece, In the characteristic calculation process, the fatigue characteristic of the metal wiring to be evaluated is determined based on the stress distribution curve and the known fatigue characteristic of the index test piece, and is calculated as a life estimation equation (2). It is a process of generalization.

The stress distribution curve is calculated using the following maximum stress estimation formula (1). σ = G · {Z · (α ₁ −α ₂ ) · ΔT} · W / t (1) where σ is the resin shear stress, G is the resin rigidity, and Z is the sealing resin body from the center of the semiconductor chip. the distance to the corners, alpha ₁ is expansion coefficient of the sealing resin member, alpha ₂ is the expansion coefficient of the interlayer insulating film where the metal wiring to be evaluated is provided, [Delta] t is the ambient temperature difference, t is the sealing resin body The resin thickness W represents the width of the metal wiring to be evaluated.

The life estimation equation (2) is expressed as follows. lnN = A−c · lnσ (2) where N is the number of cycles of expansion and contraction, A is an intercept obtained from the stress distribution curve, σ is an applied stress, and c is a gradient of the stress distribution curve.

Next, a test method of the semiconductor device for evaluation according to the first embodiment of the present invention will be described using a specific example.

First, the semiconductor device for evaluation shown in FIG. 1 is put into a temperature cycle bath which can be electrically monitored. The electrical monitor is performed according to the timing chart of FIG. 3 in order to detect a disconnection of the index test piece 5 and a short circuit of the evaluation metal wiring (specifically, aluminum wiring) 6.

As shown in FIG. 3, in step 1, using the semiconductor device for evaluation shown in FIG. 1, a temperature cycle test is performed on the semiconductor device for evaluation in accordance with the timing chart of FIG. Shrink (heat treatment).

In steps S2 and S3, disconnection of the test piece 5 and short-circuit of the aluminum wiring for evaluation 6 are monitored by the detection terminals 1 and 1 during the temperature cycle test,
As a result of the temperature cycle test, the distance data from the center of the semiconductor chip 9 of the broken index test piece 5, the number of cycles of expansion and contraction, and the center of the semiconductor chip 9 of the metal wiring 6 to be short-circuited were evaluated. Is detected (data detection process), and the characteristic diagram of FIG. 5 is drawn. In FIG. 5, the horizontal axis indicates distance data (InZ) from the center of the semiconductor chip 9 and the vertical axis indicates the number of expansion / contraction cycles (InN ₅₀ ).

Next, in step S4, the data of FIG. 5 is substituted into the maximum stress estimating equation (1) to obtain FIG. 6 for each of the aluminum wiring 6 for evaluation and the index test piece 5. When it matches the known fatigue characteristic curve of the index test piece 5,
This is the basis for the normal application of the stress (step S5). In step S6, an action is applied to the sealing resin body 2 based on the data of the index test piece 5 obtained in the data detection process (FIG. 5) and the known fatigue characteristics of the index test piece 5 (FIG. 6). A stress distribution curve (FIG. 7) is calculated (stress calculation processing).

The stress distribution curve is calculated using the following maximum stress estimation formula (1). σ = G · {Z · (α ₁ −α ₂ ) · ΔT} · W / t (1)

Next, in step S7, based on the stress distribution curve and the known fatigue characteristics of the index test piece 5,
The fatigue characteristics of the metal wiring to be evaluated are determined and generalized as a life estimation equation (2) (characteristic calculation processing).

Since the fatigue characteristic curve of the index test piece 5 is known as shown in FIG. 6, the stress distribution curve in the sealing resin body 2 is obtained as shown in FIG.

Next, since the relationship between the short-circuit cycle of the aluminum wiring for evaluation (metal wiring 6) and the position is also obtained from the above data as shown in FIG. 5, the fatigue characteristic curve of the index test piece 5 and the relationship shown in FIG. A fatigue characteristic curve of the aluminum wiring for evaluation (metal wiring 6) is obtained by combining the stress distribution curve and the stress distribution curve, and generalized as a life estimation equation (2). This can be considered unique to the diffusion process.

Next, the resin-encapsulated semiconductor device (the resin thickness,
The diffusion process is the same. The maximum acting stress is obtained by the maximum stress estimation formula (1) from the linear expansion coefficient, the rigidity, the size of the semiconductor chip to be used, and the difference in the actual use environment temperature, which are the resin characteristics of (1). In step S9, the life of the aluminum slide in actual use is obtained from the maximum acting stress and the life estimation formula (2). Therefore, the life of the aluminum slide in the actual use environment can be estimated without re-evaluating.

When the resin thickness of the sealing resin body and the diffusion process are different, the evaluation is performed again according to the test method according to the present invention. If only the resin thickness of the sealing resin body is different, the maximum stress estimation formula (1) may be corrected by correcting only the fatigue characteristic curve of the index test piece to correct the effect of the change in the resin thickness.

(Embodiment 2) FIGS. 2A and 2B are cross-sectional views showing an evaluation semiconductor device according to Embodiment 2 of the present invention.

As shown in FIG. 2, the evaluation semiconductor device according to the second embodiment of the present invention includes a pair of sealing resin bodies 2 and 2, an index test piece 5, and a metal wiring 6 for evaluation. I have.

The pair of sealing resin bodies 2a and 2b are made of the same resin material and undergo stress deformation by heat. The resin material of the pair of sealing resin bodies 2a and 2b is:
It is used as a resin for hermetically sealing the semiconductor chip 9 shown in FIG.

As shown in FIG. 2A, the index test piece 5
Has a known fatigue characteristic, is supported by the frame 3 embedded in the sealing resin body 2a, and is embedded in the sealing resin body 2a at a different distance from the center of the sealing resin body 2a. And receive stress. This structure corresponds to the sealing resin body 2
This is a TEG-A type specialized for obtaining a stress distribution in a.

As shown in FIG. 2B, the evaluation metal wiring 6 is provided on the interlayer insulating film of the semiconductor chip 8 buried in the other sealing resin body 2b, and extends from the center of the semiconductor chip 9. It is embedded in the sealing resin body 2b at different distances to receive stress. This structure is a TEG-B type specialized for obtaining the fatigue characteristics of the metal wiring 6 for evaluation.

Using the separated evaluation semiconductor devices shown in FIGS. 2A and 2B, the life estimation formula (2) is obtained, and it is considered that the life of the metal wiring with respect to the slide is mainly controlled. The point of quantitatively evaluating the fatigue characteristics of the semiconductor chip is the same as the case where the test is performed using the evaluation semiconductor device of Embodiment 1 shown in FIG. When it is desired to obtain only the stress distribution characteristics inside the semiconductor device, an evaluation semiconductor device shown in FIG. 2B may be used, and an evaluation semiconductor using a sealing resin body coated with the semiconductor chip 9 shown in FIG. There is an advantage that the apparatus does not need to be used, and the cost can be reduced as compared with the first embodiment.

[0042]

As described above, according to the present invention, it is not necessary to repeat the evaluation of the heat resistance of the resin-encapsulated semiconductor device due to the diffusion process and the change of the resin material, and the life of the aluminum slide in actual use can be quantitatively determined. Can be estimated.

According to the present invention, a life estimation formula for estimating the fatigue of a semiconductor chip can be obtained from data of a monitor temperature cycle test performed on the evaluation semiconductor device of the present invention. It is possible to quantitatively estimate the life of the metal wiring required for a resin-encapsulated semiconductor device having a different material and a different semiconductor chip size without re-evaluation.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view showing an evaluation semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG.
It is a line longitudinal cross-sectional view.

FIGS. 2A and 2B are cross-sectional views illustrating an evaluation semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a flowchart showing a test method of the semiconductor device for evaluation according to the embodiment of the present invention.

FIG. 4 is a timing chart showing a temperature cycle test performed on an evaluation semiconductor device.

FIG. 5 shows the results of a temperature cycle test performed on a semiconductor device for evaluation. As a result, the distance data and the number of cycles of expansion and contraction of the broken index test piece, the distance data and the expansion and contraction of the shorted metal wiring to be evaluated are shown. FIG. 6 is a characteristic diagram showing the number of cycles.

FIG. 6 is a characteristic diagram showing a known fatigue characteristic curve of an index test piece.

FIG. 7 is a plan view showing a conventional example.

FIG. 8 is a plan view showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Detection terminal 2 Sealing resin body 3 Frame (insulating material) 4 Bonding wire 5 Index test piece 6 Evaluation metal (aluminum) wiring 7 Bonding pad 8 Interlayer insulating film 9 Semiconductor chip

Claims (5)

[Claims] 1. An evaluation semiconductor device having a sealing resin body, an index test piece, and a metal wiring for evaluation, wherein the sealing resin body covers a semiconductor chip and undergoes stress deformation by heat. The index test piece has a known fatigue property, is embedded in the sealing resin body at a different distance from the center of the semiconductor chip and receives stress, and the metal wiring for evaluation is the semiconductor chip. The semiconductor device for evaluation is provided on the interlayer insulating film, and is embedded in the sealing resin body at a different distance from the center of the semiconductor chip to receive stress. 2. An evaluation semiconductor device comprising a pair of sealing resin bodies, an index test piece, and a metal wiring for evaluation, wherein the pair of sealing resin bodies are made of the same resin material and are made of heat. The indicator test piece has a known fatigue property, is supported by a frame embedded in the one sealing resin body, and has a different distance from the center of the sealing resin body. The metal wiring for evaluation is provided on the interlayer insulating film of the semiconductor chip buried in the other sealing resin body and receives a stress from the center of the semiconductor chip. An evaluation semiconductor device, which is embedded in the sealing resin body at different distances and receives stress. 3. A method for testing an evaluation semiconductor device, comprising: performing a heat treatment, a data detection process, a stress calculation process, and a characteristic calculation process, and performing a test on the evaluation semiconductor device. An index test piece with known fatigue characteristics and a metal wiring to be evaluated are embedded in a resin body that encapsulates a semiconductor chip, and the stress due to thermal deformation of the resin body is applied to the index test piece and the metal wiring. The heat treatment is a process of performing a temperature cycle test on the semiconductor device for evaluation and expanding and contracting the sealing resin body. The data detection process is a process of performing the temperature cycle test on the semiconductor device of the disconnected index test piece. Distance data from the chip center, the number of cycles of expansion and contraction, and distance data from the semiconductor chip center of the shorted metal wiring to be evaluated;
And the number of cycles of expansion and contraction, respectively.The stress calculation processing is based on the data of the index test piece obtained in the data detection processing and the known fatigue characteristics of the index test piece. Is a process of calculating a stress distribution curve acting on the sealing resin body.The characteristic calculation process is based on the stress distribution curve and the known fatigue characteristics of the index test piece, and evaluates the fatigue characteristics of the metal wiring to be evaluated. A test method of an evaluation semiconductor device, which is a process of determining and generalizing a life estimation formula. 4. The stress distribution curve is calculated by using the following maximum stress estimation equation: σ = G ｛Z ｛(α ₁ -α ₂ ) ・ T｝ W / t where σ provided the resin shear stress, G is the resin shear modulus, Z is the distance from the center of the semiconductor chip to the corner portion of the sealing resin member, alpha ₁ is expansion coefficient of the sealing resin member, alpha ₂ is a metal wire to be evaluated The expansion coefficient of the obtained interlayer insulating film, ΔT is the environmental temperature difference, t is the resin thickness of the sealing resin body, and W is the width of the metal wiring to be evaluated. 4. The test method for an evaluation semiconductor device according to claim 3, wherein: 5. The life estimation equation is expressed as follows: lnN = Ac-lnσ where N is the number of expansion / contraction cycles, and A is an intercept obtained from the stress distribution curve. , Σ represents the acting stress, and c represents the gradient of the stress distribution curve. The method for testing an evaluation semiconductor device according to claim 3, wherein: