JPH1084261A - Semiconductor circuit and electric circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the size of the circuit small by decreasing number of components of the semiconductor circuit having a hysteresis characteristic. SOLUTION: A NAND circuit 103 detects a trailing edge of an L level pulse signal generated from a NAND circuit 102 when a voltage of an input signal Vin rises from 0V and reaches a ViH to make an output signal S103 transit from an L level to an H level. Furthermore, the NAND circuit 103 detects an edge when the output signal S101 from the NAND circuit 101 transits from an L level to an H level in the case that the voltage of the input signal Vin is decreased from the VDD and reaches a ViL so as to make the output signal S103 transit from an H level to an L level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor circuit and an electric circuit, and more particularly to a semiconductor circuit having a hysteresis characteristic and an electric circuit including the semiconductor circuit.

[0002]

2. Description of the Related Art FIG. 8 is a diagram showing a configuration of an ink discharge control circuit in a conventional ink jet type recording head.

A driving circuit 810 is a Schmitt circuit having a hysteresis characteristic, and has an input signal Vin (Vin).
0, Vin1,...)
20 is driven to control ink ejection. Drive circuit 810
A large number of heating elements 820 are arranged on the substrate 800.
Further, the driver circuit 810 is integrated on a semiconductor substrate.

[0004] An input signal Vin is input to a drive circuit via an input terminal 811. Reference numeral 812 denotes a rising detection unit that operates at the rising threshold value ViH of the input signal Vin;
Is the falling threshold value ViL of the input signal Vin (ViL <V
iH), a falling detector, 814 is a switch for selecting the output of the rising detector 812 or the falling detector 813, and 815 drives the heating element 820 at high speed based on the output of the switch circuit 814. Buffer section.

The input signal Vin includes a signal line, a power line,
This includes spike-like noise (eg, ground bounce) due to the impedance of the ND line and external noise. To prevent malfunction due to these noises,
The drive circuit 810 is configured by a Schmitt circuit.

FIG. 9 is a specific circuit diagram of the drive circuit 810. In the figure, the rise detection unit 812 is formed of one inverter circuit, the fall detection unit 813 is formed of two inverter circuits connected in series, and the switch unit 814 is a flip-flop formed of two NAND circuits. And the buffer unit 815 is connected in series.
It consists of two inverter circuits.

When the circuit shown in FIG. 1 is realized by a CMOS process, the number of MOS transistors is PMOS and NMO.
There are 18 S in total.

[0008]

However, in the above conventional example, since the area occupied by the drive circuit 810, that is, the Schmitt circuit, is large, for example, 1) the entire area of the substrate 800 is large, and 2) the manufacturing cost is large. high,
3) There is a problem that it is difficult to increase the density.

The present invention has been made in view of such a problem, and has as its object to reduce the number of elements of a semiconductor circuit having hysteresis characteristics and to reduce the size of the semiconductor circuit.

[0010]

According to the present invention, there is provided a semiconductor circuit having a hysteresis characteristic, wherein a voltage of an input terminal is equal to a first voltage.
A first logic circuit for detecting that the voltage of the input terminal has become lower than a threshold value, a second logic circuit for detecting that the voltage of the input terminal has become higher than a second threshold value, and detection by the first logic circuit. A third logic circuit that inverts a logic level of an output terminal based on a signal and a detection signal by the second logic circuit, wherein the first, second, and third logic circuits include:
Each of them is a sequential circuit.

In the semiconductor circuit according to the present invention, it is preferable that a signal of the third logic circuit is fed back to the first and second logic circuits.

[0012] In the semiconductor circuit according to the present invention, it is preferable that the first logic circuit is constituted by a first NAND circuit, and the second logic circuit is constituted by a second NAND circuit.

In the semiconductor circuit according to the present invention, the third logic circuit includes a third NAND circuit having outputs of the first and second logic circuits as inputs, and a third NAND circuit.
A first inverter circuit for inverting the output of the circuit;
One input of each of the first and second logic circuits is connected to the input terminal, the output of the third NAND circuit is connected to the other input of the first logic circuit, It is preferable that the output of one inverter circuit is connected to the other input of the second logic circuit.

In the semiconductor circuit according to the present invention, it is preferable that the third logic circuit further includes a second inverter circuit for inverting an output of the first inverter circuit to drive the output terminal.

In the semiconductor circuit according to the present invention, it is preferable that the first logic circuit constitutes a flip-flop together with the third logic circuit.

In the semiconductor circuit according to the present invention, the first logic circuit is constituted by a first NAND circuit, and the third logic circuit is constituted by a second NAND circuit constituting a flip-flop together with the first NAND circuit. And a drive circuit for driving the output terminal based on the output of the second NAND circuit.

In the semiconductor circuit according to the present invention, it is preferable that the second logic circuit is an inverter circuit.

An electric circuit according to the present invention comprises a plurality of the semiconductor circuits integrated on the same substrate.

An electric circuit according to the present invention includes the semiconductor circuit and a heating element connected to the output terminal of the semiconductor circuit.

An electric circuit according to the present invention comprises a plurality of the semiconductor circuits integrated on the same substrate and a heating element connected to an output terminal of each semiconductor circuit.

In the electric circuit according to the present invention, the heating element can be used for heating ink in an ink jet type image recording apparatus.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment> FIG. 1 is a circuit diagram showing a configuration of a Schmitt circuit according to a first embodiment of the present invention. The drive circuit 810 is configured by the Schmitt circuit shown in FIG.

In FIG. 1, reference numeral 101 denotes a NAND circuit having a threshold value of ViL, and reference numeral 102 denotes a threshold value of ViH (ViL <Vi).
H) is a NAND circuit. The NAND circuit 101 determines a threshold value ViL when the voltage of the input signal Vin changes from the H level to the L level, and the NAND circuit 102 determines a threshold value ViH when the voltage of the input signal Vin changes from the L level to the H level. To determine.

The signal 103 detects the falling of the output signal S102 of the NAND circuit 102, that is, the fact that the voltage of the input signal Vin exceeds the threshold value ViH of the NAND circuit 102, and changes the output signal S103 to the H level. NAND
The rising of the output signal S101 of the circuit 101, that is, the voltage of the input signal Vin is equal to the threshold value ViL of the NAND circuit 101
The output signal S103 is set to L
This is a NAND circuit that changes to a level.

Reference numerals 104 and 105 denote a NAND circuit 103
This is an inverter circuit for inverting the output signal S103 twice to drive the output terminal 107 (heating element 820).

FIG. 2 is a circuit diagram showing a configuration of a NAND circuit using CMOS. 2A shows a circuit diagram of the NAND circuit 101, and FIG. 2B shows a circuit diagram of the NAND circuit 102.

FIG. 3A shows the input / output characteristics of the NAND circuits 101 and 102. In the figure, a curve VL represents an input / output characteristic of the NAND circuit 101 and a curve VH.
Is the input / output characteristic of the NAND circuit 102 and the curve Vmid
Indicates input / output characteristics of a NAND circuit having a general threshold value (VDD / 2). As shown, the reason why the threshold values of the NAND circuits 101 and 102 are set to different values is to obtain a hysteresis characteristic. In the following, ViH =
VDD / 2 + α, ViL = VDD / 2−β (α and β are positive).

To adjust the threshold value of the NAND circuit, PM
The current driving capabilities of the OS transistor and the NMOS transistor may be adjusted. That is, when the current driving capability of the PMOS transistor is higher than that of the NMOS transistor, the threshold becomes higher. Conversely, when the current driving capability of the PMOS transistor is lower than that of the NMOS transistor, the threshold becomes lower.

The current driving capability is substantially proportional to W / L when the gate length of the MOS transistor is L and the gate width is W. Therefore, when the W / L is increased, the current driving capability increases, and when the W / L is decreased, the current driving capability decreases.

For example, regarding the NAND circuit 101,
Since it is necessary to lower the threshold value ViL relating to the change in the input signal Vin, the current driving capability of the PMOS transistor 113 is reduced by connecting the NMOS transistors 114 and 115 in series.
Needs to be smaller than the entire current driving capability of.

For example, regarding the NAND circuit 102,
Since it is necessary to increase the threshold value ViH relating to the change in the input signal Vin, the current driving capability of the PMOS transistor 117 is reduced by the series NMOS transistors 118 and 119.
Needs to be increased by an amount corresponding to α from the entire current driving capability of the above.

FIG. 4 shows the input signal Vin and the output signal Vou.
FIG. 6 is a diagram illustrating a relationship with t. Hereinafter, the operation of the Schmitt circuit will be described for each of the areas A, B, and C. Region A
Is a region where the voltage of the input signal Vin changes from 0 to ViH, and region B is a region where the voltage of the input signal Vin is changed from ViH to VH.
A region where the voltage of the input signal changes from ViL to 0 is a region where the voltage of the input signal changes from DD to DD and further to ViL.

<Area A> When the voltage of the input signal Vin is 0 V, the output signals S of the NAND circuits 101 and 102 are
101 and S102 are both at the H level, and the NAND
The output signal S103 of the circuit 103 goes low, and the output signal Vout also goes low.

The voltage of the input signal Vin rises (however, Vi
If the voltage of the input signal Vin exceeds the threshold value ViL, the signal S103 is at the L level.
The output signal S101 of the AND circuit 101 maintains the H level. Also, the voltage of the input signal Vin increases (however, Vi
(Less than H), the output signal S102 of the NAND circuit 102 is high because the threshold value of the NAND circuit 102 is ViH.
Maintain levels. However, since one input signal S104 to the NAND circuit 102 is at H level, the output signal S102 of the NAND circuit 102 changes from H level to L level when the voltage of the input signal Vin exceeds ViH.

Therefore, when the voltage of the input signal Vin rises from 0 V within a range not exceeding ViH, the two inputs to the NAND circuit 103 are both at the H level, so that the output signal S103 of the NAND circuit 103 becomes Maintain L level. As a result, the output signal Vout also maintains the L level.

<Area B> As described above, the input signal Vin
At the point when the voltage exceeds ViH, the output signal S102 of the NAND circuit 102 changes from the H level to the L level. Accordingly, one input of the NAND circuit 103 changes to the L level, and the output signal S103 of the NAND circuit 103 changes to the L level.
The state transits from the level to the H level.

Accordingly, the output signal S104 of the inverter circuit 104 changes from the H level to the L level, so that the output signal S102 of the NAND circuit 102 returns to the H level. In other words, the output signal S102 of the NAND circuit 102 detects that the voltage of the input signal Vin has risen from 0 V to ViH, and outputs an L level pulse signal (the pulse width is determined by the NAND circuits 102 and 103 and the inverter circuit 104). (Depending on the delay time).

However, the output signal S103 of the NAND circuit 103 changes to the H level as the output signal of the NAND circuit 102 changes from the H level to the L level.
Level (ie, faster than the time when the signal S102 returns to the H level), the output signal S1 of the NAND circuit 103 is output.
03 maintains the H level.

Next, a case where the voltage of the input signal Vin drops from VDD (however, a range larger than ViL) will be considered.

In this case, one input signal S104 to the NAND circuit 102 is at the L level, so that even if the voltage of the input signal Vin becomes lower than ViH,
The output signal S102 of the circuit 102 maintains the H level.

On the other hand, one input signal S103 to the NAND circuit 101 maintains the H level, but since the input signal Vin voltage is higher than ViL, the output signal S101 of the NAND circuit 101 maintains the L level. . However, when the voltage of the input signal Vin becomes lower than ViL,
The output signal S101 of the NAND circuit 101 changes to the H level.

<Area C> As described above, the input signal Vin
Becomes lower than ViL, the NAND circuit 101
Changes from the L level to the H level. At this time, the output signal S102 of the NAND circuit 102
Maintain the H level, the NAND circuit 103
Changes from the H level to the L level. Therefore, the output signal Vout also transitions to the L level.

As described above, the NAND circuit 103 detects the falling edge of the L-level pulse signal generated by the NAND circuit 102 when the voltage of the input signal Vin rises from 0 V and reaches ViH. , The output signal S103 transitions from the L level to the H level. When the voltage of the input signal Vin drops from VDD and reaches ViL, the NAND circuit 103 detects an edge at which the output signal S101 of the NAND circuit 101 transitions from the L level to the H level, and outputs the output signal S103. From the H level to the L level.

Therefore, the input / output characteristics of the Schmitt circuit are
It has a hysteresis characteristic as shown in FIG.

The Schmitt circuit according to the present embodiment shown in FIG. 1 is composed of three NAND circuits and two inverter circuits. For example, when the Schmitt circuit is composed of CMOS circuits, the number of MOS transistors is sixteen. The number of elements can be reduced as compared with the conventional Schmitt circuit.

Therefore, the drive circuit 810 can be downsized by applying this Schmitt circuit.

<Second Embodiment> FIG. 5 is a circuit diagram showing a configuration of a Schmitt circuit according to a second embodiment of the present invention. The drive circuit 810 is configured by the Schmitt circuit shown in FIG.

In the figure, reference numeral 501 denotes a threshold value of ViH
The (VDD / 2 + α) inverter circuit 502 is a NAND circuit whose threshold value is ViL (VDD / 2−β). 5
Numeral 03 denotes a NAND circuit which forms a flip-flop together with the NAND circuit 502. The inverter circuits 504 and 505 are inverter circuits for inverting the output signal S503 of the NAND circuit 503 twice and driving the output terminal 507 (heating element 820).

FIG. 6 is a circuit diagram showing a configuration of a NAND circuit and an inverter circuit using CMOS. FIG. 3A is a circuit diagram of the NAND circuit 502, and FIG. 3B is a circuit diagram of the inverter circuit 501.

The NAND circuit 502 shown in FIG.
Needs to lower the threshold value ViL relating to the change in the input signal Vin, so that the current driving capability of the PMOS transistor 601 is reduced by the serial MOS transistors 603 and 60
4 is smaller than that of the entire current drive capability by an amount corresponding to β.

The inverter circuit 501 shown in FIG.
Since it is necessary to increase the threshold value ViH for the change in the input signal Vin, the current driving capability of the PMOS transistor 605 is made larger than that of the NMOS transistor 606 by an amount corresponding to α.

FIG. 7 shows the input signal Vin and the output signal Vou.
FIG. 6 is a diagram illustrating a relationship with t. Hereinafter, the operation of the Schmitt circuit will be described for each of the areas A, B, and C. Region A
Is a region where the voltage of the input signal Vin changes from 0 to ViH, and region B is a region where the voltage of the input signal Vin is changed from ViH to VH.
A region where the voltage of the input signal changes from ViL to 0 is a region where the voltage of the input signal changes from DD to DD and further to ViL.

<Area A> When the input signal Vin is 0 V, the output signal S502 of the NAND circuit 502 is NAN.
Regardless of the level of the output signal S503 of the D circuit 503,
It becomes H level. Therefore, the H level is input to both inputs of the NAND circuit 503, so that the output signal S503 of the NAND circuit 503 becomes L level and the output signal Vout also becomes L level.

Even if the voltage of the input signal Vin rises, Vi
As long as it does not exceed H, the output signal S of the inverter circuit 501
Reference numeral 501 maintains the H level. Also, the NAND circuit 50
The output signal S502 of No. 2 maintains the H level unless the output signal S503 of the NAND circuit 503 changes to the H level. Therefore, the output signal S503 of the NAND circuit 503
Maintains the L level as long as the voltage of the input signal Vin does not exceed ViH even if the voltage of the input signal Vin increases, and the output signal Vout also maintains the L level.

<Area B> The voltage of the input signal Vin is ViH
Exceeds the output signal S501 of the inverter circuit 501.
Transitions from the H level to the L level. Therefore, NAN
The output signal S503 of the D circuit 503 is the input signal S502
Transitions from L level to H level,
The output signal Vout also transitions to the H level. At this time, the output signal S502 of the NAND circuit 502 is such that the voltage of the input signal Vin is higher than ViL and the input signal S5
Since 03 is at the H level, a transition is made from the H level to the L level.

Next, consider the case where the voltage of the input signal Vin drops from VDD (however, a range larger than ViL).

First, the voltage of the input signal Vin decreases, and V
When it becomes lower than iH, the output signal S501 of the inverter circuit 501 changes from the L level to the H level. However, the output signal S502 of the NAND circuit 502 is
In a range where the voltage of the input signal Vin is higher than ViL, the L level is maintained as long as the output signal S503 of the NAND circuit 503 is at the H level. Therefore, the output signal S503 of the NAND circuit 503 maintains the H level regardless of the level of the input signal S501, and the output signal Vout also maintains the H level.

<Region C> When the voltage of the input signal Vin is ViL
Lower than the output signal S5 of the NAND circuit 502.
02 changes from the L level to the H level regardless of the level of the input signal S503. At this time, the NAND circuit 50
3 are both at the H level, the output signal S503 transitions to the L level, and the output signal Vout is also at the L level.
Transition to a level.

As described above, when the voltage of the input signal Vin rises from 0 V and reaches ViH, the NAND circuit 503 changes the output signal S501 of the inverter circuit 501 to H level.
An edge that transitions from the level to the L level is detected, and the output signal S503 transitions from the L level to the H level. In addition, when the voltage of the input signal decreases from VDD and reaches ViL, the NAND circuit 503
The edge of the output signal S502 of the transition from the L level to the H level is detected and the output signal S503 is changed from the H level to the L level.
Transition to a level.

Therefore, the input / output characteristics of the Schmitt circuit are
It has a hysteresis characteristic as shown in FIG.

Since the Schmitt circuit according to the present embodiment shown in FIG. 5 is composed of three inverter circuits and two NAND circuits, for example, when composed of CMOS circuits, the number of MOS transistors is 14 The number of elements can be reduced as compared with the conventional Schmitt circuit.

Therefore, the drive circuit 810 can be downsized by applying this Schmitt circuit.

[0064]

According to the present invention, the number of elements of the Schmitt circuit can be reduced and the size can be reduced.

[0065]

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a Schmitt circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a NAND circuit using CMOS.

FIG. 3 is a diagram illustrating input / output characteristics of a NAND circuit and input / output characteristics of a Schmitt circuit.

FIG. 4 is a diagram illustrating a relationship between an input signal Vin and an output signal Vout according to the first embodiment.

FIG. 5 is a circuit diagram showing a configuration of a Schmitt circuit according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing configurations of a NAND circuit and an inverter circuit using CMOS.

FIG. 7 is a diagram illustrating a relationship between an input signal Vin and an output signal Vout according to the second embodiment.

FIG. 8 is a diagram showing a configuration of a control circuit for ink ejection in a conventional inkjet printhead.

FIG. 9 is a specific circuit diagram of a conventional drive circuit.

Claims (12)

[Claims] 1. A semiconductor circuit having hysteresis characteristics, comprising: a first logic circuit for detecting that a voltage of an input terminal has become lower than a first threshold; and a voltage of said input terminal being higher than a second threshold. A second logic circuit for detecting the rise, a third logic circuit for inverting a logic level of an output terminal based on a detection signal of the first logic circuit and a detection signal of the second logic circuit; Wherein the first, second and third logic circuits are sequential circuits, respectively. 2. The signal of the third logic circuit is connected to the first logic circuit.
2. The semiconductor circuit according to claim 1, wherein the semiconductor circuit is fed back to a second logic circuit. 3. The first logic circuit includes a first NAND circuit.
And the second logic circuit comprises a second NAN.
3. The semiconductor circuit according to claim 2, comprising a D circuit. 4. The third logic circuit includes a third NAND circuit that receives outputs of the first and second logic circuits as inputs, and a first inverter that inverts an output of the third NAND circuit. One input of each of the first and second logic circuits is connected to the input terminal, and the output of the third NAND circuit is connected to the other input of the first logic circuit. 4. The output of the first inverter circuit, wherein the output of the first inverter circuit is connected to the other input of the second logic circuit.
3. The semiconductor circuit according to claim 1. 5. The circuit according to claim 4, wherein the third logic circuit further includes a second inverter circuit for inverting an output of the first inverter circuit and driving the output terminal. Semiconductor circuit. 6. The semiconductor circuit according to claim 1, wherein the first logic circuit forms a flip-flop together with the third logic circuit. 7. The first logic circuit includes a first NAND circuit.
And the third logic circuit includes the first N
A second N which forms a flip-flop together with an AND circuit
2. The semiconductor circuit according to claim 1, further comprising: an AND circuit; and a drive circuit that drives the output terminal based on an output of the second NAND circuit. 8. The semiconductor circuit according to claim 6, wherein said second logic circuit is an inverter circuit. 9. A semiconductor circuit comprising a plurality of the semiconductor circuits according to claim 1 integrated on a same substrate. 10. An electric circuit, comprising: the semiconductor circuit according to claim 1; and a heating element connected to the output terminal in the semiconductor circuit. 11. The semiconductor circuit according to claim 1, wherein a plurality of the semiconductor circuits are integrated on the same substrate, and a heating element is connected to an output terminal of each semiconductor circuit. electric circuit. 12. The electric circuit according to claim 10, wherein the heating element is used for heating ink in an ink jet type image recording apparatus.