JPH0715336A - Level detection circuit - Google Patents

Abstract

PURPOSE:To eliminate a through-current in the stop state by reducing a through- current in the operating state. CONSTITUTION:A reference voltage generating circuit 31 generates reference voltages Vs1-Vsn and a reference voltage switching circuit 33 selects a reference voltage used to be compared with a signal to be detected and provides the selected voltage sequentially to a node N10. The signal Si and the reference voltage Vs1 are compared through a capacitor 35 and an inverter 38. The compared results are sequentially latched by plural flip-flop circuits 41-1 to 41-n and the result of comparison between each reference voltage and each signal to be detected is decoded by a decoder. In the stop state of the level detection circuit, an NMOS 37 fixes a potential of a 2nd node N20 to a 2nd potential VSS to stop fluctuation in the potential of the node N20 and a PMOS 36 sets the potential at the node N20 to a 1st potential VDD in the operation start of the level detection circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a level for generating a plurality of reference voltages, detecting the level of an input signal from the reference voltages, and transmitting information based on the level of the input signal to a circuit or the like in the next stage. It relates to a detection circuit.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, some documents were described in the following documents. Reference 1: Japanese Patent Application Laid-Open No. 1-174116 FIG. 2 shows a circuit diagram of a conventional level detection circuit.
This level detection circuit is a circuit that obtains the level of the detected signal Si from the input terminal T1 by comparing it with a plurality of reference voltages Vs1 to Vsn, and determines the first power supply potential VDD and the second power supply potential VDD.
Are connected in series between the power supply potentials VSS of
a resistor 1 and a resistor group 2 of a reference voltage generation circuit that generates s to Vsn, and a plurality of comparators 10-1 to 10-n that respectively input the detected signal Si from the input terminal T1 and the reference voltages Vs to Vsn. , Each comparator 10-1 to
10-n output signal Sc is logically converted to output signal S
and a decoder 20 for outputting o from the output terminal T2. Each of the comparators 10-1 to 10-n has the same configuration, and has the reference voltages Vs1 to Vsn or the detected signal Si.
Input selector switch 1 for inputting either one of
1 and 12, a capacitor 13 for inputting the detected signal Si from the node N2 and blocking a DC component, and a capacitor 13
Of the voltage detection element connected in series to the output side node N3 of the inverter, the flip-flop 15 of the holding circuit that holds the output from the output side node N4 of the inverter 14 and outputs the output to the decoder 20, and the reference voltage at the node N2. , And a switch 16 that short-circuits the input and output of the inverter 14 when inputting. The inverter 14 is composed of, for example, a complementary MOS transistor (hereinafter, CMOS) in which a P-channel MOS transistor (hereinafter, PMOS) and an N-channel MOS transistor (hereinafter, NMOS) are connected in series. .

FIG. 3 is a time chart of the waveform of each part of FIG. The operation of FIG. 2 will be described with reference to FIG. The resistor 1 and the resistor group 2 divide the voltage between the power supply potentials VDD and VSS, so that the plurality of reference voltages Vs1 to Vs1.
Vsn is generated respectively. Comparator 10-1
, The input / output-side nodes N3 and N4 of the inverter 14 are short-circuited while the switches 11 and 16 are on, and the voltage levels of these nodes N3 and N4 are set to the inverter 1
The threshold voltage Vth is 4. That is, the reference voltage Vs1 is applied to the node N2, and the threshold voltage Vs is applied to the node N3.
th is applied. The flip-flop 15 inputs the control signal S2 from the clock signal terminal, holds the "L" information of the inverter 14, and outputs the output signal Sc.

Next, the switches 11 and 16 are turned off,
The switch 12 is turned on. During the ON period of the switch 12, the detected signal Si is applied to the node N2, and the voltage of the node N3 also changes in conjunction with the node N2 as shown in FIG. When the detected signal Si is higher than the reference voltage Vs1, the voltage of the input side node N3 of the inverter 14 becomes higher than the threshold voltage Vth, and the output of the inverter 14 becomes
It becomes "L". The flip-flop 15 has a control signal S1.
Is input from the clock signal terminal, and the flip-flop 15
Holds the “L” information of the inverter 14. As a result, the result of comparison between the detected signal Si and the reference voltage Vs1 is output as the output signal Sc. The detected signal Si is
When the voltage is lower than the reference voltage Vs1, the voltage of the input side node N3 of the inverter 14 becomes lower than the threshold voltage Vth,
The output of the inverter 14 becomes "H". The flip-flop 15 inputs the control signal S1 from the clock signal terminal, holds the “H” information of the inverter 14, and outputs the output signal S
Output c. The above operation is performed and the comparator 10-
1 compares the reference voltage Vs1 with the detected signal Si. Similarly, the other comparators 10-2 to 10-n simultaneously compare the reference voltages Vs2 to Vsn and the input signal Si, respectively. The decoder 20 decodes each signal Sc, and the level detection result of the detected signal Si is output from the output terminal T2 to the outside as the output signal So. As a result, the voltage level of the input signal Si is detected.

[0005]

However, the conventional level detection circuit has the following problems.
While the level detection circuit operates and the switch 16 is turned on, the inverter 16 is short-circuited by the switch 16 and the voltages of the nodes N3 and N4 become the threshold voltage Vth. However, the NMOS and P that form the inverter 14
The MOS has different thresholds due to manufacturing variations, and the threshold voltage Vth is an intermediate voltage between these thresholds. Therefore, while the switch 16 is on, both the NMOS and the PMOS are on and a minute through current flows through the inverter 14. In the level detection circuit of FIG. 2 having a plurality of comparators, this through current becomes large and causes power supply noise in the power supply voltage between the power supply potentials VDD and VSS. When the level detection circuit is used with a low power supply voltage, this power supply noise causes malfunction. Also,
When the level detection circuit stops operating, the capacitor 13
The potential of the output electrode of the node N3 is not fixed and
Voltage becomes a floating state near the threshold value Vth. Therefore, though the level detection is not performed, a through current flows through the inverter 14, which hinders reduction of current consumption.

In order to solve the above-mentioned problem, Document 1 adopts means for fixing the potential on the input side of the logic circuit at the time of stop. However, in the level detection circuit,
Even if the means for fixing the potential on the input side of the inverter 14 at the time of stop is used, not only the through current at the time of operation is not reduced, but at the start of the operation, the voltage of the node N3 becomes
There is a problem that it takes time to reach the threshold value Vth of 4. That is, the technique of Document 1 was insufficient to solve the problem of the level detection circuit. The present invention provides a level detection circuit that solves the problems that the above-described conventional technology has, that a through current that flows during operation causes a malfunction, and that a through current flows even during a stop. is there.

[0007]

In order to solve the above-mentioned problems, a first aspect of the present invention provides a level detection circuit, a reference voltage generating circuit for generating a plurality of reference voltages based on a power supply voltage, and a control signal. A first switch for shutting off or turning on the power supply voltage to the reference voltage generating circuit,
A reference voltage switching circuit that sequentially outputs the plurality of reference voltages to a first node, a second switch that inputs a detected signal to the first node in synchronization with the reference voltage switching circuit, and the first switch. A direct current component removing capacitor connected between the node and the second node, an offset correcting element for setting the second node to the first potential, and a complementary switch to the first switch based on the control signal. Is turned on,
A potential fixing gate for fixing the second node to a second potential, and when the voltage of the second node exceeds a predetermined threshold value, a voltage corresponding to the input voltage is output to the third node. And a voltage detection element. Further, the level detection circuit is connected in parallel with the voltage detection element, and is turned on when the reference voltage switching circuit outputs, and turned off when the second switch outputs.
Switch, a detection result switching circuit that sequentially captures the voltage of the third node corresponding to the reference voltage switching circuit, a holding circuit that holds the output of the detection result switching circuit, and the output of the holding circuit And a decoder for outputting the level detection result of the detected signal. In the second invention, the voltage detection element of the first invention is composed of an inverter, and the holding circuit is composed of a flip-flop.

[0008]

According to the first aspect of the present invention, since the level detecting circuit is configured as described above, the first switch starts or stops the operation of the reference voltage generating circuit. When the reference voltage generation circuit operates, a plurality of reference voltages are generated. One of the plurality of reference voltages is selected by the reference voltage switching circuit and output to the first node. Further, the second switch inputs the detected signal to the first node in synchronization with the reference voltage switching circuit. The DC component removing capacitor receives the reference voltage or the detected signal from the first node, removes the DC component, and outputs a voltage according to the voltage of the first node to the second node. In the potential fixing gate, the first
When the switch is off, that is, when the reference voltage generation circuit is stopped, the switch is turned on to fix the second node to the second potential. When the potential fixing gate is turned off, the offset correction element sets the second node to the first potential.

The third switch shorts the input and output of the voltage detection element and sets each voltage of the second and third nodes as the threshold value of the voltage detection element when the reference voltage switching circuit is outputting. To do. When the second switch is outputting, the third switch is turned off, and the voltage of the second node becomes a voltage according to the voltage of the detected signal input to the first node. The voltage detection element detects the second node voltage, and when the voltage of the second node exceeds a predetermined threshold value, the voltage according to the voltage of the second node is output to the third node. . When the detection result switching circuit sequentially takes in the voltage of the third node corresponding to the reference voltage switching circuit, the outputs thereof are held by the holding circuits. The output of the holding circuit is decoded by the decoder and the level detection result of the detected signal is output. According to the second invention,
The inverter inverts the output when the voltage at the second node exceeds the threshold. Further, the flip-flop latches the output of the detection result switching circuit with an internal transistor. Therefore, the above problem can be solved.

[0010]

1 is a circuit diagram of a level detecting circuit showing an embodiment of the present invention. This level detection circuit is shown in FIG.
Similarly to the level detection circuit of No. 1, the detected signal S1 input from the input terminal T1 is compared with a plurality of reference voltages Vs1 to Vsn to detect the level of the detected signal S1 and a logic corresponding to the detection result. It is a circuit that outputs the output signal So of the signal from the output terminal 2. In this circuit, the plurality of reference voltages Vs1 are connected between the power supply potential VDD and the power supply potential VSS.
.About.Vsn, and the reference voltage generation circuit 3 based on the control signal S3 from the input terminal T3.
1, a first switch (for example, PMOS) 32 for cutting off or turning on the power supply voltage, and a reference voltage generation circuit 3
The reference voltage switching circuit 33 that sequentially outputs the reference voltages Vs1 to Vsn from 1 to the first node N10 and the reference voltage switching circuit 33 that is turned on in synchronization with the turning off of the reference voltage switching circuit 33, and outputs the detected signal Si from the input terminal T1 to the first node N1. And a second switch 34 for inputting to the node N10. Reference voltage generation circuit 31
Has a plurality of resistors 31-1 to 31-n for dividing the power supply voltage to generate the reference voltages Vs1 to Vsn, which are connected in series. Reference voltage switching circuit 33
Has switches 33-1 to 33-n, and one end of each of the switches 33-1 to 33-n has a reference voltage Vs1 to
It is connected to Vsn and the other end is commonly connected to the node N10.

In the level detection circuit of this embodiment, further,
A DC component removing capacitor 35 having one electrode connected to the node N10, and an offset correction element (eg, PMOS) connected to the other electrode of the capacitor 35 and setting the second node N20 to the first potential. 36, a voltage fixing element (for example, NMOS) 37, an inverter 38 connected to the node N20, and a third switch 39 connected between the node N30 on the output side of the inverter 38 and the node N20. is doing. Here, the NMOS 37 is
PM by the control signal S3 input from the input terminal T3
Operates complementarily to OS31, and when in the ON state, node N
It has a function of connecting 20 to the power supply potential VSS which is the second potential.

Further, a detection result switching circuit 40 which sequentially takes in the voltage of the third node N30 corresponding to the reference voltage switching circuit 31, a holding circuit 41 which holds the output of the detection result switching circuit 40, and a holding circuit. A decoder 42 that decodes the output of 41 and outputs an output signal So of the level detection result of the detected signal from the output terminal T2 is provided. The detection result switching circuit 40 includes a plurality of switches 4
0-1 to 40-n, and each of those switches 40
One ends of -1 to 40-n are commonly connected to the node N30. The holding circuit 41 includes a plurality of flip-flops 41-
1 to 41-n, the data terminals of the respective flip-flops 41-1 to 41-n are connected to the respective switches 40-
It is connected to the other ends of 1 to 40-n, respectively. The decoder 42 is a circuit that logically converts the output signals Sc from the flip-flops 41-1 to 41-n, and is connected to the output terminals of the flip-flops 41-1 to 41-n. Next, the operation of the level detection circuit shown in FIG. 1 will be described with reference to FIG. FIG. 4 is a time chart of FIG. 1, in which each signal and the waveform of each part are shown.

When the control signal S3 becomes "L", the PMOS
32 is turned on. When the PMOS 32 is turned on, the level detection circuit starts operating and the reference voltage generation circuit 31
Then, the reference voltages Vs1 to Vsn are generated. At the same time, the NMOS 37 fixing the node N20 is turned off, and the potential of the node N20 is set to the first potential VDD. A control signal S4 and a control signal S5 for selecting a reference voltage from the outside are applied to the switch 31-1 and the switch 39, respectively, and the switch 31-1 and the switch 39 are turned on. During a period in which the switch 31-1 and the switch 39 are on, the input and output of the inverter 38 are short-circuited, and the voltage of each node N20, 30 is the threshold voltage V of the inverter 38.
th. On the other hand, the reference voltage Vs1 is applied to the input side of the capacitor 35, that is, the node N10.

Next, the switch 31-1 and the switch 39
Is turned off, and in synchronization with this, an external control signal S5
Turns on the switch 34. Further, the control signal S6 is applied to the switch 40-1, and the switch 40-1 is turned on. Therefore, the voltage of the node N10 becomes the level of the detected signal Si, and the voltage of the node N20 rises or falls in conjunction with the voltage change of the node N10. When the level of the detected signal Si is lower than the reference voltage Vs1, the voltage of the node N20 exceeds the threshold Vth and drops to a voltage lower than the threshold Vth. In this case, the inverter 38 outputs "H". When the level of the detected signal Si is higher than the reference voltage Vs1, the voltage of the node N20 has the threshold value Vt.
The voltage exceeds h and rises to a voltage higher than the threshold Vth. In this case, the inverter 38 outputs "L". The flip-flop 41-1 latches the output of the inverter 38 by the control signal S7 input to the clock terminal from the outside,
The latched information is retained. That is, the reference voltage Vs1
The result of comparison between the detected signal Si and the detected signal Si is held in the flip-flop 41-1. The above operation is based on the reference voltage Vs2.
To Vsn are repeatedly performed, and the result is held in each of the flip-flops 41-2 to 41-n. When a series of comparison operations is completed, each flip-flop 41-1 to 41-n
The held data of is output to the decoder 42 as the output signal Sc. The decoder 42 decodes the signal Sc and outputs an output signal So based on the level detection result of the detected signal Si. When the control signal S3 becomes "H", the PMOS 32
Turns off. When the PMOS 32 turns off,
This level detection circuit stops and the generation of the reference voltage stops. At the same time, the NMOS 37 is turned on,
The potential of the node N20 is fixed to the second potential VSS.

As described above, this embodiment has the following advantages. (1) Each switch 33-1 of the reference voltage switching circuit 33
33-n is the reference voltage V from the reference voltage generation circuit 31.
s1 to Vsn are selected and supplied to the node N10. Therefore, the comparison with the detected signal Si does not need to be performed by, for example, a plurality of conventional comparators, and one series is sufficient. Therefore, the through current during operation is small, and the power supply noise can be reduced. (2) As a result of (1) above, when the level detection circuit is formed in a semiconductor integrated circuit (IC) or the like, the circuit configuration is simplified and the chip area can be reduced. (3) Node N2 when the level detection circuit is stopped
Since the potential of 0 is fixed, a through current does not flow at the time of stop, and low current consumption can be realized. (4) Since the PMOS 36 sets the potential of the node N20 to the first potential VDD at the same time that the NMOS 37 is turned off, the level detection circuit can start operating quickly. (5) Since the voltage detection element is composed of the inverter 38 and the holding circuit is composed of the flip-flops 41-1 to 41-n, the circuit structure is simplified.

The present invention is not limited to the above embodiment,
Various modifications are possible. The following are examples of such modifications. (A) The plurality of switches 31-1 to 31-n configuring the reference voltage switching circuit 33 may be configured by gates such as a multiplexer. (B) Each of the PMOSs 32 and 36 and the NMOS 37 is an NMOS according to the set polarity of the detected signal Si.
It may be replaced with 32 and 36 and the PMOS 37, or may be constituted by a bipolar transistor. (C) The detection result switching circuit 40 includes switches 40-1 to 40-1.
Although 40-n is used, other elements such as a gate may be used.

[0017]

As described in detail above, according to the first aspect of the invention, the reference voltage switching circuit selects a plurality of reference voltages, and the selected reference voltages are sequentially output to the first node. To be done. The reference voltage and the signal to be detected via the second switch are alternately applied to the first node, and the reference voltage and the signal to be detected are compared via the voltage detection element. The comparison result is held in the holding circuit, and after the comparison between the plurality of reference voltages and the detected signal is completed, it is decoded by the decoder and the output signal according to the level of the detected signal is output. Therefore, the circuit for comparing the reference voltage and the detected signal may be one series, and, for example, a plurality of circuits as in the conventional case are not required. As a result, it is possible to reduce extra through current during operation, reduce power supply noise, and reduce current consumption. Further, since the structure inside the level detection circuit is simplified, the circuit formation area can be reduced and the cost can be reduced. When the level detection circuit is stopped, the potential fixing gate fixes the second node to the second potential, so that the voltage detection element is completely turned off, and the generation of shoot-through current is eliminated. Therefore, current consumption can be reduced. Second
According to the invention, the voltage detecting element is composed of an inverter and the holding circuit is composed of a flip-flop. Therefore, a level detection circuit that achieves the above effects can be realized with a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a level detection circuit showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional level detection circuit.

FIG. 3 is a time chart of FIG.

FIG. 4 is a time chart of FIG.

[Explanation of symbols]

12, 35 Capacitor 14, 38 Inverter (voltage detection element) 20, 42 Decoder 31 Reference voltage generation circuit 32 PMOS (first switch) 33 Reference voltage switching circuit 34, 39 Second and third switch 35 Capacitor 36 PMOS ( Offset correction element) 37 NMOS (potential fixing gate) 40 Detection result switching circuit 41 Holding circuit 41-1 to 41-n Flip-flop N10, N20, N30 First, second and third nodes

Claims (2)

[Claims] 1. A reference voltage generation circuit that generates a plurality of reference voltages based on a power supply voltage, and a first switch that shuts off or turns on the power supply voltage to the reference voltage generation circuit based on a control signal. A reference voltage switching circuit that sequentially outputs the plurality of reference voltages to a first node, a second switch that inputs a detected signal to the first node in synchronization with the reference voltage switching circuit, and the first node A DC component removing capacitor connected between the first node and a second node; an offset correction element that sets the second node to a first potential; and a complementary switch to the first switch based on the control signal. When the voltage of the second node exceeds a predetermined threshold, a voltage according to the input voltage is applied to the third gate for fixing the potential which fixes the second node to the second potential. Node A voltage detection element that outputs the voltage to the voltage detection element, a third switch that is connected in parallel with the voltage detection element, is turned on when the reference voltage switching circuit outputs, and is turned off when the second switch outputs, and the reference voltage. A detection result switching circuit that sequentially takes in the voltage of the third node corresponding to the switching circuit, a holding circuit that holds the output of the detection result switching circuit, and a decoding circuit that decodes the output of the holding circuit to output the detected signal. A level detection circuit comprising: a decoder that outputs a level detection result. 2. The level detection circuit according to claim 1, wherein the voltage detection element is composed of an inverter, and the holding circuit is composed of a flip-flop.