JPH1083443A - Arithmetic unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To serially operate data of not less than three picture elements with the small number of times by providing a sum signal generation means for generating the sum signal of one bit and a carry signal generation means for generating the carry signal of two bits. SOLUTION: The inputs 133-135 of three picture element data of eight bits are sequentially inputted from LSB in synchronizing with a clock signal 130. Selectors 111 and 112 respectively select inputs 131 and 132 in the first cycle and select carries 1 and 2 in second-eighth cycles. The outputs of flip flops 101-105 are operated in full adders 106 and 107 and an operated result is outputted from a sum 2 as the exclusive OR of five inputs. The carry signal of two bits to a high-order digit is outputted from the carries 1 and 2. Thus, three pieces of data of eight bits, which are serially inputted, are added.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit mainly implemented by a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, the performance required of semiconductor integrated circuits has been increasing year by year. Particularly, in the case of semiconductor integrated circuits which realize video signal processing, a large amount of data is processed at high speed. Ability is required.

As a conventional processor for realizing high-speed arithmetic processing of a large amount of data on a semiconductor integrated circuit, for example, a document “Jim Children, et al”
SVP: SERIAL VIDEO PROCESSE
R "IEEE CUSTOM INTEGRATED
CIRCULTS CONFERENCE p. 1
7.3 1990 ".

Hereinafter, an arithmetic unit used in the above-described conventional processor will be described with reference to the drawings.

FIG. 10 shows a configuration diagram of an arithmetic processing unit of a conventional processor. In FIG. 10, 1 and 2
Is a RAM that can simultaneously read and write 1024-bit data, and can store a video signal of one line up to 1024 pixels.

Reference numeral 3 denotes a 1-bit arithmetic unit (alu) 102
Four units are arranged in parallel, and each alu is a RAM
1024-bit data read from 1 and RAM
For the 1024-bit data read from 2,
1024 alus perform the same 1-bit operation,
The 1024-bit operation result is output, and the operation is performed by writing the 1024-bit operation result to the RAM1 or RAM2.

Each alu has a function of communicating with a nearby alu, and can realize a horizontal filter using some pixel data in the horizontal direction.

This arithmetic unit basically has 1024 1's.
A multi-bit operation is realized by repeatedly executing a bit operation. FIG. 11 shows a configuration diagram of the alu in FIG.

In FIG. 11, 1, 2 and 3 each represent 1
The bit flip-flop circuit (FF) writes and outputs 1-bit data in synchronization with the clock signal 10.

Reference numeral 5 denotes a three-input adder for adding the outputs of FF1, FF2 and FF3.
m) and carry.

The carry can be fed back to the FF 3. For example, when it is desired to add two 8-bit pixels to obtain an 8-bit output, each pixel is synchronized with a clock signal. FF1 and FF2 are fetched serially in order from the LSB, and carry generated in each bit is fed back to FF3 to carry, thereby realizing in eight cycles.

[0012]

However, in the above configuration, since alu is composed of a three-input adder, for example, one line of pixel data stored in When a horizontal filter for three pixels is realized and the result is to be written into the RAM 2, the operation is performed as follows.

First, pixel data for one line is read out serially from the RAM 1 bit by bit, and alu
Then, an operation is performed on two pixels among the three pixels that realize the filter, and the operation result is serially stored bit by bit in the RAM 2 as pixel data of an intermediate operation result for one line.
Write to.

Next, one line of pixel data is read again from the RAM 1 serially one bit at a time,
From AM2, pixel data of an intermediate operation result for one line is read out serially one bit at a time, and an operation is performed on the remaining one pixel of the three pixels realizing the filter with alu and the intermediate operation result, One line of pixel data is serially written into the RAM 2 bit by bit as an output of a horizontal filter for three pixels, thereby realizing a three-pixel horizontal filter.

In other words, two serial read operations and two serial write operations are required for RAM1 and RAM2, and two serial operation operations are required for alu. There was a problem.

Accordingly, the present invention has been made in view of the above problems, and provides an arithmetic unit (corresponding to alu in the conventional example) capable of serially calculating data of three or more pixels in a small number of times.

[0017]

In order to solve the above problems, an arithmetic unit according to the present invention comprises a sum signal generating means for generating a 1-bit sum signal and a carry signal for generating a 2-bit carry signal. Generating means, wherein the sum signal generating means
For a first input signal of bits, an exclusive OR is output as a sum signal, and the carry signal generating means outputs a first carry signal and a second carry signal, and When the number of bits whose value is 1 is 1 or less in one input signal, both outputs of the first carry signal and the second carry signal become 0, and the first carry signal becomes 0. When the number of bits whose value is 1 is 2 or more and 3 or less in the input signal, one of the output of the first carry signal and the second carry signal is 1 and the other output is 0. In the first input signal, when the number of bits whose value is 1 is 4 or more, the output of both the first carry signal and the second carry signal becomes 1 It was done.

As a result, among the five-bit input of the arithmetic unit of the present invention, three data which are serially input one bit at a time are input as the three-bit input, and the remaining two bits are input according to the present invention. By inputting a 2-bit carry signal output from the arithmetic unit, a 1-bit serial arithmetic operation can be performed on three data.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a circuit configuration diagram of an arithmetic unit according to a first embodiment of the present invention.

In FIG. 1, 106 and 107 are full adders, and 106 is a first full adder according to claim 7;
07 corresponds to the second full adder according to claim 7, and
By connecting sum 1, the output of full adder 106, to one of the inputs of full adder 107,
06 and the full adder 107 realize the sum signal generating means and the carry signal generating means according to the first aspect.

That is, the carry 1 output from the full adder 106 corresponds to the first carry signal according to claim 7,
Carry 2, which is the output of full adder 107, corresponds to the second carry signal described in claim 7, and sum 2, which is the output of full adder 107, corresponds to the second sum signal described in claim 7. .

The carry 1 output from the full adder 106 and the carry 2 output from the full adder 107 correspond to the first carry signal and the second carry signal described in claim 1, respectively. The sum 2 output from the adder 107 corresponds to the sum signal of the first aspect.

The operation of the full adder 106 and the full adder 107 is to perform addition on three inputs, to output a two-digit addition result, and to output a lower-order addition result from sum 1 or sum 2. It outputs the result of addition of the upper digit from carry 1 or carry 2.

In the figure, 101, 102, 103, 104,
Numeral 105 is a 1-bit flip-flop circuit for storing and outputting data in synchronization with the clock signal 130, and realizes the data holding means according to the second, third, eighth and ninth aspects.

In the figure, reference numerals 111 and 112 denote selectors having two inputs and one output, which implement the first selector according to the third and ninth aspects.

Using the arithmetic unit according to the present embodiment configured as described above, three 8-bit pixel data GA (7: 0) serially input from the LSB in synchronization with the clock signal 130. , GB (7: 0), G
The operation when adding C (7: 0) to obtain an 8-bit output Z (7: 0) using eight cycles will be described.

The three 133-bit pixel data GA (7: 0), GB (7: 0), and GC (7: 0) are input to the inputs 133, 134, and 135 in FIG. (GA (0), GB (0), GC (0)) are input serially in this order.
At 32, 0 is input at least in the first cycle.

The selectors 111 and 112 select the input 131 and the input 132 in the first cycle, respectively, and select the carry 1 and the carry 2 in the second to eighth cycles, respectively. .

The operation at the time of such setting will be described with reference to the timing chart shown in FIG. This timing chart shows the clock signal 130 and the flip-flop 1
3 shows outputs 01 to 105 and an output of sum 2.

In cycle 1, flip-flop 10
0 is output from 1, 102 and the flip-flop 103
105 output GA (0), GB (0), and GC (0) which are the LSBs of 8-bit pixel data.

These five outputs are operated by the full adder 106 and the full adder 107, and an output Z (0) of the operation result is output from the sum 2 as an exclusive OR of these five inputs. And carry 2 carry signals carry1 (0) and carry2 (0) from carry 2 to the upper digit.

Carry1 (0) and carry2 (0)
When carry to the upper digit generated as a result of adding five inputs is 0, carry1 (0) and car1
ry2 (0) outputs 0, and the carry to the upper digit is 1
, One of carry1 (0) and carry2 (0) outputs 1 and the other outputs 0, and when the carry to the upper digit is 2, carry1 (0) and carry
Both y2 (0) outputs 1.

In cycle 2, the carry 1 (0) and carry 2 (0) output of cycle 1 are output from flip-flops 101 and 102, respectively, and flip-flops 103 to 105 output GA (1), GB (1), GC
(1) is output.

These five outputs, that is, the carry signal from the two lower digits and the input of the three LSB + 1 digits, are operated by the full adder 106 and the full adder 107 to obtain the sum 2
Outputs an operation result output Z (1) as an exclusive OR of these five inputs, and carries a 2-bit carry signal carry1 (1) from carry 1 and carry 2 to the upper digit.
Output carry2 (1).

From cycle 3 to cycle 8, the same operation as in cycle 2 is repeated, and sums 2 to Z
(2), Z (3), Z (4), Z (5), Z (6), Z
(7) is output.

In this manner, in eight cycles, addition of three 8-bit data input serially can be realized.

In an arithmetic unit using a three-input adder as in the conventional example, at least 16 cycles are required to realize the addition of three 8-bit data input serially. By using the arithmetic device having the configuration of the embodiment, it is possible to provide an arithmetic device that can be realized with eight cycles, which is half the number of cycles.

Although the operation of the present embodiment has been described with respect to three 8-bit pixel data, pixel data having an arbitrary number of bits can be added in the same manner. it can.

In the description of the operation of this embodiment, the operation of adding three pixel data has been described.
To add two pixels out of one pixel data and to subtract one pixel, input the bit-inverted data of the pixel data to be subtracted, and input either the input 131 or the input 132 in the first cycle. Is input by inputting 1 to the pixel data, and when it is desired to add one pixel out of three pixel data and subtract two pixels, input data of bit inversion of the pixel data to be subtracted, This can be realized by inputting 1 as the input 131 and the input 132 in the first cycle.

(Embodiment 2) FIG. 3 is a circuit configuration diagram of an arithmetic unit according to a second embodiment of the present invention.

In FIG. 3, reference numerals 206 and 207 denote full adders, and reference numeral 206 denotes a first full adder according to claim 7;
07 corresponds to the second full adder according to claim 7, and
By connecting sum 1, the output of full adder 206, to one of the inputs of full adder 207, full adder 2
06 and the full adder 207 realize the sum signal generating means and the carry signal generating means according to the first aspect.

That is, the carry 1 output from the full adder 206 corresponds to the first carry signal according to claim 7,
Carry 2, which is the output of full adder 207, corresponds to the second carry signal described in claim 7, and sum 2, which is the output of full adder 207, corresponds to the second sum signal described in claim 7. .

A carry 1 output from the full adder 206 and a carry 2 output from the full adder 207 correspond to the first carry signal and the second carry signal described in claim 1, respectively. The sum 2 output from the adder 207 corresponds to the sum signal of the first aspect.

The operation of the full adder 206 and the full adder 207 is to perform addition on three inputs, output a two-digit addition result, and output a lower-order addition result from sum 1 or sum 2. It outputs the result of addition of the upper digit from carry 1 or carry 2.

In the figure, reference numerals 221 and 222 denote 1-bit flip-flop circuits which store and output data in synchronization with the clock signal 230, respectively, and realize the first data holding means according to claim 4 or 10. It is.

In the figure, 201, 202, 203, 204,
Reference numeral 205 denotes a 1-bit flip-flop circuit which stores and outputs data in synchronization with the clock signal 230, and realizes the second data holding means according to claims 4 and 10.

Reference numerals 211 and 212 in the figure denote selectors with two inputs and one output, which implement the first selection means according to the fourth and tenth aspects.

Using the arithmetic unit of the present embodiment configured as described above, three 8-bit pixel data GA (7: 0) serially input from the LSB in synchronization with the clock signal 230. , GB (7: 0), G
The operation when adding C (7: 0) to obtain an 8-bit output Z (7: 0) using eight cycles will be described.

The three 8-bit pixel data GA (7: 0), GB (7: 0), and GC (7: 0) are input to the inputs 233, 234, and 235 in FIG. (GA (0), GB (0), GC (0)) in that order.
At 32, 0 is input at least in the first cycle.

The selectors 211 and 212 select the outputs of the flip-flops 201 and 202 in the first cycle, and select the outputs of the flip-flops 221 and 222 in the second to eighth cycles. So that

The operation at the time of such setting will be described with reference to the timing chart shown in FIG. This timing chart shows the clock signal 230 and the flip-flop 2
3 shows the outputs of 01 to 205, 221, 222 and the output of sum 2.

In cycle 1, flip-flop 20
1 and 202 and the values output from the flip-flops 221 and 222, the selector 2
11 and 212, flip-flops 201 and 20
2 is selected and output, and the flip-flops 203 to 205 output GA (0), GB (0), and GC (0), which are the LSBs of 8-bit pixel data. .

These five outputs are operated by the full adder 206 and the full adder 207, and an output Z (0) of the operation result is output from the sum 2 as an exclusive OR of these five inputs. And carry 2 carry signals carry1 (0) and carry2 (0) from carry 2 to the upper digit.

Carry1 (0) and carry2 (0)
When carry to the upper digit generated as a result of adding five inputs is 0, carry1 (0) and car1
ry2 (0) outputs 0, and the carry to the upper digit is 1
, One of carry1 (0) and carry2 (0) outputs 1 and the other outputs 0, and when the carry to the upper digit is 2, carry1 (0) and carry
Both y2 (0) outputs 1.

In the cycle 2, the carry 1 (0) and carry 2 (0) output from the cycle 1 are output from the flip-flops 221 and 222.

These flip-flops 221 and 222
And the outputs of the flip-flops 201 and 202 are
By the selectors 211 and 212, the flip-flop 2
21 and 222 are selected and output, and the flip-flops 203 to 205 are GA (1), GB (1), GC
(1) is output.

These five outputs, that is, the carry signal from the two lower digits and the input of the three LSB + 1 digits, are operated by the full adder 206 and the full adder 207 to obtain the sum 2
Outputs an operation result output Z (1) as an exclusive OR of these five inputs, and carries a 2-bit carry signal carry1 (1) from carry 1 and carry 2 to the upper digit.
Output carry2 (1).

Thereafter, from cycle 3 to cycle 8, the same operation as cycle 2 is repeated, and sums 2 to Z
(2), Z (3), Z (4), Z (5), Z (6), Z
(7) is output.

In this way, in eight cycles, addition of three 8-bit data input serially can be realized.

In an arithmetic unit using a three-input adder as in the conventional example, at least 16 cycles were required to add three 8-bit data input serially. By using the arithmetic device having the configuration of the embodiment, it is possible to provide an arithmetic device that can be realized with eight cycles, which is half the number of cycles.

Although the operation of the present embodiment has been described with respect to three 8-bit pixel data, pixel data having an arbitrary number of bits can be added in the same manner. it can.

In the description of the operation of this embodiment, the operation of adding three pixel data has been described.
When it is desired to add two pixel data out of one pixel data and to subtract one pixel data, input data of bit inversion of the pixel data to be subtracted, and input one of the input 231 and the input 232 to the first. It is realized by inputting 1 in the cycle,
When it is desired to add one pixel data out of two pixel data and to subtract two pixel data, input the bit-inverted data of the pixel data to be subtracted, and set the input 231 and the input 232 to 1 in the first cycle. This can be realized by inputting.

(Embodiment 3) FIG. 5 is a circuit configuration diagram of an arithmetic unit according to a third embodiment of the present invention.

In FIG. 5, 306 and 307 are full adders, and 306 is a first full adder according to claim 7;
07 corresponds to the second full adder according to claim 7, and
By connecting sum 1, the output of full adder 306, to one of the inputs of full adder 307, full adder 3
06 and the full adder 307 realize the sum signal generating means and the carry signal generating means according to the first aspect.

That is, the carry 1 output from the full adder 306 corresponds to the first carry signal according to claim 7,
Carry 2, which is the output of full adder 307, corresponds to the second carry signal described in claim 7, and sum 2, which is the output of full adder 307, corresponds to the second sum signal described in claim 7. .

The carry 1 output from the full adder 306 and the carry 2 output from the full adder 307 correspond to the first carry signal and the second carry signal described in claim 1, respectively.
The sum 2 output from the full adder 307 corresponds to the sum signal of the first aspect.

The operation of full adder 306 and full adder 307 is to perform addition on three inputs, to output a two-digit addition result, and to output a lower-order addition result from sum 1 or sum 2. It outputs the result of addition of the upper digit from carry 1 or carry 2.

In the figure, reference numerals 321 and 322 denote 1-bit flip-flop circuits for storing and outputting data in synchronization with the clock signal 330, respectively, which realize the first data holding means according to claim 5 or 11. It is.

Reference numeral 323 in the figure denotes a 1-bit flip-flop circuit which stores and outputs data in synchronization with the clock signal 330, and realizes the second data holding means according to the fifth and eleventh aspects.

13. The third data holding means according to claim 5, wherein reference numerals 301, 302, 303, and 304 each denote a 1-bit flip-flop circuit for storing and outputting data in synchronization with a clock signal 330. Is realized.

In the figure, reference numeral 305 denotes a 1-bit flip-flop circuit which stores and outputs data in synchronization with the clock signal 330, and realizes the fourth data holding means according to the fifth and eleventh aspects.

Reference numeral 313 in the figure denotes a two-input one-output selector, which implements the selection means according to the fifth and eleventh aspects.

In the figure, 311 and 312 are 2 inputs and 1 respectively.
It is an output selector. Using the arithmetic unit according to the present embodiment configured as described above, the clock signal 330
5 8 serially input from LSB in synchronization with
Pixel data GA (7: 0), GB (7:
0), GC (7: 0), GD (7: 0), GE (7:
0) is added to obtain an 8-bit output Z (7: 0) using 16 cycles.

Inputs 333 and 334 shown in FIG. 5 are used to input two 8-bit pixel data GA (7: 0) and GB (7: 0) in the odd cycle in synchronization with the clock signal 330.
(GA (0), GB (0)) in order, and the two 8-bit pixel data GD (7: 0) and GE (7: 0) are converted to LSB in even-numbered cycles.
(GD (0), GE (0)) are input serially in order.

The input 335 is configured to serially input 8-bit pixel data GC (7: 0) in order from the LSB (GC (0)) in at least an odd cycle in synchronization with the clock signal 330. Inputs 331 and 332
Is to input 0 at least in the first and second cycles.

The selectors 311 and 312 select the inputs 331 and 332 in the first cycle and the second cycle, respectively, and output the outputs of the flip-flops 321 and 322 in the third to sixteenth cycles, respectively. To choose.

The selector 313 selects the output of the flip-flop 305 in the odd cycle, and selects the output of the flip-flop 327 in the even cycle.

Further, 0 is stored in the flip-flop 323 in the first cycle. The operation at the time of such setting will be described with reference to the timing chart shown in FIG. This timing chart shows a clock signal 330,
The output of the flip-flops 301 to 305 and 321 to 323 and the output of the sum 2 are shown, and one-digit addition is realized in two cycles of an odd clock and an even clock.

In cycle 1, flip-flop 30
0 is output from 1,302, and the flip-flop 303
305 output GA (0), GB (0), and GC (0), which are the LSBs of 8-bit pixel data.

These five outputs are operated by the full adder 306 and the full adder 307, and the output sum1 (0) of the operation result is obtained from the sum 2 as the exclusive OR of these five inputs.
, And carry signals carry1 (0), carry2 of 2 bits from carry 1 and carry 2 to the upper digit.
(0) is output.

Carry1 (0) and carry2 (0)
When carry to the upper digit generated as a result of adding five inputs is 0, carry1 (0) and car1
ry2 (0) outputs 0, and the carry to the upper digit is 1
, One of carry1 (0) and carry2 (0) outputs 1 and the other outputs 0, and when the carry to the upper digit is 2, carry1 (0) and carry
Both y2 (0) outputs 1.

In cycle 2, flip-flop 30
0 is output from 1,302, and the flip-flop 30
G which is the LSB of pixel data of 3,304 to 8 bits
D (0) and GE (0) are output.

In addition, sum1 (0), carry1 (0), carry outputted as the operation result of the previous cycle
2 (0) are flip-flops 323 and 32, respectively.
1,322.

Of these eight outputs, five outputs from the flip-flops 301, 302, 303, 304, and 323 are operated by the full adder 306 and the full adder 307. The output sum2 (0) of the operation result is output as a logical OR, and the carry signal c of 2 bits from carry 1 and carry 2 to the upper digit is output.
arry3 (0) and carrr4 (0) are output.

Sum2 (0) is GA (0), GB
This is the exclusive OR of (0), GC (0), GD (0), and GE (0), and is the LSB operation result Z (0).

Carry3 (0) and carry4 (0)
When carry to the upper digit generated as a result of adding five inputs is 0, carry3 (0) and carry3
ry4 (0) outputs 0, and carry to the upper digit is 1
, One of carry3 (0) and carry4 (0) outputs 1 and the other outputs 0. When the carry to the upper digit is 2, carry3 (0) and carry4 (0)
Both y4 (0) outputs 1.

Thus, cycle 1 and cycle 2
Performs operations on five 8-bit LSBs in a cycle,
As a calculation result, carry signals carry1 (0) and carry2 (0) to two upper digits are output in cycle 1, and in cycle 2, a calculation result Z (0) and a carry signal carry3 to two higher digits (carry3 (0)) 0) and carry4 (0) are output.

In cycle 3, flip-flop 30
Two carry signals carry1 (0) and carry2 (0) outputted from flip-flops 321 and 322 as an operation result two cycles before from 302 are outputted, and 8-bit pixel is outputted from flip-flops 303 to 305. GA (1), GB which is LSB + 1 of data
(1), GC (1) are output.

Also, sum2 (0), carry3 (0), carry output as the operation result of the previous cycle
4 (0) are flip-flops 323 and 32, respectively.
1,322.

Of these eight outputs, five outputs from flip-flops 301, 302, 303, 304, and 323 are operated by full adder 306 and full adder 307, and exclusive sum of these five inputs is obtained from sum 2. The output sum1 (1) of the operation result is output as a logical OR, and the carry signal c of 2 bits from carry 1 and carry 2 to the upper digit is output.
arry1 (1) and carry2 (1) are output.

Carry1 (1) and carry2 (1)
When carry to the upper digit generated as a result of adding five inputs is 0, carry1 (1) and car1
ry2 (1) outputs 0, and carry to the upper digit is 1
, One of carry1 (1) and carry2 (1) outputs 1 and the other outputs 0, and when the carry to the upper digit is 2, carry1 (1) and carry1
Both y2 (1) outputs 1.

In cycle 4, flip-flop 30
Two carry signals carry3 (0) and carry4 (0) output from flip-flops 321 and 322 as an operation result two cycles before the first and second 302 are output, and 8-bit pixels are output from flip-flops 303 and 304. GD (1), GE which is LSB + 1 of data
(1) is output.

Also, sum1 (1), carry1 (1), carry1 output as the operation result of the previous cycle
2 (1) are flip-flops 323 and 32, respectively.
1,322.

Of these eight outputs, five outputs from the flip-flops 301, 302, 303, 304, and 323 are operated by the full adder 306 and the full adder 307. The result sum2 (1) of the operation result is output as a logical OR, and the carry signal c of 2 bits from carry 1 and carry 2 to the upper digit is output.
arry3 (1) and carrr4 (1) are output.

Sum2 (1) is GA (1), GB
(1), GC (1), GD (1), GE (1), car
ry1 (0), carry2 (0), carry3
(0), the exclusive OR of carry4 (0),
The operation result of LSB + 1 is Z (1).

Carry3 (1) and carry4 (1)
When carry to the upper digit generated as a result of adding five inputs is 0, carry3 (1) and car3
ry4 (1) outputs 0, and carry to the upper digit is 1
, One of carry3 (1) and carry4 (1) outputs 1 and the other outputs 0, and when the carry to the upper digit is 2, carry3 (1) and carry4
Both y4 (1) outputs 1.

As described above, cycle 2 and cycle 4
In the cycle, five 8-bit LSB + 1 operations are executed, and as the operation result, two carry signals carry1 (1) and carry2 (1) to the upper digits are output in cycle 3, and the operation result Z in cycle 4 (1) Carry signals carry3 (1) and carry4 (1) to two upper digits
Is output.

Hereinafter, from cycle 5 to cycle 16,
The odd cycle performs the same operation as the cycle 3, the even cycle repeats the same operation as the cycle 4, and sequentially from the sum 2 of the even cycle to Z (2), Z (3), Z (4), Z
(5), Z (6) and Z (7) are output. In this manner, in 16 cycles, addition of five 8-bit serially input data can be realized.

In an arithmetic unit using a three-input adder as in the conventional example, at least 32 cycles were required to realize the addition of five serially input 8-bit data. By using the arithmetic device having the configuration described in (1), it is possible to provide an arithmetic device that can be realized with half the number of cycles, that is, 16 cycles.

In this embodiment, the selector 313 is connected to the input 33 without the flip-flop 323 in this embodiment.
5 and the sum 2 are selected and output to the flip-flop 305, so that the flip-flops 321 and
322 corresponds to the first data holding means according to claims 6 and 12, 301, 302, 303 and 304 correspond to the second data holding means according to claims 6 and 12, and the flip-flop 305 The selector 313 corresponds to the third data holding unit according to the sixth and twelfth aspects.
A computing device corresponding to the selecting means described can be made,
The operation outputs GC data at the odd cycle of the flip-flop 305, and sums the data at the even cycle.
By performing the operation of outputting 1 data,
An arithmetic unit that performs the same operation as the operation of the third embodiment of the present invention can be realized.

Although the operation of the present embodiment has been described with respect to five 8-bit pixel data, pixel data having an arbitrary number of bits can be added in the same manner. it can.

In the description of the operation of the present embodiment, the operation of adding five pixel data has been described.
When it is desired to add four pixel data out of one pixel data and subtract one pixel data, input data of bit inversion of the pixel data to be subtracted and input 33
Of the four inputs to be input in the first cycle and the second cycle of 1 and input 332, one is input once,
The remaining three times are realized by inputting 0, and when it is desired to add three pixel data out of five pixel data and subtract two pixel data,
Bit-inverted data of the pixel data to be subtracted is input. Of the four inputs input in the first and second cycles of the inputs 331 and 332, one is input two times and the remaining two times Is realized by inputting 0. If it is desired to add two pixel data out of five pixel data and subtract three pixel data, input data of bit inversion of the pixel data to be subtracted. , Input 331 and input 332, the input of the first cycle and the input of the second cycle are realized by inputting 1 once and inputting 0 the remaining three times. When it is desired to add one pixel data out of five pixel data and to subtract four pixel data, the data of the bit inversion of the pixel data to be subtracted is input and input 331 is performed. All inputs of four to enter the first cycle of the auxiliary input 332 and to the second cycle it can be realized by one.

The selector 31 according to the present embodiment
1 and 312, the flip-flop 321,
322 is output to flip-flops 301 and 30 respectively.
2 is connected to the input of the flip-flops 301, 302, 321, and 322, the initial state of the flip-flops 301, 302, 321, and 322 is set to 0, so that 0 is output from the flip-flops 301 and 302 in cycle 1 and cycle 2. Can,
An arithmetic unit that performs the same operation as the operation described in the third embodiment of the present invention can be made.

(Embodiment 4) FIG. 7 is a circuit diagram of an arithmetic unit according to a fourth embodiment of the present invention.

In FIG. 7, 406 and 407 are full adders, and 406 is a first full adder according to claim 13;
Reference numeral 407 corresponds to the second full adder according to the thirteenth aspect. Carry 1, which is the output of the full adder 406, corresponds to the first carry signal according to the thirteenth aspect. Some sum 1 corresponds to the first sum signal according to claim 13,
The carry 2 output from the full adder 407 corresponds to the second carry signal described in claim 13, and the sum 2 output from the full adder 307 corresponds to the second sum signal described in claim 13. .

The operation of full adder 406 and full adder 407 performs addition on three inputs, outputs a 2-digit addition result, and outputs a lower-order addition result from sum 1 or sum 2. It outputs the result of addition of the upper digit from carry 1 or carry 2.

In the figure, reference numerals 421 and 422 denote 1-bit flip-flop circuits for storing and outputting data in synchronization with the clock signal 430, respectively.
1 is connected to the flip-flop 422, and the flip-flop 421 and the flip-flop 4
22 implements the first data holding means according to claim 14.

Reference numerals 404 and 405 in the figure denote 1-bit flip-flop circuits for storing and outputting data in synchronization with the clock signal 430, respectively, and realize the second data holding means according to claim 14. .

Reference numerals 401, 402, and 403 in the figure denote 1-bit flip-flop circuits for storing and outputting data in synchronization with a clock signal 430, respectively, and realize a third data holding means according to claim 14. It is.

A selector 415 in the figure selects the sum 1 and the carry 1 output from the full adder 406 and outputs the selected sum to one of the three inputs of the full adder 407. This implements the first selecting means described.

In the figure, 413 and 414 are 2 inputs and 1 respectively.
The selector is an output selector, and implements the second selection unit according to the fourteenth aspect.

In the figure, 411 and 412 each have two inputs and one.
The selector is an output selector, and implements the second selection unit according to the fourteenth aspect.

Using the arithmetic unit according to the present embodiment configured as described above, five 8-bit pixel data GA (7: 0) serially input from the LSB in synchronization with clock signal 430. , GB (7: 0), G
C (7: 0), GD (7: 0), GE (7: 0) are added, and an 8-bit output Z (7: 7:
The operation for obtaining 0) will be described.

The input 431 in FIG.
In synchronization with 0, 8-bit pixel data GD (7: 0) is serially input in order from the LSB (GD (0)) in even-numbered cycles.
At least, 0 is input in the first and third cycles.

The input 432 is set so that 0 is input at least in the first cycle in synchronization with the clock signal 430.

The input 433 is synchronized with the clock signal 430 and outputs the 8-bit pixel data GA in odd cycles.
(7: 0) is serially input in order from LSB (GA (0)), and 8-bit pixel data GE (7: 0) is serially input in order from LSB (GE (0)) in even-numbered cycles. To be entered.

The inputs 434 and 435 are synchronized with the clock signal 430, respectively, at least in the odd cycles.
Bit pixel data GB (7: 0) and GC (8: 0) are serially input in order from LSB (GB (0), GC (0)).

The selector 415 sets the sum 1 in the odd cycle.
Is selected, and carry 1 is selected in an even-numbered cycle.

The selector 411 selects the input 431 in the first and third cycles of the odd cycle, selects the output of the flip-flop 422 in the other odd cycles, and selects the input of the flip-flop 422 in the even cycle. 431 is selected.

The selector 412 sets the input 4 in the first cycle.
32, and sum 2 is selected for the other cycles.

The selectors 413 and 414 select the inputs 434 and 435 in the odd cycle, respectively, and select the carry 1 and the carry 2 in the even cycle, respectively.

The operation at the time of such setting will be described with reference to the timing chart shown in FIG. This timing chart shows the clock signal 430 and the flip-flop 4
11 shows the outputs of 01 to 405, 421, and 422 and the output of sum 1, and indicates two of the odd cycle and the even cycle.
In a cycle, one-digit addition is realized.

In cycle 1, the sum 1 of full adder 406 is connected to the input of full adder 407 by selector 415, so that full adder 406 and full adder 4
07, the outputs of the flip-flops 401 to 405 are added, sum1 (0) is output from the sum 2 as the exclusive OR of these five inputs, and the carry 1
And carry signal mi of 2 bits from carry 2 to the upper digit
dcy1 (0) and midcy2 (0) are output.

Midcy1 (0) and midcy2 (0)
Is that midcy1 (0) and midcy1 (0)
Both cy2 (0) outputs 0, and the carry to the upper digit is 1
, One of midcy1 (0) and midcy2 (0) outputs 1 and the other outputs 0, and when the carry to the upper digit is 2, midcy1 (0) and middc
Both y2 (0) outputs 1.

That is, in cycle 1, GA (0), GB (0), and GC (0) output from the flip-flops 401 and 402 and the LSB of the 8-bit pixel data output from the flip-flops 403 to 405 are used. (0)
And the exclusive OR of five inputs su
m1 (0) and carry signal midcy1 to the upper digit
(0), midcy2 (0) are output.

In the cycle 2, the carry 1 of the full adder 406 is connected to the input of the full adder 407 by the selector 415, so that the two full adders are connected in series.

The full adder 406 performs addition on the outputs of the flip-flops 401 to 403 to obtain the sum 1
, Outputs sum2 (0) as an exclusive OR of three inputs, and outputs midcy3 (0) as a 1-bit carry signal from carry 1 to the upper digit.

That is, flip-flops 401 and 40
GD (0) and GE (0), which are the LSBs of 8-bit pixel data, output from the flip-flop 402
Sum1 which is the operation result of the previous cycle output from
(0) is added and the exclusive OR sum2
(0) and a carry signal midcy3 (0) to the upper digit are output.

Here, exclusive OR sum2 is GA (0), GB which is the LSB of five 8-bit pixel data.
This is the exclusive OR of (0), GC (0), GD (0), and GE (0), which is the operation result Z (0).

Full adder 407 outputs 2-bit carry signals midcy1 (0), midcy output from flip-flops 404, 405 as the operation result of the previous cycle.
2 (0) and midcy output from full adder 406
Adds three inputs of 3 (0), outputs a carry signal carry2 (0) of one bit from the carry 2 to the upper two digits, and outputs a one bit digit from the sum 2 to the upper one digit An up signal carry1 (0) is output.

That is, the carry signal m to the three upper digits
idcy1 (0), midcy2 (0), midcy3
By adding (0), GA (0), GB (0), and GC, which are the LSBs of five 8-bit pixel data,
(0), GD (0), GE (0), a 1-bit carry signal carry2 to the upper two digits, generated when adding
(0) and 1-bit carry signal carr to the upper digit of 1 digit
Output y1 (0).

As described above, cycle 2 and cycle 2
Performs operations on five 8-bit LSBs in a cycle,
As the calculation result, in cycle 2, the calculation result Z (0), carry signal carry2 (0) to the second digit upper digit, and carry signal carry1 (0) to the first digit upper digit are output.

In cycle 3, as in cycle 1, sum 1 of full adder 406 is connected to the input of full adder 407 by selector 415, so that full adder 406 and full adder 407 Flip-flop 401
４０405 are added, sum1 (1) is output as the exclusive OR of these five inputs from sum 2, and a carry signal midcy1 (1) of 2 bits from carry 1 and carry 2 to the upper digit is output. ), Midcy2
(1) is output.

That is, in cycle 3, 0 output from flip-flop 401 and flip-flop 40
2, a carry signal carry1 (0) from the lower digit to the upper digit by one digit from the operation result of the previous cycle,
GA (1), GB which is LSB + 1 of 8-bit pixel data output from flip-flops 403 to 405
(1) Performs an operation on GC (1) and outputs an exclusive OR sum1 (1) of five inputs and carry signals midcy1 (1) and midcy2 (1) to the upper digit.

In cycle 4, as in cycle 2, the carry 1 of full adder 406 is connected to the input of full adder 407 by selector 415, thereby connecting the two full adders in series. Become.

That is, flip-flops 401 and 40
LSB + 1 of 8-bit pixel data output from 3
GD (1), GE (2), and flip-flop 4
Sum, which is the operation result of the previous cycle output from 02
1 (1) is added, and the exclusive OR sum is
2 (1) and carry signal midcy3 (1) to the upper digit
Is output.

Here, the exclusive OR sum2 is GA (1), which is LSB + 1 of five 8-bit pixel data.
GB (1), GC (1), GD (1), GE (1),
Carry signal carry1 from LSB to upper digit by one digit
This is the exclusive OR of (0), which is the operation result Z (1).

Full adder 407 outputs 2-bit carry signals midcy1 (1), midcy output from flip-flops 404, 405 as the operation result of the previous cycle.
2 (1) and midcy output from full adder 406
3 (1) is added, a carry signal carry2 (1) of one bit to the upper two digits is output from the carry 2, and a one bit digit to the upper digit of the one digit is outputted from the sum 2. An up signal carry1 (1) is output.

That is, the carry signal m to the three upper digits
idcy1 (1), midcy2 (1), midcy3
By adding (1), GA (1), GB (1), and G (1), which are LSB + 1 of five 8-bit pixel data, are obtained.
1-bit carry signal carry to upper two digits generated when C (1), GD (1) and GE (1) are added
2 (1) and one bit carry signal car to one digit higher digit
ry1 (1) is output.

As described above, in cycle 3 and cycle 4
In the cycle, five 8-bit LSB + 1 operations are executed, and as the operation result, the operation result Z (1)
It outputs a carry signal carry2 (1) to the upper digit of two digits and a carry signal carry1 (1) to the upper digit of one digit.

In cycle 5, as in cycles 1 and 3, selector 415 outputs sum 1 of full adder 406.
Is connected to the input of the full adder 407, the full adder 406 and the full adder 407 add to the outputs of the flip-flops 401 to 405, and the exclusive OR of these five inputs is obtained from the sum 2. As sum1
(1) is output and a carry signal midcy1 (1), middc of 2 bits from carry 1 and carry 2 to the upper digit
Output y2 (1).

That is, in the cycle 5, the carry signal carr from the two-digit lower digit to the two-digit upper digit, which is the operation result three cycles before, output from the flip-flop 401.
y2 (0) and a carry signal carry1 (1) from the lower digit to the upper digit by one digit, which is the operation result of the previous cycle output from the flip-flop 402;
L of 8-bit pixel data output from 03 to 405
Performs an operation on GA (2), GB (2), and GC (2) which are SB + 2, and performs an exclusive OR sum of five inputs
1 (2) and carry signal midcy1 to the upper digit
(2), outputs midcy2 (2).

In cycle 6, as in cycles 2 and 4, carry 1 of full adder 406 is connected to the input of full adder 407 by selector 415, thereby connecting the two full adders in series. Will be.

That is, flip-flops 401 and 40
LSB + 2 of 8-bit pixel data output from 3
GD (2), GE (2), and flip-flop 4
Sum, which is the operation result of the previous cycle output from 02
1 (2) is added and the exclusive OR sum is
2 (2) and carry signal midcy3 (2) to the upper digit
Is output.

Here, the exclusive OR sum2 is GA (2), which is the LSB + 1 of five 8-bit pixel data.
GB (2), GC (2), GD (2), GE (2),
Carry signal carry2 from LSB to upper two digits
This is the exclusive OR of (0) and the carry signal carry1 (1) from LSB + 1 to the upper digit by one digit, and is the operation result Z (2).

Full adder 407 outputs 2-bit carry signals midcy1 (2), midcy output from flip-flops 404, 405 as the operation result of the previous cycle.
2 (2) and midcy output from full adder 406
3 (2) is added, a carry signal carry2 (2) of one bit from the carry 2 to the upper two digits is outputted, and a one bit digit from the sum 2 to the upper one digit is outputted. An up signal carry1 (2) is output.

That is, the carry signal m to the three upper digits
idcy1 (2), midcy2 (2), midcy3
By adding (2), GA (2), GB (2), and G (2), which are LSB + 5 of five 8-bit pixel data,
1-bit carry signal carry to upper 2 digits generated when C (2), GD (2) and GE (2) are added
2 (2) and one-bit carry signal car to one digit upper digit
ry1 (2) is output.

As described above, two of cycle 5 and cycle 6
In the cycle, five 8-bit LSB + 2 operations are executed, and as an operation result, an operation result Z (2)
A carry signal carry2 (2) for a two-digit upper digit and a carry signal carry1 (1) for a one-digit upper digit are output.

Hereinafter, from cycle 5 to cycle 16,
The odd-numbered cycle performs the same operation as cycle 5, the even-numbered cycle repeats the same operation as cycle 6, and the even-numbered cycles of sum 1 to Z (2), Z (3), Z (4), Z
(5), Z (6) and Z (7) are output.

In this way, it is possible to realize addition of five serially input 8-bit data in 16 cycles.

In an arithmetic unit using a three-input adder as in the conventional example, at least 32 cycles are required to realize the addition of five 8-bit serially input data. By using the arithmetic device having the configuration described in (1), it is possible to provide an arithmetic device that can be realized with half the number of cycles, that is, 16 cycles.

Although the operation of the present embodiment has been described with respect to five 8-bit pixel data, pixel data having an arbitrary number of bits can be added in the same manner. it can.

In the present embodiment, a data temporary storage device that delays by two cycles using flip-flops 421 and 422 is realized.
A temporary data storage device that delays by two cycles may be used.

In the description of the operation of the present embodiment, the operation of adding five pixel data has been described.
When it is desired to add four pixel data out of one pixel data and to subtract one pixel data, data of bit inversion of the pixel data to be subtracted is input, and at least the first cycle of the input 431 or the first cycle of the input 432 is input. This can be realized by inputting 1 to one of the first cycle and 0 to the other and inputting 0 to the third cycle of the input 431, and adding three pixel data out of five pixel data to obtain two pixel data. , The data of the bit inversion of the pixel data to be subtracted is input, and at least 1 is input to both the first cycle of the input 431 and the first cycle of the input 432, and
Whether 0 is input in the third cycle of 1 or at least 0 is input in both the first cycle of the input 431 and the first cycle of the input 432 and 1 is input in the third cycle of the input 431; When it is desired to add two pixel data out of five pixel data and to subtract three pixel data, input data of bit inversion of the pixel data to be subtracted, and at least input 4
1 is input to either the first cycle of the 31st cycle or the first cycle of the input 432, and 0 is input to the other.
Can be realized by inputting “1” in the third cycle of “1”.
When subtraction is to be performed for one pixel data, the data of the bit inversion of the pixel data to be subtracted is input, and at least the first cycle of the input 431, the first cycle of the input 432, and the third cycle of the input 431 are input. Can be realized by inputting

(Embodiment 5) FIG. 9 is a circuit diagram of an arithmetic unit according to a fifth embodiment of the present invention.

In FIG. 9, 11000 and 13000
Is a RAM that can simultaneously read and write 1024-bit data, and has 102 pixels.
One line of video signal of up to four pixels can be stored.

The RAM 11000 includes 1101-120
24, 1024 RAMs, and RAM1
Each of 1001 to 12024 can store 128-bit data, and can read and write 1-bit data in synchronization with a clock signal 10030.

The RAM 13000 includes 13001 to 140
24, 1024 RAMs, and RAM1
Each of 1001 to 12024 can store 128-bit data, and can read and write 1-bit data in synchronization with a clock signal 10030.

Reference numeral 15000 denotes an operation array in which 1024 operation units 15001 to 16024 are arranged in parallel.
Each computing element 15001 to 16024 forming the computation array
Is a computing unit exemplified in the first embodiment.

Each of the computing units 15001 to 16024
From M11001 to M12024, a total of 5 bits of RAM data corresponding to each arithmetic unit and data of two RAMs on the right and left sides thereof, and a RAM 13
From among 01 to 14024, a total of 5 bits of RAM data corresponding to each of the arithmetic units and data of two RAMs on the left and right in the vicinity thereof are transferred to any of the five inputs of each of the arithmetic units. Can also be entered.

For example, the arithmetic unit 16001 has the RAM 11
099-RAM12003 and RAM13099-RA
The output of M14003 can be input to any of the five inputs of the arithmetic unit 16001.

Each of the computing units 15001 to 16024
Are RAM 11001 to 12024, RAM 13001
The calculation results can be output to the corresponding RAMs from among.

For example, the arithmetic unit 16001 is the RAM 120
01 and the RAM 14001 can output the operation result.

Further, 5 of each of the arithmetic units 15001 to 16024
One input has constant values 0 and 1 for each input.
Can be given.

Hereinafter, a case will be described in which adjacent three pixels are added to 8-bit pixel data of one line stored in the RAM 11000 and an 8-bit operation result is written to the RAM 13000.

First, pixel data for one line from the RAM 11000 is synchronized with the clock signal
B is sequentially read out one bit at a time over eight cycles in order from B, and outputs to each of the arithmetic units 15001 to 16024 the output of the corresponding RAM and the output of the left and right RAMs in the vicinity of the RAMs 1101001 to 12024, respectively. , To the inputs 133 to 135 of the arithmetic units.

Each operation unit performs the operation described in the first embodiment, and outputs the operation result to L in synchronization with the clock signal.
The data is serially output bit by bit over eight cycles in order from the SB.

Finally, data is serially written to the RAM 13000 one bit at a time starting from the LSB in eight cycles in synchronization with the clock signal 10030.

The reading from the RAM 11000, the execution of the operation, and the writing to the RAM 13000 are executed by a pipeline operation, and the operation can be realized with a throughput of 8 cycles.

In other words, in the conventional arithmetic unit shown in the conventional example, eight lines for one line stored in the RAM 1 are stored.
In the case where the adjacent three pixels are added to the pixel data composed of bits and an 8-bit operation result is written into the RAM 2, a throughput of 16 cycles is required even if the operation can be realized at the minimum. Thus, when the arithmetic unit according to the fifth embodiment of the present invention is used, it can be realized with eight cycles, which is half the number of cycles.

Although the arithmetic device according to the present embodiment uses the arithmetic device according to the first embodiment of the present invention as an arithmetic device forming an arithmetic array, the arithmetic device according to the second embodiment of the present invention is used. It can also be realized by using an arithmetic device.

The arithmetic device according to the present embodiment uses the arithmetic device according to the third embodiment of the present invention as an arithmetic device forming an arithmetic array, and converts one line of pixel data from the RAM 11000 into a clock signal 10030. Synchronously, LSB
From the RAMs 1101 to 12024, the output of the corresponding RAM and the outputs of the two adjacent left and right RAMs are output to This can be provided to the inputs 133 to 135 of each computing unit, and can be realized in 16 cycles. In that case, RAM11000
, One line of pixel data is read out serially from the LSB one bit at a time in 16 cycles in order from the LSB in synchronization with the clock signal 10030.
Of the RAMs 11001 to 12024, the output of the corresponding RAM and the output of the left and right neighboring RAMs are output to the input 33 of each arithmetic unit.
Give odd cycles to 3-335, output two RAMs to the left and
The output of the RAM two to the right is applied to the inputs 333 and 334 of the arithmetic units in even cycles, and each arithmetic unit performs the operation described in the third embodiment, and synchronizes the operation result with the LSB in synchronization with the clock signal.
It outputs one bit at a time over 16 cycles in order. Then, the data is sent to the RAM 13000 in order from the LSB in synchronization with the clock signal.
Write one bit at a time over the cycle. In this way, reading from RAM 11000, execution of operation, RAM 13000
Can be executed by pipeline operation, and an operation can be executed with a throughput of 16 cycles.
Further, in this case, the calculation can be similarly performed by using the calculation device of the fourth embodiment as the calculation device.

It should be noted that the arithmetic unit of the present embodiment has a RAM
By the time the outputs of the RAM 11000 and the RAM 13000 are input to the operation array, the RAM 11000 and the RAM 13
000 data (for example, FIFO)
Memory).

[0175]

As described above, according to the first aspect of the present invention,
The arithmetic unit described in 2, 3, 4, 7, 8, 9, and 10 is a conventional three-input unit for serially adding or subtracting three bits of data sequentially input from the LSB. In the case of using an adder, at least 2 bits of the number of bits required as an operation result
Although it was necessary to perform the operation serially twice as many times, by providing a sum signal generating means for generating a 1-bit sum signal and a carry signal generating means for generating a 2-bit carry signal, By calculating three bits of data sequentially input from the LSB by the required number of bits as the calculation result, the calculation result can be serially output from the LSB.

Further, in the present invention, claims 5, 6, 11,
The arithmetic units described in 12, 13, and 14 are serially LSB
When serially adding or subtracting five pieces of data consisting of a plurality of bits input sequentially from
In the case of using an input adder, it is necessary to perform serial operation at least four times the number of bits required as an operation result, but a sum signal generating means for generating a 1-bit sum signal And a carry signal generating means for generating a 2-bit carry signal, the data consisting of three bits, which are serially input in order from the LSB, is reduced to 2 bits of the number of bits required as an operation result. By performing serial operations twice as many times, the operation result is LS
B can be serially output in order.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an arithmetic unit according to a first embodiment of the present invention.

FIG. 2 is a timing chart of the operation of the arithmetic unit according to the first embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of an arithmetic unit according to a second embodiment of the present invention.

FIG. 4 is a timing chart of the operation of the arithmetic unit according to the second embodiment of the present invention;

FIG. 5 is a circuit configuration diagram of an arithmetic unit according to a third embodiment of the present invention.

FIG. 6 is a timing chart of the operation of the arithmetic unit according to the third embodiment of the present invention.

FIG. 7 is a circuit configuration diagram of an arithmetic unit according to a fourth embodiment of the present invention.

FIG. 8 is a timing chart of the operation of the arithmetic unit according to the fourth embodiment of the present invention.

FIG. 9 is a block diagram of an arithmetic unit according to a fifth embodiment of the present invention.

FIG. 10 is a block diagram of a conventional arithmetic unit.

FIG. 11 is a circuit configuration diagram of a conventional arithmetic unit.

[Explanation of symbols]

101 to 105, 201 to 205, 221, 222, 3
01-305, 321-323, 401-405, 42
1,422,1,2,3 flip-flops 106,107,206,207,306,307,4
06,407,5 Full adder 111,112,211,212,311-313,4
11 to 415 selectors 130, 230, 330, 430, 10030, 10
Clock signal 11000, 13000, 1, 2 RAM block 11001 to 12024, 13001 to 14024 R
AM 15000,3 Arithmetic array 15001 to 16024 Arithmetic unit

Claims (14)

[Claims] A sum signal generating means for generating a 1-bit sum signal; and a carry signal generating means for generating a 2-bit carry signal, wherein the sum signal generating means includes a 5-bit first signal. For the input signal, an exclusive OR is output as a sum signal, and the carry signal generating unit outputs a first carry signal and a second carry signal, and outputs the first input signal. When the number of bits whose value is 1 is 1 or less, both outputs of the first carry signal and the second carry signal become 0, and among the first input signals, When the number of bits whose value is 1 is 2 or more and 3 or less, the output of one of the first carry signal and the second carry signal is 1 and the other output is 0, When the number of bits whose value is 1 is 4 or more in the input signal of the above, the first carry signal and the second digit An arithmetic unit characterized in that both outputs of the raising signal become 1. 2. The arithmetic unit according to claim 1, wherein said first carry signal, said second carry signal, and a second input signal comprising three bits are stored in synchronization with a clock signal. And a data holding means for outputting the data, wherein an output of the data holding means is provided as the first input signal to the carry means and the sum generation means. 3. The arithmetic unit according to claim 1, wherein a two-bit signal comprising the first carry signal and the second carry signal or a third input signal comprising two bits, The first selecting means for selecting any two bits and outputting as a first output signal, the second input signal consisting of three bits, and storing the first output signal in synchronization with a clock signal And a data holding means for outputting the data, wherein an output of the data holding means is provided as the first input signal to the carry means and the sum generation means. 4. The arithmetic unit according to claim 1, wherein a two-bit signal comprising said first carry signal and said second carry signal is stored and output in synchronization with a clock signal. One data holding means, a second data holding means for storing and outputting a second input signal of 5 bits in synchronization with a clock signal, and a second data holding means.
Bit output or the 2-bit output of the 5-bit output of the second data holding means,
First selecting means for outputting as a first output signal, wherein the two-bit output of the first selecting means and the 5-bit output of the second data holding means, An arithmetic unit, wherein an output of three bits excluding bits is provided as the first input means to the carry means and the sum generation means. 5. The arithmetic device according to claim 1, wherein a two-bit signal comprising said first carry signal and said second carry signal is stored in synchronization with a clock signal, and said first carry signal is stored in said first carry signal. First data holding means for outputting a 2-bit output as an output, second data holding means for storing the sum signal in synchronization with a clock signal and outputting a 1-bit output as a second output; And a third data holding means for storing a second input signal consisting of 2 bits in synchronization with a clock signal and outputting a 4-bit output as a third output; An input signal, storing the data in synchronization with a clock signal, a fourth data holding means for outputting a 1-bit output as a fourth output, and selecting one of the second output and the fourth output; 1 as the fifth output
Selecting means for outputting an output composed of bits, wherein the third output and the fifth output are provided as the first input signal to the carry means and the sum generating means. Arithmetic unit. 6. The arithmetic unit according to claim 1, wherein a two-bit signal composed of said first carry signal and said second carry signal is stored in synchronization with a clock signal, and said first carry signal is stored in said first carry signal. A first data holding means for outputting 2 bits as an output; storing the first output and a second input signal consisting of 2 bits in synchronization with a clock signal; A second data holding means for outputting the sum signal, a selecting means for selecting a third input signal consisting of 1 bit, and outputting the selected signal as a third output; A third data holding device that stores the data in synchronization with the third output and outputs one bit as a fourth output, wherein the second output and the fourth output are used as the first input signal, Raising means and the sum generating means. Arithmetic unit to do. 7. A first full adder for generating a first sum signal and a first carry signal, and a second full adder for generating a second sum signal and a second carry signal. Wherein the first sum signal is input to any one of the inputs of the second full adder, and the first input signal consisting of 5 bits is 3 bits of the first full adder. And 3 of the second full adder
An arithmetic unit characterized by being connected to two-bit inputs other than the input of the first sum signal among the bit inputs. 8. The arithmetic unit according to claim 7, wherein said first carry signal, said second carry signal, and a second input signal comprising 3 bits are stored in synchronization with a clock signal. And an output of the data holding means, wherein the output of the data holding means is provided as the first input signal to the first full adder and the second full adder. apparatus. 9. The arithmetic unit according to claim 7, wherein the signal is a two-bit signal composed of the first carry signal and the second carry signal, or a third input signal composed of two bits. The first selecting means for selecting any two bits and outputting as a first output signal, the second input signal consisting of three bits, and storing the first output signal in synchronization with a clock signal And an output of the data holding means, wherein the output of the data holding means is provided as the first input signal to the first full adder and the second full adder. apparatus. 10. The arithmetic unit according to claim 7, wherein a two-bit signal comprising said first carry signal and said second carry signal is stored and output in synchronization with a clock signal. One data holding unit, a second data holding unit that stores and outputs a second input signal composed of 5 bits in synchronization with a clock signal, and a 2-bit output of the first data holding unit, First selecting means for selecting any two-bit output from the five-bit output of the second data holding means and outputting the selected signal as a first output signal; And the three-bit output of the second data holding means, excluding any one of the two bits, are used as the first input means to provide the first full addition. And the second full adder An arithmetic unit characterized by the following. 11. The arithmetic unit according to claim 7, wherein a two-bit signal comprising said first carry signal and said second carry signal is stored in synchronization with a clock signal, and said first carry signal is stored in said first carry signal. First data holding means for outputting a 2-bit output, and second data holding means for storing the second sum signal in synchronization with a clock signal and outputting a 1-bit output as a second output; A third data holding means for storing the first output and a second input signal of 2 bits in synchronization with a clock signal and outputting a 4-bit output as a third output; A fourth data holding unit that stores a third input signal in synchronization with a clock signal and outputs a one-bit output as a fourth output, and any one of the second output and the fourth output. Select the first output as the fifth output. Selecting means for outputting the third output and the fifth output as the first input signal to the first full adder and the second full adder. An arithmetic unit characterized by the following. 12. The arithmetic unit according to claim 7, wherein a two-bit signal comprising said first carry signal and said second carry signal is stored in synchronization with a clock signal, and said first carry signal is stored in said first carry signal. A first data holding means for outputting 2 bits as an output; storing the first output and a second input signal consisting of 2 bits in synchronization with a clock signal; A second data holding means for outputting the sum signal, a selecting means for selecting a third input signal consisting of 1 bit, and outputting the selected signal as a third output; A third data holding device that stores the data in synchronization with the third output and outputs 1 bit as a fourth output, wherein the second output and the fourth output are used as the first input signal, That are given to one full adder and the second full adder. An arithmetic unit characterized by the following. 13. A first full adder for generating a first sum signal and a first carry signal, and a second full adder for generating a second sum signal and a second carry signal. And a first selection unit that selects one of the first sum signal and the first carry signal and outputs 1 bit as a first output,
The first output is input to any one of the inputs of the second full adder, and the first input consisting of 5 bits is
Of the 3-bit input of the first full adder and the 3-bit input of the second full adder, the input is connected to the input of 2 bits other than the input of the first output. An arithmetic unit characterized by the above-mentioned. 14. The arithmetic unit according to claim 13, wherein
The second carry signal, stored in synchronization with the clock signal, the first data holding means to output as a second output, the first carry signal, and the second carry signal And a second input consisting of 2 bits are selected, and 2 bits are selected as a third output.
A second selecting means for outputting an output composed of bits, a signal of 2 bits composed of the second sum signal, the signal of the second output, and a third input composed of 2 bits. A third selecting means for selecting and outputting a 4-bit output as a fourth output, and a second data holding means for storing the third output in synchronization with a clock signal and outputting as a fifth output Means, and a third data holding means for storing a 3-bit signal of the fourth output and a fourth input consisting of 1 bit in synchronization with a clock signal and outputting as a sixth output, The fifth output is input as 2 bits input to the second full adder among the first inputs, and the sixth output is the second input of the first input. The feature is that it is input as 3 bits input to one full adder That computing device.