JPS6182234A - Multiplier circuit - Google Patents

Abstract

PURPOSE:To realize high speed and high integration, and also to execute easily initializing of an accumulator register by using cumulative data as only one input signal to be added, and adding it simultaneously in an addition process of the partial product of each digit of a multiplying circuit. CONSTITUTION:A multiplier Xin and a multiplicant Yin are supplied to a full adder array 21 being a digital multiplier through registers 1, 2, respectively. Product data of a multiplier and a multiplicant obtained from the full adder array 21 is supplied to an accumulation register 7 to which a clock signal CK is supplied through a carry foresight circuit CLA22. An output of the accumulator register 7 is outputted from an external terminal 4, also supplied to an accumulator controlling circuit 9, brought to data conversion so that it is added and subtracted to and from product data of the full adder array 21 by a cumulative signal ACC and an adding and subtracting signal ADD/SUB, inputted selectively to an addition process of the partial product of each digit of the full adder array 21 through a line 19 and added.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a multiplier circuit that is also capable of accumulation by addition or subtraction of multiplied data.

[Technical background of the invention]

Generally, this type of multiplier circuit (multiplier-accumulator circuit) is configured as shown in FIG. 7, for example. That is, the multiplier Xin and the multiplicand Y l n are respectively X,
Y registers 1, 2 are fed, and these input data are fed via lines 11.12 to a full adder array 3 as a dinotal multiplier. This full adder array 3
The product data of the multiplier Xjn and the multiplicand Yin obtained from the above is supplied to the summation circuit 5 via a carry look-ahead circuit (hereinafter simply referred to as a CLA circuit) 4 for each bit. The output data of this summation circuit 5 is sent to a CLA circuit 6 for each bit.
via the accumulator register 7, which is supplied with the clock signal CK. The output data of accumulator register 7 is
It is output from external terminal 8 and is also supplied to accumulator control circuit 9 via line 17. This accumulator control circuit 9 includes an accumulation signal ACC and an addition/subtraction signal ADD/SU.
Two control signals B are supplied, and in response to these control signals, the output data of the accumulator register 7 is converted into product data supplied from the full adder array 3 to the summation circuit 5 via the CLA circuit 4. Data is converted so that addition and subtraction are performed. And this converted data is line 1
9 to the summation circuit 5 for accumulation.

FIG. 8 shows a specific configuration example of the circuit surrounded by the dashed-dotted line 20 in FIG. A total circuit is realized. In Figure 8, the blocks A, H, and F surrounded by squares are bit products, respectively.
A half adder with a bit product input and a full adder with a bit product input are shown, and the circled H and F are respectively a simple half adder (including a bit product input) and a full adder. This shows that.

The ANDer is supplied with a boxed al and a signal TC that determines whether the block is signed or unsigned. This is used to correct the sign bit along with the full adder, and Xs ''' TC-X15 Ys := 'rc HY 15 a=Tc, (X15+Y15) +TC(X15 ・
Yts). Since the correction and generation of this code bit is well known, the explanation thereof will be omitted.

Now, if the multiplier is X and the multiplicand is Y, then as is well known, the product P is P=X-Y (1). Here, the multiplier X and the multiplicand Y can be expressed by the following equations (2) and (3), respectively.

X=-Xs・215+ΣXi ・Z'-'=-Xa ・
215-1-x* ・-・(2) j=1 Y=-Ys・215+ΣYi ・2 '-' =-Ys
・Z15+y* ・, (3) 1 Therefore, the product P is: P=X*・Ys−Xs−Ys・2−Ys・Xs・215
+X5-Ya -230 = (Xs-Ys -Xs-Ys)・2 +)(*・7
*+X8・Ys・Z+Ys−W;・215+Xs・2
+Y8・215...(4) Totoru. Here, Xs and Ys are the inverted bits of X* and Y*, respectively. Furthermore, if a rounding function at the 15th bit (indicated by RND in FIG. 8) is provided, the final output data Q of the multiplier 3 will be IQ=P-1-2J.

When the output data R of the accumulator register 7 is added or subtracted from the output data Q of the multiplier 3 by the summation circuit 5,
The output data S of the summation circuit 5 are each as follows: S=Q0ΣR1・21-1...(
5) i Or, it can be expressed as 5=Q-ΣR1·2'-1...(6) i=1. In this circuit, m-35
, which is equal to the number of bits in accumulator register 7,
In other words, it has enough bit length to accumulate multiple products output from multiplier 3, so it is longer than twice the bit length of each input register 1 and 2 by 3 bits for expansion. It is equipped with a bit.

[Problems with background technology]

Incidentally, it is desired that the multiplier and the accumulator be faster, but as mentioned above, the multiplier 3 and the summation circuit 5 are separated,
When a multiplier-accumulator is implemented using each independent adder, first looking at the signal propagation time of multiplier 3, Q15, which is the immediate digit, has the maximum number of elements to be added as a path. , and the sum signal propagation time a of the 16 stages of full adders to generate product data QI5, and further product data Q16 to Q, ? The output delay time of the multiplier 3 is the sum of the carry signal propagation times of the 15 stages of full adders and the 4 stages of half adders for generating 4.

Furthermore, the delay time of the carry signal propagating from the lower 11'f bit to the first bit in the full adder of the summation circuit 5 is added for accumulation, making it difficult to achieve high speed.

Therefore, in order to increase the speed, the CLA circuit 4.6 is provided, but the CLA circuit 4.6 is provided only in the final stage adder of the multiplier 3.
When the circuit 4 is provided, although the generation of the product data Q of the multiplier 3 can be made faster, the propagation time of the carry signal of the adder of the summing circuit 5 becomes slower. On the other hand, only the adder of the summation circuit 5 has C
When the I, A circuit 6 is provided, the propagation time of the carry signal that generates the product data Q of the multiplier 3 is slow, so providing the CLA circuit only on either side has little effect. Therefore, in order to achieve high speed, the multiplier 3
It is necessary to provide a CLA circuit for each of the and summation circuits 5, and providing two CLA circuits 4.6 in this manner poses a problem in realizing high integration.

In addition, if you want to invalidate the accumulated data output from the accumulator register 7, as soon as you initialize it or set any data, you can connect the accumulator register 7 and the external terminal (input/output common terminal) A three-state buffer controlled by a field control signal is provided between the CLA circuit 6 and the accumulator register 7 to set its output to a high impedance state, and a preload control circuit is provided between the CLA circuit 6 and the accumulator register 7. A selection control signal must be supplied to select the external input signal. The timing of each signal required for these series of operations is completely different from the timing required for normal multiplication, and there is also the drawback that the control becomes complicated.

[Purpose of the invention]

This invention was made in view of the above circumstances,
The object is to provide a multiplier circuit which can be operated at high speed and highly integrated, and which can also simplify the initialization of the accumulator register.

[Summary of the invention]

In other words, in this invention, in order to achieve the above object, instead of clearly separating the multiplier and the summation circuit functionally as in the conventional case, the accumulated data should also be simply added together. By considering it as an input signal and inputting and adding this accumulated data to the addition process of the partial products of each digit in the multiplier circuit, high speed is achieved, and the initialization control signal is used in the accumulator register. This allows the contents of the register to be easily initialized by simply inputting .

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows the configuration, and in the figure, the same components as in FIG. 7 are given the same reference numerals.

The multiplier Xin and the multiplicand Yin are fed to the X and Y registers 1 and 2, respectively, and their input data is on line 11.
．． 12 to a full adder array 21 as a digital multiplier. The product data of the multiplier Xin and the multiplicand Yin obtained from the full adder array 21 is sent to the clock signal CK via the CLA circuit 22 for each bit.
is supplied to an accumulator register 7, which is supplied with . The output data of the accumulator register 7 is output from an external terminal 8 and is also supplied to an accumulator control circuit 9 via a line 17. Two control signals, an accumulation signal ACC and an addition/subtraction signal ADD/SUB, are supplied to the accumulator control circuit 9, and the output data of the accumulator register 7 is controlled by the full adder according to these control signals. The data is converted so that it is added to or subtracted from the product data of the array 21. Then, this converted cumulative data is selectively inputted via line 19 to the addition process of the partial products of each digit in the full adder array 21 and added.

FIG. 2 shows the detailed structure of the full adder array 2 and the CLA circuit 22 surrounded by the dashed line 23 in FIG. The accumulated data RO and R1 from the accumulator registers (not shown) are respectively sent to the final stage full adder corresponding to each bit, and also to the accumulated data R2 to R30.
are each supplied to the full adder at the stage before the final stage of the digit corresponding to that bit, and the accumulated data R31 to R34 are each supplied to the half adder at the stage before the final stage corresponding to that bit. be done. Further, each final stage full adder is supplied with a carry signal output from an adder in the stage immediately preceding the final stage of the adjacent lower digit. This configuration considers that the accumulated data is simply one input signal to be added, and inputs and adds this accumulated data to the process of adding partial products of each digit in the multiplier 21. Chiru.

According to this configuration, by providing one CLA circuit 22, speeding up becomes possible. In other words, if we look at the signal propagation time in the circuit shown in FIG. The sum of the propagation times of the carry signals becomes the delay time as a multiplier-accumulator. Since the CLA circuit only requires one circuit, it can be highly integrated compared to conventional circuits. However, if a significant increase in speed is not desired, the CLA circuit 22 may not be provided.

Figure 3 shows a configuration example for further increasing the speed of the circuit shown in Figure 2 above, in which a partial product of the same digit is divided into two, for example into an odd number stage and an even number stage, and these are added in parallel. Then, in the final stage, the sums of the partial products obtained from each of the odd-numbered stages and the even-numbered stages are added. As a result, the number of stages for adding partial products can be reduced to about half, and speeding up can be achieved. Thanks to the increased speed achieved by using the CLA circuit 22, the speed can be significantly increased. The parallel addition method used in FIG. 3 above is a well-known technique, but what should be noted here is that the accumulated data R may be input to any adder for each digit. The circuit shown in FIG. 3 is an optimal design example in which accumulated data R is input in order to increase the speed.

FIG. 4 shows an example of the configuration of the accumulator Renostaph.

ing. Output data from the multiplier circuit 100 having an accumulation function is supplied to the data input end of the accumulator register 7, and is taken into the accumulator register 7 based on the clock signal CK. The output data obtained from the data output terminal Q of the accumulator register 7 is supplied to the accumulator control circuit 9 via the line/17, and the output data of this accumulator control circuit 9 is used for performing the accumulation. Multiplier circuit 1 via line 19 to
Sent on 6o. An initialization signal R8 is supplied to the clear terminal CLR of the accumulator Renostaph, and this signal R8
When is "PAL", the contents of the accumulator lenostaf are initialized to "0" and "1". The accumulator control circuit 9 includes an AND gate 9+ to which the accumulation signal ACC and the output of the accumulator register 7 are supplied;
Exclusive OR circuit (hereinafter abbreviated as EXOR circuit) 9 to which the output of 1 and the addition/subtraction signal ADD/SUB are supplied.
The output of this EXOR circuit 9□ is supplied to the multiplier circuit 100 via line 19. Note that the accumulation signal ACC is assumed to be "1" when accumulating, and 0 when not accumulating, and the addition/subtraction signal ADD is
/SUB shall be 1'' when subtracting, and II OII when accumulating or adding. Therefore, the output line 19 of the accumulator control circuit 9 is The data from the accumulator register 7 is output, and on the other hand, when subtracting, the data obtained by inverting the output of the accumulator register 7 is output.When not accumulating, the data is output from the accumulator Renostaf. 0'' is output regardless.

When subtracting a here, as is well known, it is necessary to take two's complement, so not only do we invert the output of the accumulator register 7, but we also use it as an addition input for the least significant digit. ) 11 - signal SUB to It I
Of course, you can do this by inputting II.

According to this configuration, when the accumulator register 7 is initialized, all bits are forcibly set to II OII or "1" data. In addition, it is initialized.
Or, if you want to arbitrarily set the data of °゛1'' in each bit, you can configure it as shown in Fig. 5. In the 5th area, the same components as in Fig. 4 are given the same reference numerals. Therefore, the explanation thereof will be omitted. That is, the multiplier circuit 1000
Output d, and gate 24. An inverted signal of the initialization signal R8 is supplied to the other input terminal of the AND gate 241.

The initialization signal R8 is supplied to one input terminal of the AND gate 242, and the output of the oscillator 25 is supplied to the other input terminal of the AND gate 242. The output of each is
) 26 such that the output of the or-dart 26 is supplied to the data input end of the accumulator register 7.

In the configuration as described above, the oscillator 25 has a value of 0 to be set in the accumulator register 7 of the pit at the time of initialization.
An initial value of # or ``1'' is stored, and when initialization is desired, the initialization signal R8 becomes ``1'', so the AND dart 242 is turned on and the signal 241 is turned off. Therefore, it is wandered. On the other hand, when not initializing, the initialization signal R8 is set to 0'', the AND dart 241 is turned on, and the 24
2 is off. As a result, the data output from the multiplier circuit 100 is set in the accumulator register 7 via the AND/DART 241 and the OR/DART 26. Therefore, in such a configuration, the timing for initialization is 1/7 of the clock signal CLK, so initialization can be performed even while an operation is being executed, and the extra time required for initialization (
cycles) and complex timing operations are not required.

Note that in this case, the data selection circuit is constructed by the AND gates 24., 242 and the orate gate 26.
It is sufficient if the output data of the multiplier circuit 100 or the output data of the oscillator 25 can be selected according to the initialization signal R8.
It goes without saying that the OS transistor may be used simply as a transfer gate, and that the configuration is not limited to the above-mentioned configuration.

FIG. 6 shows another embodiment of the present invention, showing a configuration in which a preload control circuit is provided. In FIG. 6, the same components as those in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted. That is, the output of the full adder array 21 as a digital multiplier is sent to the selection control signal SC via the CLA circuit 22 for each bit.
is supplied to the Noriload control circuit 27 to which is supplied. The output of this Noriload control circuit 27 is the clock signal CK
is supplied to an accumulator register 7, which is supplied with . The output of the accumulator register 7 is fed to a three-state buffer 28, which is fed with a field control signal FC, and via line 17 to an accumulator control circuit 9. Above 3
The output of the status buffer 28 is outputted via an external terminal (input/output common terminal) 8.

The external input data input to the external terminal 8 is supplied to the preload control circuit 27 via the line 18, and the accumulator register 7 is supplied to the preload control circuit 27 via the line 18.
It is configured so that it can be set to

According to such a configuration, arbitrary external data can be set in the multiplier circuit, and the arbitrary data can be accumulated in the multiplication result by the full adder array 21.

Note that the full adder array 21 and the CLA circuit 22 are as follows:
The configuration shown in FIG. 2 or 3 may be used.

〔Effect of the invention〕

As described above [7], according to the present invention, a multiplier circuit can be obtained which can achieve high speed and high integration, and can also simplify the initialization of the accumulator register.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a multiplier circuit according to an embodiment of the present invention, FIG. 2 is a diagram illustrating the specific configuration of the full adder array and CLA circuit in FIG. 1, and FIG.
The figures are diagrams for explaining other configuration examples of the full adder array and the CLAl path in Figure 1, Figures 4 and 5 are diagrams for explaining the initialization of the accumulator register, and Figure 6 is a diagram for explaining the initialization of the accumulator register. Figure 7 is a block diagram for explaining another embodiment of the present invention, Figure 7 is a block diagram for explaining a conventional multiplier circuit, and Figure 8 shows the detailed configuration of some of the circuits in Figure 7 above. FIG. 1...X register, 2...X register, 7...accumulator register, 8...external terminal, 9...accumulator control circuit, 21...full adder array (digital multiplication device), 22... Carry look-ahead circuit (CLAM path), 27.
...Preload control circuit, 28...3-state buffer,
Sc, . . . section control signal, Fc, . . . field control signal. Applicant's representative Patent attorney Takehiko Suzue Figure 4 Figure 5

Claims (12)

[Claims] (1) A multiplier circuit characterized by comprising the following components a to f. a. X register into which the multiplier X is input; b. Y register into which the multiplicand Y is input; c. a digital multiplier into which the multiplier X and the multiplicand Y are input; d. Accepts multiplication output data from the multiplier. an accumulator register coupled to e. an accumulator control circuit for selectively sending output data from the accumulator register to the digital multiplier; f. a full adder array forming the digital multiplier; By combining the data of the corresponding digit in the accumulator register in the process of generating a partial product of the multiplier X and the multiplicand Y by each cell of Accumulation means for accumulating output data. (2) The output data of the accumulator register in the accumulating means is selectively input to each digit of each cell of a full adder array constituting the digital multiplier. The multiplier circuit according to item 1. (3) The accumulator register further comprises input means for inputting initial value data, and initializes the data of the multiplier register in response to a control signal. Multiplier circuit as described. (4) The accumulator control circuit, in response to a control signal, adds or subtracts the output data of the accumulator register to the product data of the digital multiplier, or simply multiplies the product data without adding anything. 2. The multiplier circuit according to claim 1, further comprising means for operating the multiplier circuit as a multiplier circuit. (5) A multiplier circuit characterized by comprising the following components a to g. a, an X register into which the multiplier X is input; b, a Y register into which the multiplicand Y is input; c; a digital multiplier into which the multiplier X and the multiplicand Y are input; d) a full adder array forming the digital multiplier. a carry lookahead circuit provided at the last stage of each digit; e, an accumulator register coupled to accept the multiplication output data from the carry lookahead circuit; f, an accumulator register coupled to receive the multiplication output data from the carry lookahead circuit; an accumulator control circuit for selectively sending data to the digital multiplier, g. an accumulating means for accumulating the product data of the digital multiplier and the data output from the accumulating register by combining data of corresponding digits in the multiplier register; (6) The output data of the accumulator register in the accumulating means is selectively input to each digit of each cell of a full adder array constituting the digital multiplier. The multiplier circuit according to item 5. (7) The accumulator register further includes input means for inputting initial value data, and initializes the data of the multiplier register in response to a control signal. Multiplier circuit as described. (8) The accumulator control circuit, in response to a control signal, adds or subtracts the output data of the accumulator register to the product data of the digital multiplier, or simply multiplies the product data without adding anything. 6. The multiplier circuit according to claim 5, further comprising means for operating the multiplier circuit as a multiplier circuit. (9) A multiplier circuit characterized by comprising the following components a to h. a, an X register into which the multiplier X is input, b, a Y register into which the multiplicand Y is input, c, a digital multiplier into which the multiplier X and the multiplicand Y are input, d, multiplication output data from the digital multiplier, and a preload control circuit into which data from the outside is inputted via an external terminal and controlled by a selection control signal; e, an accumulator register coupled to receive an output of the preload control circuit; f, the accumulator. an accumulator control circuit for selectively sending the output data from the register to the digital multiplier; g. the output data of the accumulator register is supplied and controlled by a field control signal; h, the data of the corresponding digit in the accumulator register in the process of generating the partial product of the multiplier accumulating means for accumulating the product data of said digital multiplier and the data output from said accumulator register by combining said digital multiplier; (10) The output data of the accumulator register in the accumulating means is selectively input to each digit of each cell of a full adder array constituting the digital multiplier. The multiplier circuit according to item 9. (11) Claim 9, wherein the accumulator register further includes input means for inputting initial value data, and initializes the data of the multiplier register in response to a control signal. Multiplier circuit as described. (12) The accumulator control circuit, in response to a control signal, adds or subtracts the output data of the accumulator register to the product data of the digital multiplier, or simply multiplies the product data without adding anything. 10. The multiplier circuit according to claim 9, further comprising means for operating the multiplier circuit as a multiplier circuit.