JPH1083355A - Memory checking mechanism for vehicle controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mechanism executing a sure memory check while avoiding a bad influence on the other processings and ABS(anti-lock braking system) control at the time of memory check. SOLUTION: A computer 2 controls ABS every 10ms and is provided with ROM 12 storing a program for ABS control and an abnormality detecting means checking the program at every prescribed byte in the storing area of ROM 12 when the computer 2 is started. Then the abnormality detecting means is operated in the idle time of a program executing time from the starting of the execution of the program to the finish of the 10ms period of the computer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vehicle control device such as an anti-lock brake device (ABS).
In particular, it relates to a memory check mechanism of a computer.

[0002]

2. Description of the Related Art Recently, in a vehicle control device that controls an engine, an ABS, and the like by a microcomputer, in order to prevent unauthorized modification of a vehicle control program described in a memory, the program is controlled. Various techniques for checking are provided, one of which is described in Japanese Patent Application Laid-Open No. 7-042609.

[0003] In brief, the memory check mechanism checks a memory storing a program for controlling an engine. When the memory check mechanism is checked, the memory check mechanism is activated every predetermined time when the computer is started. A memory check is performed for each predetermined byte in the storage area of the memory. When the engine speed is 4,000
In a high rotation state of 0 rpm or more, rotation interrupt processing occurs frequently and the load on the engine control processing increases, which causes a delay in arithmetic processing and concerns about an adverse effect on engine control. .

[0004]

However, in the conventional memory check mechanism, as described above, the program is checked at every predetermined time and at every predetermined byte of the storage area of the memory to detect an abnormality. For example, when the wheel speed signal is captured by an external interrupt, for example, when the vehicle speed increases, the number of external interrupts increases, the wheel speed calculation processing load increases, and the memory check of a predetermined byte is completed. It may not be possible or adversely affect engine control.

[0005] When the engine speed is high at 4,000 rpm or higher, the memory check is forbidden as described above because of concern about the adverse effect on the engine control. If a memory error occurs at a speed of 000 rpm or more, this error cannot be detected,
Since the engine control process is performed in the state of the memory abnormality, the engine control may be adversely affected.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems in the conventional memory check mechanism. A computer that controls the vehicle, a memory that stores a program for controlling the vehicle, and when the computer is running, checks the program for each predetermined byte in a storage area of the memory to check for abnormalities. In the memory check mechanism of the vehicle control device having a program abnormality detection means for detecting, the program execution time from the start of execution of the program for controlling the vehicle to the end of a predetermined period of the computer is reduced to an idle time of the program execution time. Activating the program abnormality detecting means.

According to a second aspect of the present invention, the program abnormality detecting means checks a memory check by an added value of memory contents from a start address to an end address.

According to a third aspect of the present invention, the program abnormality detecting means checks the memory by an exclusive OR of memory contents from a start address to an end address.

According to the present invention, the program abnormality detecting means checks the memory by at least one of an added value of memory contents from a start address to an end address and an exclusive OR. It is characterized by.

According to the above configuration, for example, in a background job in which ABS control processing is being performed, a series of processing required for ABS control is completed, and the calculation cycle becomes, for example, 1
During the free time until 0 ms elapses, the memory check is performed to the extent possible, and the memory check is temporarily interrupted when 10 ms elapses, and when the series of ABS control processing is terminated, the previous time is temporarily interrupted again. Resume checking from address. For this reason, other processing and ABS
Memory check can be performed without adversely affecting control.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an overall configuration in which a vehicle control device of the present invention is applied to an ABS control device. In FIG. Interface circuit,
5 is a power supply regulator.

The microcomputer 2 includes front and rear wheel speed sensors 6a, 6b, 6c and a brake switch 7.
Is input via the input interface circuit 3 and the power supply 8 is turned on by the ignition switch 9.
And it is started by being inputted through the power supply regulator 5.

The microcomputer 2 includes a CPU 1
0, RAM 11, ROM storing control program
12, an input / output port (I / 0) 13, a timer 14, and an A / D converter 15.

The CPU 10 executes processing for controlling the operation of various devices for controlling the vehicle. Specifically, the CPU 10 inputs the wheel speed sensors 6a to 6c input through the input interface circuit 3. On the basis of the information signal from the brake switch 7, the arithmetic processing is performed according to a program stored in the ROM 12, and a drive signal is output to the ABS hydraulic unit 16 via the output interface circuit 4.

The ABS hydraulic unit 16 is controlled by a program stored in the ROM 12 so as to exhibit optimum brake performance without brake lock. However, the program is changed contrary to the intention of the vehicle manufacturer. If the brakes are applied, or if the memory is destroyed for some reason, the optimal braking state may not be exhibited. For this reason, a memory check is performed based on the following various flows.

FIG. 2 shows the ABS background job flow, FIGS. 3 to 5 show the wheel pulse measurement processing flow, and FIG. 6 shows the internal timer interrupt processing flow. FIG. 7 shows a memory check flow.

The background job flow routine shown in FIG. 2 performs processing once every 10 ms. First, steps 1 (S1) to 3 (S3)
In the block (1), the timer value (JOB_C) that counts up every 1 ms in the internal timer interrupt process (1 ms) shown in FIG. 6 is monitored, and in step 1 (S1),
JOB_C ≧ 10 is determined. In other words, in response to the lapse of 10 ms from the previous processing, if the time is shorter than 10 ms, the processing returns to the original state.
Go to 2). In this step 2 (S2), the following 1
In order to determine 0 ms, the timer value (JOB_C) is cleared, and the process proceeds to step 3 (S3). Here, a fail-safe process, which is an abnormality diagnosis of the ABS control device, is performed. Next, in step 4 (S4), the timer value (JOB_C)
Is determined to be greater than or equal to 2, and waits until it becomes 2 or more. When it becomes 2 or more, wheel speed calculation processing is performed in step 5 (S5). Here, the wheel speed calculation is performed based on the results of the wheel speed pulse measurement shown in FIGS.

Subsequently, the process proceeds to step 6 (S6), and waits until the timer value (JOB_C) becomes 4 or more. When the timer value (JOB_C) becomes 4 or more, the process proceeds to step 7 (S7). The pseudo vehicle speed calculation process is performed in (). Next, in step 8 (S8), the process waits until the timer value (JOB_C) becomes 6 or more, and when it becomes 6 or more, the ABS control arithmetic processing is performed in step 9 (S9). Then, Step 1
At 0 (S10), the process waits until the timer value (JOB_C) becomes 8 or more, and when it becomes 8 or more, a ROM check process (memory check) is performed in step 11 (S11). This step 11 (S1
In 1), the processing is continued until the timer value (JOB_C) reaches 10 by the internal timer interrupt process 1 ms. When the timer value (JOB_C) reaches 10, the memory check is temporarily suspended and the process proceeds to step 1 (S1). Transition.

Then, Step 1 (S1) to Step 3
A background job is executed again by (S3),
In the memory check of step 11 (S11), the memory check is restarted from the address temporarily suspended last time.

Here, the processing flow shown in FIGS.
Front and rear wheels (FR, FR) output from the wheel speed sensors 6a to 6c.
The number of pulses of the pulse waveform obtained by converting the wheel speed signal (FL, RR) into a rectangular wave in the interface circuit 3 is measured.

In the processing flow shown in FIG. 6, first, in step 20 (S20), a timer value (JOB_C) that counts up every 1 ms is counted up, and then in step 21 (S21), the step of FIG. The ABS control calculation result calculated in step 9, such as solenoid drive, actuator relay drive, and motor relay drive signals, is output as a port. Then, in step 22 (S22), processing that is performed periodically at 1 ms, for example, processing such as loading the A / D conversion result into the RAM is performed.

Further, in the memory check processing flow shown in FIG. 7, first, in step 30 (S30), it is determined whether or not the memory is in a failed state due to a memory abnormality. If the memory is already in a failed state (FAIL_FLAG = 1), the memory check is performed. Is terminated, but is not in the fail state (FA
IL_FLAG = O) is an address (ADDRESS_) to be checked in the register A in step 31 (S31).
M: the initial value is zero), the final address to be checked in the register B, and the checksum value (CHECK_
SUM: the initial value is zero), and the value Y when the last address is checked is stored in the register D. Next, step 3
2 (S32), the value of the register A, that is, the memory content of the address to be checked is added to the value of the register C and stored in the register C, and the value of the register C is stored in the RAM (CHECK).
K_SUM). Subsequently, step 33 (S3
3) In order to set an address to be checked next, the register A is incremented to A + 1, and the value is stored in the RAM.
(ADDRESS_M). Next, step 3
In 4 (S34), it is determined whether or not the check has been completed up to the final address. If the check has been completed (A = B) up to the final address, the process proceeds to step 36 (S36). If the check has not been completed up to the last address (A ≠ B), the process proceeds to step 35 (S35).
Here, if the timer value (JOB_C) is not 10, the memory check is performed up to the last address.
The process moves to 2 (S32). Also, here (JOB_C) =
Since the case of 10 indicates that 10 ms has elapsed, the memory check is temporarily suspended. Then, as shown in FIG. 2, when the next timer value (JOB_C) ≧ 8 is satisfied and the memory check is performed again, the address and the checksum which have been checked up to the previous time are stored in step 31 (S
31), and the check is restarted.

That is, since a series of processing necessary for the ABS control processing is completed and the timer value (JOB_C) becomes 10, the memory check is performed in a vacant time until 10 ms elapses. Adverse effects are avoided.

Next, in step 34 (S34), if the check has been completed up to the last address, step 36
In step S36, it is determined whether or not the result matches a predetermined value (C = D).
In step 82), the abnormal rotation timer value is cleared, and in step 40 (S40), the memory check is performed again from the top address.
M) and the checksum (CHECK_SUM) are cleared, and the memory check process ends.

If it is determined in step 36 (S36) that the data do not match, the process proceeds to step 37 (S36).
At 37), the number of checks NG is determined, and if it is X times or more, fail-safe processing is performed at step 38 (S38), and then FAI is performed at step 41 (S41).
L_FLAG is set to 1 and the memory check process ends. If it is less than X times in step 37 (S37), the abnormal count timer value (NG_CNT) is incremented by one in step 39 (S39), and step 4 is executed.
0 (S40), a check address (ADDRESS_
M) and the checksum (CHECK_SUM) are cleared, and the memory check process ends.

As described above, in the background job in which the ABS control process is being performed, a series of processes required for the ABS control is completed, and the memory check is performed to the extent that it is possible in the idle time until the calculation cycle elapses 10 ms. Then, the memory check is temporarily interrupted after 10 ms, and the check is resumed from the address temporarily interrupted last time when a series of ABS control processing is completed. It is possible to perform a reliable memory check while avoiding an adverse effect on memory. As a result, the reliability of the ABS control is improved.

In addition, since the memory check can be performed under any conditions of the vehicle (up to fail-safe detection of memory abnormality), the reliability of the ABS control is further improved.

FIG. 8 shows another embodiment of the memory check process. The difference from the flow shown in FIG. 7 is that the checksum (CHECK_CHECK) in step 52 (S52) is used.
SUM) is not the sum of the memory contents from the prior application address to the last address, but the exclusive OR (XO)
R). That is, regardless of whether the sum is an exclusive value or an exclusive OR, when the calculation is performed from the beginning to the end address, each value becomes a specific value. Therefore, it is not always necessary to perform the memory check with the added value.

The other structure is the same as that of FIG. Therefore, the same operation and effect as those of the first embodiment can be obtained.

FIG. 9 shows a third embodiment, which also has the same basic configuration as the flow shown in FIG. 7, but differs from the first address to the last address in steps 71 (S71) and 72 (S72). The difference is that the addition value up to and the exclusive OR are calculated, and if at least one of them does not match, it is determined that the memory is abnormal. That is,
In step 71 (S71), the checksum value 1 is stored in the register C, the checksum value 2 is stored in the register D, and the value Y or Z at the time of checking up to the final address is stored in the registers E and F, respectively. Next, step 7
In 2 (S72), the value A is added to the value of the register C and stored in the register C, or the exclusive OR (XOR) of the value D is stored in the register D. Other configurations are the same as in the first embodiment. Therefore, the same operation and effect can be obtained.

It is to be noted that the present invention provides an ABS
The present invention is not limited to control, and can be applied to other vehicle control devices such as engine control.

[0032]

As is apparent from the above description, according to the memory check mechanism of the vehicle control device according to the present invention, an idle time until a predetermined period elapses after a series of processes required for vehicle control is completed. At time, the memory check is performed to the extent possible, and the memory check is temporarily interrupted when a predetermined period has elapsed, and at the time when a series of vehicle control processing is completed,
Since the check is restarted again from the address temporarily interrupted last time, a reliable memory check can be performed while avoiding adverse effects on other processes and control. As a result, the reliability of vehicle control is improved.

In addition, the memory check is not performed when the engine speed is 4,000 rpm or more, as in the prior art, but the memory check is performed under all conditions of the vehicle, so that the reliability of vehicle control is further improved.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of an ABS control device.

FIG. 2 is a background job flow of an ABS control process.

FIG. 3 is a flowchart of a wheel speed pulse measurement process.

FIG. 4 is a flowchart of a wheel speed pulse measurement process.

FIG. 5 is a flowchart of a wheel speed pulse measurement process.

FIG. 6 is an internal timer interrupt processing flow according to the embodiment;

FIG. 7 is a memory check processing flow.

FIG. 8 is a different example of a memory check processing flow.

FIG. 9 shows still another example of the memory check processing flow.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Control unit 2 ... Microcomputer 3 ... Input interface 4 ... Output interface 5 ... Power supply regulator 6a-6c ... Wheel speed sensor 7 ... Brake switch 9 ... Ignition switch 12 ... ROM 16 ... ABS hydraulic unit

Claims (4)

[Claims] 1. A computer for controlling a vehicle by executing it at predetermined intervals, a memory storing a program for controlling the vehicle, and a storage area of the memory when the computer is running. A memory check mechanism of a vehicle control device comprising: a program abnormality detecting unit that checks the program for each predetermined byte to detect an abnormality. A memory check mechanism of a control device for a vehicle, wherein the program abnormality detecting means is operated during an idle time of a program execution time until a cycle ends. 2. The memory check mechanism according to claim 1, wherein said program abnormality detection means checks the memory check by an added value of memory contents from a start address to an end address. 3. The memory check mechanism according to claim 1, wherein said program abnormality detection means checks the memory by an exclusive OR of memory contents from a first address to a last address. . 4. The apparatus according to claim 1, wherein the program abnormality detecting means checks the memory by at least one of an added value of the memory contents from the first address to the last address and an exclusive OR. Memory check mechanism of the vehicle control device.