JPH1082835A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the throughput of burn-in and reduce the cost by increasing the number of semiconductor devices mountable on a burn-in board. SOLUTION: An integrated circuit formed on a semiconductor chip is provided with an integrated circuit main body 111 having the primary desired function. It is also provided with a clock signal generating circuit and a test pattern signal generating circuit l 12 for generating various control signals and test pattern signals required for the burn-in of a semiconductor device 10, multiple multiplexer circuits 1113, and switch elements 1141, 1142. Since the clock signal generating circuit and the test pattern signal generating circuitng 112 are formed in the integrated circuit, the function required for a burn-in device becomes simple, and the device cost can be reduced. The region and area required to mount the semiconductor devices 10 on a burn-in board are reduced, and the number of the mountable semiconductor devices 10 can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, more particularly, to a test circuit for screening a defect in order to secure reliability after a package is completed. It is used for circuits, memory integrated integrated circuits, and the like.

[0002]

2. Description of the Related Art In a semiconductor device manufacturing process, normally, a non-defective product is selected by a die sort test after a wafer manufacturing process is completed, a defective product is marked, and then a non-defective product is stored in a package to obtain a final product. Finished in form. Then, defective screening is performed on the semiconductor device after completion of the package finished in the form of the final product. The screening of the defect is performed to expose a potential defect of the device and remove the defective device so as not to deteriorate the non-defective device or to make it a defective product in order to secure the reliability of the semiconductor device. As a method of this screening, burn-in, in which voltage stress and temperature stress are accelerated and applied simultaneously at the time of normal use, is often used.

FIG. 5 is a plan view showing a burn-in state of a conventional semiconductor device after a package is completed. In this burn-in state, a plurality of semiconductor devices 60 are mounted horizontally on the burn-in board 50, respectively.

FIG. 6 is a circuit diagram showing a state in which one of the semiconductor devices 60 in FIG. 5 is taken out and electrically connected to a burn-in device 70. 6, a semiconductor device 60 includes an integrated circuit 61 formed on a semiconductor chip, power supply pins 621 and 622 for supplying a power supply potential electrically connected to the integrated circuit 61, and a ground pin for supplying a ground potential. 63
1, 632, and 64 external pins such as 64 signal input pins.
Have ~ 100.

[0005] The burn-in device 70 is provided in the semiconductor device 6.
It has a group of buffer circuits 71 for supplying a clock signal, a test pattern signal, and the like to the group of signal input pins 64 of 0. As shown in FIG. 6, at the time of burn-in of the conventional semiconductor device 60, as in the actual use of the semiconductor device 60,
Burn-in board 50 for all external pins of semiconductor device 60 (except for vacant pins, if any).
It is connected to the burn-in device 70 via the upper wiring (not shown).

However, as the package size of the semiconductor device 60 increases and the number of external pins increases, the physical area necessary for mounting one semiconductor device 60 on the burn-in board 50 and wiring to each external pin are performed. The wiring area required for this increases. In other words, the number of semiconductor devices 60 that can be mounted on the burn-in board 50 decreases, the burn-in throughput decreases, and the cost increases.

Further, the semiconductor device 60 is used for burn-in.
The number of signal input pins that need to input signals to
The performance required for the test pattern signal generation circuit and the like in the burn-in device 70 becomes more complicated, and the cost of the burn-in device 70 increases.

[0008]

As described above, in the conventional semiconductor device, at the time of burn-in after the package is completed, the number of semiconductor devices that can be mounted on the burn-in board decreases, the burn-in throughput decreases, and the cost increases. However, the performance required for the test pattern signal generation circuit and the like in the burn-in device becomes more complicated, and there is a problem that the cost of the burn-in device increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. At the time of burn-in after package completion, the number of semiconductor devices that can be mounted on a burn-in board is increased, thereby improving the burn-in throughput and reducing the cost. It is an object of the present invention to provide a semiconductor device that can reduce the cost, simplify the performance required for the burn-in device, and reduce the cost of the burn-in device.

[0010]

According to the present invention, there is provided a semiconductor device comprising:
An integrated circuit formed on a semiconductor chip and including a clock signal generation circuit / test pattern signal generation circuit for generating various control signals / test pattern signals required for burn-in of the semiconductor device, and a package encapsulating the semiconductor chip A power supply terminal for supplying a power supply potential and a ground terminal for supplying a ground potential, which are electrically connected to the integrated circuit and led out of the package, respectively, and are electrically connected to the integrated circuit, respectively. A plurality of signal input terminals led out of the package and a clock signal generation circuit / test pattern signal generation circuit of the integrated circuit, and led out of the package, and in a burn-in mode / normal Clock signal generation circuit and test pattern signal generation according to use mode Characterized by comprising a mode switching input terminal to which the potential for controlling whether the operation of the road is applied.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram showing an example of a configuration of a semiconductor device according to a first embodiment of the present invention and an electrical connection state with the outside at the time of burn-in.

FIG. 2 is a circuit diagram showing an example of an electrical connection state with the outside when the semiconductor device of FIG. 1 is normally used. In FIG. 1, a semiconductor device 10 includes an integrated circuit formed on a semiconductor chip, a rectangular resin package 11 which seals the semiconductor chip, and a package electrically connected to the integrated circuit, respectively. 90 to 100 external terminals (external pins) led out.

In the present invention, the external pins include a power supply pin 121 for supplying a normal power supply potential, a ground pin 131 for supplying a ground potential, and a plurality of signal inputs as an external pin group used during normal use of the semiconductor device 10. Pin 14 (on /
A mode switching input pin 15 for designating switching between a normal use mode and a burn-in mode of the semiconductor device; and a semiconductor device 10.
The external pin group used during both burn-in and normal use includes a power supply pin 122 and a ground pin 132 which are used to supply a burn-in power supply potential during burn-in and a normal power supply potential during normal use.

The integrated circuit formed on the semiconductor chip is used to generate various control signals and test pattern signals required for burn-in of the semiconductor device 10 in addition to the integrated circuit main body 111 having the originally desired function. A clock signal generation circuit / test pattern signal generation circuit 112 (corresponding to at least a part of a clock signal generation circuit and a test pattern signal generation circuit provided in a conventional burn-in device), a plurality of multiplexer circuits 113, and a plurality of switches Including elements 1141 and 1142.

Next, the circuit configuration of the integrated circuit will be described. The integrated circuit including the integrated circuit main body 111 and the clock signal generation circuit / test pattern signal generation circuit 112 is connected to the first power supply pin 121 for supply of a normal power supply potential, has a sufficiently wide gate width, and has a current supply capability. It is connected to a second power supply pin 122 for supplying a burn-in power supply potential via a high first switch element 1141.

The integrated circuit is connected to a first ground pin 131 for supplying a ground potential and is connected to a second ground pin 132 for supplying a ground potential via a second switch element 1142. ing.

Each output of the plurality of two-input multiplexer circuits 113 is connected to the integrated circuit body 111. One input of each of the plurality of two-input multiplexer circuits 113 is connected to a plurality of signal input pins 14 respectively. The plurality of two-input multiplexer circuits 11
The other outputs of the clock signal generation circuit / test pattern signal generation circuit 112 are connected to the other input of each of the three.

The clock signal generation circuit / test pattern signal generation circuit 112 is connected to the mode switching input pin 15 and the mode switching input pin 1
The normal use mode / burn-in mode of the semiconductor device is designated according to the applied potential of No. 5.

In this embodiment, of the external pins, the external pins (burn-in power supply pin 122, burn-in ground pin 13) used for burn-in are used.
2. Mode switching input pins 15) are gathered on one side of the rectangular resin package 11.

Thus, at the time of burn-in, a required power supply potential and a mode switching input potential can be applied to the semiconductor device 10 via the external pins 122, 132, and 15 on one side.

FIGS. 3 and 4 are a plan view and a side view showing a burn-in state of the semiconductor device 10 in which external pins used for burn-in are collected on one side as described above. In this burn-in state, a plurality of semiconductor devices 10 are mounted vertically on the burn-in board 30 respectively.

At the time of burn-in of the semiconductor device 10 having the above-described structure, as shown in FIGS. 3 and 4, the semiconductor device 10 is mounted on the burn-in board 30 in a vertical state. A required potential and a signal are applied to the semiconductor device 10 via a wiring (not shown).

Then, as shown in FIG. 1, a burn-in power supply potential is supplied to the second power supply pin 122,
The ground potential is supplied to the ground pin 132 of
A burn-in mode designation potential (for example, a burn-in power supply potential) is supplied to the mode switching input pin 15 as a mode switching input. At this time, the operation of the clock signal generation circuit / test pattern signal generation circuit 112 becomes possible, and various control signals / test pattern signals required for burn-in are generated.

Thus, the first switch element 1141
And the second switch element 1142 are turned on, and the burn-in power supply potential of the second power supply pin 122 is applied to the integrated circuit main body 11 via the first switch element 1141.
1 and the ground potential of the second ground pin 132 is applied to the integrated circuit body 1 via the second switch element 1142.
The test pattern signal is applied to the integrated circuit main body 111 via a plurality of two-input multiplexer circuits 113.

On the other hand, during normal use of the semiconductor device 10, with the semiconductor device 10 mounted on a circuit board of a system product, as shown in FIG. And a required signal to the semiconductor device 10 via the buffer circuit 16 group.

That is, the normal power supply potential is supplied to the first power supply pin 121, the ground potential is supplied to the first ground pin 131, and the normal power supply potential is supplied to the second power supply pin 122. The potential is supplied to the second ground pin 13
2 is supplied with a ground potential, and a mode switching input pin 15 is supplied with a burn-in mode designating potential (for example, a ground potential) as a mode switching input. At this time, the operation of the clock signal generation circuit / test pattern signal generation circuit 112 becomes impossible, and various control signals / test pattern signals required for burn-in are not generated.

Thus, the first switch element 1141
And the second switch element 1142 are turned off, and the normal power supply potential of the first power supply pin 121 is applied to the integrated circuit main body 111, and the first ground pin 131 is turned off.
Is applied to the integrated circuit main body 111, and a required signal input from the outside via the group of buffer circuits 16 is input to the integrated circuit main body 111 via the plurality of two-input multiplexer circuits 113.

According to the semiconductor device 10 as described above,
A clock signal generation circuit / test pattern signal generation circuit 112 required for burn-in (corresponding to at least a part of the clock signal generation circuit and the test pattern signal generation circuit provided in the conventional burn-in device) is formed inside the integrated circuit. Therefore, the performance required for the burn-in device is simplified, and the cost of the burn-in device is reduced.

Of the external pins of the semiconductor device, the external pins used for burn-in (power-in pin 121 for burn-in, ground pin 131 for burn-in,
The mode switching input pins 15) are collected on one side of the rectangular resin package 11. Thus, at the time of burn-in of the semiconductor device 10, it is possible to supply a required potential and a signal to the semiconductor device 10 via the external pins 121, 131, and 15 on one side.

In other words, as shown in FIGS. 3 and 4, a plurality of semiconductor devices 10 can be mounted vertically to the burn-in board 30, so that the package size of the semiconductor device 10 will be increased in the future. Even if the number of external pins increases, the physical area required for mounting the semiconductor device 10 on the burn-in board 30 and the wiring area required for wiring to each external pin decrease, and the burn-in board 30 The number of semiconductor devices 10 that can be mounted is increased, the burn-in throughput is improved, and the cost of burn-in can be reduced.

[0031]

As described above, according to the semiconductor device of the present invention, at the time of burn-in after package completion, the number of semiconductor devices that can be mounted on a burn-in board is increased, thereby improving the burn-in throughput and reducing the cost of burn-in. Can be reduced, the performance required for the burn-in device can be simplified, and the cost of the burn-in device can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a configuration of a semiconductor device according to a first embodiment of the present invention and an electrical connection state with the outside during burn-in.

FIG. 2 is a circuit diagram showing an example of an electrical connection state with the outside during normal use of the semiconductor device of FIG. 1;

FIG. 3 is a plan view showing an example of a burn-in state when external pins used for burn-in of the semiconductor device of FIG. 1 are collected on one side;

FIG. 4 is a side view corresponding to FIG. 3;

FIG. 5 is a plan view showing a conventional burn-in state of a semiconductor device after completion of a package.

FIG. 6 is a circuit diagram showing a state in which one of the semiconductor devices in FIG. 5 is taken out and electrically connected to a burn-in device.

[Explanation of symbols]

Reference Signs List 10: semiconductor device, 11: resin package, 111: integrated circuit body, 112: clock signal generation circuit / test pattern signal generation circuit, 113: multiplexer circuit, 1141: first switch element, 1142: second switch element 121: a power pin for supplying a normal power potential; 131: a ground pin for supplying a ground potential; 122: a power pin for supplying a burn-in power potential; 132: a ground pin; 14: a signal input pin; 15: a mode switching input pin; 30 ... Burn-in board.

Claims (4)

[Claims] An integrated circuit formed on a semiconductor chip and including a clock signal generation circuit and a test pattern signal generation circuit for generating various control signals and test pattern signals required for burn-in of a semiconductor device; and the semiconductor chip. And a power supply terminal for supplying a power supply potential and a ground terminal for supplying a ground potential, which are electrically connected to the integrated circuit and led out of the package, respectively. A plurality of signal input terminals that are electrically connected and led out of the package, and are electrically connected to a clock signal generation circuit / test pattern signal generation circuit of the integrated circuit and led out of the package. Clock signal generation circuit and test according to burn-in mode / normal use mode Wherein a potential for controlling whether the operation of the turn signal generation circuit comprises a mode switching input terminal applied. 2. The semiconductor device according to claim 1, wherein the package has a rectangular shape, and among the external terminals, external terminals used for burn-in are gathered on one side of the rectangular package. Semiconductor device characterized by the above-mentioned. 3. The semiconductor device according to claim 1, wherein the external terminals used for the burn-in are a burn-in power supply terminal, a burn-in ground terminal, and a mode switching input terminal. apparatus. 4. The semiconductor device according to claim 1, wherein said plurality of signal input pins are connected corresponding to each one input node, and said clock signal is connected to each other input node. A plurality of two-input multiplexer circuits each connected to an output of a generation circuit / test pattern signal generation circuit and each output node connected to a plurality of signal input nodes of the integrated circuit; and the clock signal generation circuit / test pattern signal generation. A first switch element and a second switch element that are turned on by a control signal output during operation of the circuit, wherein the power terminal has a first power terminal for supplying a normal power potential and a burn-in. A second power supply terminal for supplying a power supply potential, wherein the ground terminal includes a first ground terminal to which a ground potential is supplied during normal use; A second ground terminal to which a ground potential is supplied at the time of burn-in; a power supply node of the integrated circuit connected to the first power supply terminal and the second power supply node connected to the second power supply terminal via the first switch element; And a ground node of the integrated circuit is connected to the first ground terminal and to the second ground terminal via the second switch element. A semiconductor device, comprising: