JPH1079739A - Control system for rate conversion buffer for atm cell - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a capacity of a buffer memory, to decrease a cell delay and to conduct quickly a restoration processing in the case that synchronization is disturbed by reducing a residence of cell in a buffer memory in a rate conversion buffer control system of a subscriber interface section of an ATM asynchronous transfer mode exchange. SOLUTION: A rate conversion buffer of a subscriber interface section of an ATM exchange is provided with a timing discrimination means 11 discriminating a phase relation of read request signals from a common section in duplicate and a timing decision means 12 to decide a read timing according to a discrimination result signal from the timing discrimination means 11. Then an ATM cell is read out of buffer memories of an active system and a standby system depending on the timing decided by the timing decision means 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control system for controlling a speed conversion buffer of a subscriber interface unit of an ATM exchange.

ATM (Asynchronous Transfer Mode) communication is a high-speed communication technology that can provide multimedia communication such as image communication, high-speed data communication, and voice signal communication.

In this ATM communication, information to be communicated is divided into fixed-length data of 48 bytes, and is transferred as fixed-length data called a cell having destination information (referred to as a header) of 5 bytes added to the beginning. I do. And A
In the TM communication device, the destination of the cell is determined from the information in the header of each cell, and communication is performed by transmitting the cell to a specified line or terminal.

In such ATM communication, the data amount and data rate transmitted from the ATM terminal are not constant but fluctuate with time. In order to send such data that fluctuates with time to the common unit at a specified speed, the data is written into an ATM cell, then temporarily stored in a buffer memory for speed conversion, and read out using a read clock from the common unit. Conversion is being performed.

[0005] In such an ATM switch for performing the ATM communication, it is required to reduce the capacity of the buffer memory of the buffer memory for speed conversion of the ATM cells and to reduce the cell delay in the ATM switch.

[0006]

2. Description of the Related Art FIG. 6 is a diagram for explaining a conventional example (1). 20U-0, 20U-1, 20D-0, 20 in the figure
D-1, 20L-0, and 20L-1 are buffer memories (shown as buffers in the figure) for storing cells, 21 is a header conversion unit, 22, 22, 0 and 22-1 are selectors, 23-0,
23-1 is a filter. “0” of XX-0 / 1 indicates “system 0” of a device having a duplex configuration, and “1” indicates “system 1” of a device having a duplex configuration.
Is “UP”, that is, the up direction, and “D” is “DOW”.
N ”, that is, in the down direction,“ L ”is“ LOOPBA
CK ", that is, a return.

In this configuration, as the upstream cell flow, the input cell Ci from the subscriber side is input to the header conversion unit 21, in which the header is compared with the data of a conversion register (not shown) to perform pattern matching. Is obtained, the content of the header is replaced with the value of the conversion register, and then stored in the buffer memories 20U-0 and 20U-1. Then, they are read as output cells Co0 and Co1 by a read clock signal from a common unit for multiplexing / demultiplexing cells (not shown).

Next, as the downstream cell flow, the cells Ci0 and Ci1 from the common section pass through the filters 23-0 and 23-1, and then, out of the buffer memories 20D-0 and 20D-1,
The common unit is stored in a buffer memory corresponding to the active system (hereinafter, the active system is referred to as an ACT system, and the standby system is referred to as an SBY system) at that time. Buffer memory 20D-
The cells stored in 0, 20D-1 are read by the read clock signal and output as Co. At this time, the selector 22 outputs the buffer memory 20D-0, 20D
-1, the cell in which cells are stored is selected.

Further, when the specific cell is folded, the headers are collated by the filters 23-0 and 23-1, and the cell having the matched header is stored in the folding buffer memory 20L.
-0, stored in 20L-1. Selectors 22-0, 22
-1 indicates that if a folded cell is stored in the buffer memories 20L-0 and 20L-1, regardless of the state of the buffer memories 20U-0 and 20U-1, that cell is preferentially selected and output as the output cell Co. Output.

FIG. 7 shows a time chart of the conventional example (1). As described with reference to FIG. 6, the speed conversion buffer adopts a duplex configuration, and it is necessary that the systems be synchronized with each other, and each system operates according to the time chart in the figure. Hereinafter, the operation will be described with reference to a time chart.

Ci: Indicates an input cell, Write (not shown)
The Octet Pointer is written to the buffer memory while incrementing. 1 to 4 in the figure indicate that four cells have been continuously input. The actual operation is not limited to four cells, and the same operation is repeated even when five or more cells are continuously input.

Wpo: indicates a write cell pointer, and is updated to the next address every time writing of one cell is completed. Rrq0: Indicates a read request pulse 0 from the ACT system (here, the system is 0).

Jrd; whether or not reading is possible (empty or not empt
y) is the timing to perform Judge Read, and Rrq0
After half a cell. In the figure, in the first judgment, since the writing of the cell 1 has not been completed, no cell exists in the buffer memory (empty state), and the cell cannot be read. In the next judgment, the writing of the cell 1 is performed. Has been completed
(not empty state), so that reading becomes possible.

Rpo0, Rpo1; Read Cell Pointers 0, 1
In the case where there is a reading instruction when Rrq0 and Rrq1 are input, reading is performed from the buffer memory while incrementing a read octet pointer (not shown).

Rpo0, Rpo1; read cell pointers, each time reading of one cell is completed, updating to the next address. As described above, since the phase difference between the two systems is within ± 0.5 cells, the buffer accumulation amount is determined at the cell middle point of the ACT system.
Cell synchronization is performed by starting reading at the beginning of the next read request pulse.

FIG. 8 shows a flow chart of the conventional synchronous recovery. As described with reference to FIG. 7, cell synchronization between systems is as follows.
The same cell is output within 1/2 cell, but for some reason, both systems' write cell pointer or read cell
If the Pointer shifts and cell synchronization is lost, it is necessary to automatically restore cell synchronization. Hereinafter, the operation will be described according to the steps of the flowchart.

S1: It is determined whether or not the buffer memory is empty. S2: Determine whether there is a read instruction. S3: If there is a reading instruction in S2, reading is performed.

S4: Next, the mismatch flag is set to "0". S5: If there is no reading instruction in S2, it is determined whether the mismatch flag is “0” or “1”.

S6: If the mismatch flag is "0" in S5, the mismatch flag is set to "1". in this case,
No reading is performed. S7: If the mismatch flag is “1” in S5, Read Cell
Update Pointer. The cell is discarded.

S8: If the buffer memory is empty in S1, the mismatch flag is set to "0". With such processing, reading is performed from the shifted state, and when either buffer memory becomes empty, the synchronization recovery processing (when there is a read request pulse Read Request Pulse, the read instruction is continuously performed twice) In the case of "no instruction", a blank reading is performed.).

FIG. 9 is a diagram for explaining the conventional example (2).
The figure shows the details of the configuration related to the downstream cell flow in the conventional example (1) described with reference to FIG. In the figure, the buffer memories 20D-0 and 20D-1 and the selector 22 are the same as those described with reference to FIG.
e Cell Pointer (shown as light pointer in the figure), 25-
Reference numerals 0 and 25-1 indicate a read cell pointer (indicated as a read pointer in the figure), and 26 indicates a read determination unit.

The COMACT shown in FIG.
The signal is a signal from the control unit that determines whether or not the cell is the T system. The input cell is written into one of the ACT buffer memories 20D-0 and 20D-1 by COMACT.
Read Cell Pointers 25-0 and 25-1 operate on the SBY side with priority based on the determination result of the read determination unit 26, and output as output cells Co via the selector 22. (AC
When switching from the T system to the SBY system, all cells are read and stopped in an empty state. FIG. 10 shows a time chart of the conventional example (2).

Ci0, Ci1: Indicates an input cell. ACT-CONT: a switching signal for instructing the system to operate as the ACT system. Here, at first, the system 0 operates as the ACT system, and the ACT-C is activated during the input of the input cell 2-0.
This is an example in which the ONT signal is switched from system 0 to system 1.

Wpo0, Wpo1; Since cells are written only to the ACT system, cells 1 and 2 are written to the 0 system, and cells 3 to 5 are written to the 1 system. Rti: indicates a read timing signal.

Co: Indicates an output cell, cells 1 and 2 are output from the 0 system, and cells 3 and thereafter are output from the 1 system.

[0026]

As described in the above prior art example (1), ATM cells are written and read in a duplicated system.
The phase relationship between Pulses is unchanged during operation, but it is not known which system is faster. Also, by updating the Write Cell Pointer after cell writing is completed,
Reading becomes possible after writing of the cell is completely completed. Therefore, the storage amount of the buffer memory is determined at the midpoint of the ACT system cell timing. However, as shown in the time chart of FIG. As 4
It is necessary for the cell.

As described with reference to FIG. 8, the Write Cell Pointers 24-0, 24-
1. If the Read Cell Pointers 25-0 and 25-1 no longer match, recovery cannot be performed until one of them becomes empty several times. If the line is almost saturated, it takes a long time to recover. It costs.

Further, as shown in FIG. 10, due to the timing relationship between the SBY system and the ACT system, the state in which one cell is being written into the buffer memory for storing the downstream cells, one cell is staying, and one cell is being read is changed. The resulting capacity of three cells is required.

In the case of the return of a specific cell, since the reading is performed without synchronizing the two systems, the synchronization of the return cell may be disturbed. The present invention provides an ATM cell which can reduce the capacity of the buffer memory by shortening the stay in the buffer memory, reduce the cell delay, and quickly perform the recovery process when the synchronization is disturbed. Attempts to implement a control method for the speed conversion buffer memory.

[0030]

FIG. 1 is a diagram for explaining the principle of the present invention. In the figure, reference numeral 100 denotes a speed converter of a subscriber interface unit of the ATM exchange, and an ATM (not shown).
It performs speed conversion when transmitting ATM cells from the terminal to the common units 200 and 201.

In the present invention, the duplicated common part 2
Timing determination means for determining the phase relationship between the read request signals Rrq0 and Rrq1, and timing determination means for determining the read timing in accordance with the determination result signal from the timing determination means. 11, the buffer memories 20-0, 20-
By reading the ATM cell from 1, it is possible to reduce the time from the determination to the start of reading, and to reduce the capacity of the buffer memory.

[0032]

FIG. 2 shows an embodiment (1) of the present invention.
FIG. Reference numeral 100 in the figure denotes a speed converter of the subscriber interface unit of the ATM exchange. 200, 2
01 is a duplicated common part, 20U-0, 21U
-1 is a duplicated buffer memory.

Reference numeral 11A denotes a phase comparator as the timing judging means 11 described in the principle diagram. The timing determining means 12 reads the read request signals Read Request Pulse 0, 1 (Rrq0, Rrq1 in the figure) from the common units 200, 201. ), And a read signal generator 12A that determines the read timing from the output of the phase comparator 11A and the selector 12B.

FIG. 3 shows a time chart of the embodiment (1) of the present invention. (A) The case where the timing of the ACT read request pulse is early is shown. Ci: Indicates an input cell.

RrqA: Indicates Read Request Pulse ACT. RrqS: Read Request Indicates Pulse SYB, Read Request
Timing is behind Pulse ACT.

Srd: a read signal indicating the read timing. If the timing of the Read Request Pulse ACT is earlier, it is determined at the rising edge of the Read Request Pulse ACT whether or not the read operation is possible.
Read Request Pulse Reads the cell at the rising edge of SYB.

CoA; ACT buffer memory 20U-
This is a cell read from 0. CoS: a cell read from the SBY buffer memory 20U-1. (B) Shows the case where the timing of the SBY system Read Request Pulse is early.

Ci: Indicates an input cell. RrqA: Indicates Read Request Pulse ACT. RrqS: Read Request Indicates Pulse SYB, Read Request
Timing is earlier than Pulse ACT.

Srd: a read signal indicating the read timing. If the timing of the Read Request Pulse SYB is earlier, the judgment is made at the falling edge of the Read Request Pulse ACT, and the Read Request Pulse ACT, Read Request P
ulse Read cell at rising edge of SYB.

CoA; ACT buffer memory 20U-
This is a cell read from 0. CoS: a cell read from the SBY buffer memory 20U-1. With this process, if the ACT read request pulse is early, the ACT cell is output immediately after the determination,
BY cells are output within 1/2 cell time. Also,
When the SBY read request pulse is early, the SBY cell is output immediately after the determination, and the ACT cell is 1 / cell.
Output within 2 cell times. With such a configuration, the buffer memory stays for two cells for a time, and the required capacity of the buffer memory is three cells, and the capacity of the buffer memory can be reduced.

FIG. 4 is a diagram for explaining the embodiment (2) of the present invention. Flame indicating the cell timing
Enable Pulse (indicated by Fe in the figure) is added and input simultaneously. The counter 13 counts up the cell number each time the Flame Enable Pulse is input, and stores the cell number in the buffer memories 20U-0 and 20U-1 together with the input cells. When reading the stored cells, the cell numbers of both systems are compared by the number comparator 14. If they match, the cells are valid. If they do not match, the read cell pointer 1 is used.
Until the count values of 5-0 and 15-1 match, stop updating the Read Cell Pointer with the larger count value,
Perform synchronization recovery.

With this operation, even if the cell numbers of the two systems do not match, synchronization can be quickly restored. FIG. 5 is a diagram illustrating an embodiment (3) of the present invention.

The figure shows an embodiment for controlling cells in the downlink direction. The phase of the Flame Enable Pulses Fe0 and Fe1 is compared by the phase comparator 16 to determine which phase is earlier, and the result is notified to a switch (shown as SW in the figure) 17. The switch 17 connects the earlier system to a path that passes through the buffer memory 20D for 1/2 cell, and connects the latter system to a path that passes through the slower system. The selector 22 selects the output cells Co0 and Co1.

The phase difference between the ACT system and the SBY system is at most 1/2.
Since the cell is a cell, the capacity of the buffer memory 20D is １ ／.
A cell is sufficient. Also, since the phase difference between the ACT system and the SBY system takes a value of 0 to ０ cell, in order to absorb this phase difference, 0 is set based on the cell timing of the slower system.
〜 Cell delay is performed.

The stack monitors 19-0 and 19-1 monitor the stacks of the Flame Enable Pulses Fe0 and Fe1 and notify the phase comparator 16 of the monitoring result. If a stack occurs in a system that does not pass through the 1/2 cell buffer memory 20D, the normal system is returned to the buffer memory when empty information is received from the Read Cell Pointer (indicated by an R pointer in the figure) 18. In addition to switching to a system that does not pass through 20D, the selector 22 is instructed to forcibly select a normal system.

Further, in the return of a specific cell,
The ACT side return buffer memory 20L-A is selected by the ACT side read request signal Read Request Pulse1, and its state is detected to generate a read instruction signal.
This is notified to Read Cell Pointers 0 and 1 of both systems,
By reading cells from the buffer memories 20L-0 and 20L-1, cell synchronization is ensured.

[0047]

According to the present invention, by reducing the time from the read determination to the start of the read, the capacity of the buffer memory can be reduced, and the cell delay in the ATM exchange can be reduced.

Further, when the pointer is shifted and cell synchronization cannot be achieved, synchronization can be quickly restored regardless of the cell flow rate. Further, in the return of the specific cell, it is possible to prevent the cell synchronization from being disturbed by inserting the cell synchronously.

[Brief description of the drawings]

FIG. 1 illustrates the principle of the present invention.

FIG. 2 illustrates an embodiment (1) of the present invention.

FIG. 3 is a time chart according to the embodiment (1) of the present invention.

FIG. 4 is a diagram illustrating an embodiment (2) of the present invention.

FIG. 5 is a diagram illustrating an embodiment (3) of the present invention.

FIG. 6 is a diagram illustrating a conventional example (1).

FIG. 7 is a time chart of a conventional example (1).

FIG. 8 is a flowchart of synchronization recovery in a conventional example.

FIG. 9 is a diagram illustrating a conventional example (2).

FIG. 10 is a time chart of a conventional example (2).

[Explanation of symbols]

100 Speed converter 20-0, 20-1, 20U-0, 20U-1, 20
D, 20D-0, 20D-1, 20L-0, 20L-1
Buffer memory 11 Timing determination means 11A, 16 Phase comparator 12 Timing determination means 12A Readout signal generator 12B Selector 13 Counter 14 Number comparator 15-0, 15-1, 18, 25-0, 25-1 Read
Cell Pointer 17 Switch 19-0, 19-1 Stack monitor 21 Header converter 22, 22-0, 22-1 Selector 23-0, 23-1 Filter 24-0, 24-1 Write Cell Pointer 26 Read determination unit 200, 201 common part

Claims (6)

[Claims] In a rate conversion buffer of a subscriber interface section of an ATM exchange, timing determining means for determining a phase relationship of a read request signal from a duplicated common section, and a determination result signal from the timing determining means. And timing determining means for determining the read timing, wherein the timing determined by the timing determining means
A method of controlling an ATM cell speed conversion buffer, wherein ATM cells are read from working and standby buffer memories. 2. The control method of an ATM cell speed conversion buffer according to claim 1, wherein said timing determination means is constituted by a phase comparator for comparing the phase of a read request signal from a duplexed common unit, The timing determining means includes a selector for selecting an earlier phase of the read request signal from the duplicated common unit, an output of the phase comparator, and an output of the selector as inputs to the ATM buffer from the active and standby buffer memories. A rate conversion buffer control method for an ATM cell, comprising a read signal generation unit for generating a timing signal for reading a cell. 3. The control method of an ATM cell speed conversion buffer according to claim 1, further comprising a counter for adding an additional number to an input cell, wherein said counter is used when writing an input cell to a duplicated buffer memory. When writing and reading the counted serial number together with the input cells, when reading, compare the serial numbers of the output cells from both systems, and if they do not match, stop until the system with the larger count matches. Characteristic ATM cell rate conversion buffer control method. 4. The ATM cell rate conversion buffer control method according to claim 1, wherein a half-cell buffer memory for temporarily storing downstream input cells, and a phase relationship between a duplicated input system. And a phase comparator that outputs a system with a slower phase through, and outputs a system with an earlier phase via the buffer memory for the セ ル cell based on the comparison result of the phase comparator. The control method of the ATM cell speed conversion buffer. 5. The control method of an ATM cell speed conversion buffer according to claim 4, further comprising: a stack monitoring unit for detecting a stack of a cell timing signal of a duplex system, wherein the stack monitoring unit stacks the cell timing signal. Is detected, the normal system is switched to a route that does not pass through a buffer memory for 1/2 cell.
Control method of TM cell speed conversion buffer. 6. The control method of an ATM cell speed conversion buffer according to claim 1, further comprising a readability determining unit for determining a storage state of a specific cell, wherein a readability determination result by said readability determination unit of an active system is reserved. A control method of an ATM cell speed conversion buffer, characterized in that a system is notified and a specific cell is looped back in synchronization.