JPH1078828A - Frequency multistage change controller for clock and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the unwanted power consumption to the utmost, and to attain an operation without deteriorating the capability of a CPU. SOLUTION: A clock is supplied through a supply clock controlling part 3 to a CPU 1. The end of a CPU processing is communicated through an interruption monitoring part 2 to the supply clock controlling part 3 by using an interrupting port. On the other hand, interruption from the outside such as a keyboard 4 or each kind of control signal transmitting part 5 is communicated through the interruption monitoring part 2 to the CPU 1. The interruption monitoring part 2 communicates the classification of the interruption from the outside to the supply clock part 3. The supply clock controlling part 3 calculates a dividing ratio by referring to the information of the number of the ends of the processing or the number of the counts of outside clocks. Therefore, the supply clock can be dynamically switched according to static information for designating an operating frequency. Thus, the capability of the CPU can be used as best as possible, and also power consumption can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock frequency multi-stage change control device and a frequency multi-stage change control method.

[0002]

2. Description of the Related Art A conventional controller for controlling a clock supplied to a central processing unit (hereinafter, referred to as a CPU) is operated by a supply clock having a statically determined one frequency, or
In order to select a plurality of types of static supply clocks, selection has been made by human intervention in hardware such as a jumper switch, software control, or selection of a static supply clock by hardware control.

In this method, since there is no relation between the clock supply unit to the CPU and each external interrupt signal, the CPU operates within an allowable range of the apparatus in response to an external interrupt signal that enters irregularly. It is necessary to operate the interrupt processing unit within a certain time so that
The supply clock of U cannot be reduced below a certain level.
As a result, unnecessary power consumption has occurred.

A clock control device of this type includes a device described in Japanese Patent Application Laid-Open No. 7-334267. In this device, the condition for changing the operating frequency, the designation information of the module for changing the operating frequency, and the designation information of the operating frequency to be changed are stored in the storage means in advance, and the state of the logic LSI sequentially input and the state of the storage means A condition for changing the operating frequency is compared, and when the comparison result matches, the corresponding operating frequency is changed. In these devices, before the CPU operates, it is necessary to hold the supply clock frequency or the reference value for generating the supply clock frequency for the CPU to operate.

[0005]

In any of the conventional control devices, it is necessary to provide a static supply clock frequency with some means or information before the CPU operates in order for the CPU to operate. Therefore, in this type of control device, when executing a process in which the processing amount of the CPU is indeterminate within a unit time, the operation clock of the CPU must be set in consideration of the processing amount when the CPU processing amount is large. No. As a result, if the processing amount is small as a result, the CP
There is a problem that U performs useless operation. Also, preparing various operation clocks in consideration of a change in CPU processing has a problem in that, for example, the area of a board is reduced when hardware is used, and the storage area is reduced when software is used.

An object of the present invention is to suppress unnecessary power consumption and make the most of the capacity of the CPU to make the CP within a certain time.
An object of the present invention is to provide a clock multi-stage change control device and a multi-stage change control method for terminating the operation of U.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a multi-stage clock change control apparatus and a multi-stage change control method according to the present invention provide a means for dynamically changing a clock supplied to a CPU. Is newly added.

That is, the present invention adds monitoring means for monitoring an interrupt signal, clock control means for controlling a supply clock, and a processing end notification function for notifying the interrupt monitoring means of the end of software processing. Monitoring means for receiving a processing end signal, receiving an external interrupt signal,
There is provided notification means for notifying the CPU and instruction means for instructing the supply clock control mechanism of the type of the external interrupt signal notified to the CPU.

The clock control means includes an input means for externally inputting a clock frequency that is a multiple of the upper limit of the CPU-supplied clock, and C as an initial value of a division ratio (ratio).
Storage means for holding a frequency division ratio approximating the allowable maximum clock frequency of the PU, arithmetic means for calculating the frequency division ratio of the clock, and initialization of the frequency division ratio according to the type of the notified interrupt signal Initialization means.

According to the present invention described above, control for automatically changing the supply clock of the CPU in multiple stages can be performed in accordance with the amount of calculation processing, and the processing amount of the CPU changes at certain time intervals. It is used when the supply clock of the computer device used for the real-time processing that continues to operate for a long time is changed in multiple stages.

Therefore, by using the present invention, the supply clock can be dynamically switched in accordance with the calculation processing amount of the CPU without the need for static information or means for designating the operating frequency. Therefore, the capacity of the CPU can be maximized and the power consumption can be reduced.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A clock frequency multi-step change control device and a frequency multi-step change control method according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a clock frequency multi-stage change control device according to an embodiment of the present invention.
In FIG. 1, the interrupt boat of the CPU 1 is connected to an external device or circuit via an interrupt monitor 2. The interrupt monitoring of the interrupt monitor 2 is performed by operating a key corresponding to the interrupt monitoring process from the keyboard 4. Further, the control signal from the various control signal transmitting unit 5 is transmitted to the interrupt monitoring unit 2. The supply of the clock signal to the CPU 1 is supplied via the supply clock control mechanism 3.

FIG. 2 is an example of a flowchart showing a multi-stage clock change control device according to an embodiment of the present invention. The following processing is determined or executed by the program unit stored in the storage area inside the CPU 1 in FIG.
In FIG. 2, in step 210 (hereinafter, abbreviated as S210), it is determined whether or not there is a process due to an external or internal factor.

If these factors are present (YES in S210), the process proceeds to S220, in which control for automatically changing the supply clock of the CPU 1 in multiple steps according to the amount of calculation is performed. The CPU 1 executes a process of changing the supply clock of the computer device used for the real-time process in which the amount of processing of the CPU 1 changes and continues to operate for a long time. If there is no external or internal factor (NO in S210), the process proceeds to S230, and a processing end notification is made. The above processing is repeatedly performed.

In this embodiment, the processing end notification is a signal indicating the end of the clock multi-stage change processing, and the supply clock control shown in FIG. 1 is performed via the interrupt monitor 2 using the interrupt port in FIG. Notify part 3. After the notification, the clock multi-stage change process is performed again.

On the other hand, external interrupts such as the keyboard 4 and various control signals 5 in FIG. 1 are notified to the CPU 1 via the interrupt monitoring unit 2. At this time, the interrupt monitoring unit 2 notifies the supply clock control unit 3 of the type of interrupt from outside.

FIG. 3 is a block diagram for explaining a detailed configuration of the supply clock control unit 3 in FIG. In FIG. 3, an external clock 8 is frequency-divided by a clock frequency dividing circuit 9 to supply a frequency-divided clock signal to the CPU 1. The dividing ratio used by the clock dividing circuit depends on the calculation result of the dividing ratio calculator 14. On the other hand, an external clock is also sent to the frequency division ratio calculation unit 14.

The frequency dividing ratio calculator 14 has an arithmetic circuit 12 and several registers 13 therein. The clock signal supplied from the outside is added in the arithmetic circuit 12 and held in the register 13. Further, the interrupt signal 11 notified from the interrupt monitor 2 is also added by the arithmetic circuit 12 and held in the register 13. In addition, the register 13 holds information such as an initial setting value of the frequency division ratio and the number of process terminations.

When the count number of the external clock 8 held in the register 13 reaches a constant value, the supply clock control unit 3 refers to the number of notification of the number of processing completions, and allows the CPU 1 to perform processing within the next constant time. The frequency dividing ratio approximate to the minimum clock is obtained from the count number of the external clock notified within the same time immediately before, and is notified to the clock frequency dividing circuit 9. Further, when the number of processing end notifications becomes equal to or more than a certain value, the supply clock control unit 3 refers to the count number of the external clock 8 and obtains the frequency division ratio as before.

On the other hand, an interrupt requesting an immediate response notified from the keyboard 4 or the like in FIG.
When the number 4 is received, the register 13 holding the frequency division ratio of the clock supplied to the CPU 1 is initialized. Thereby, C
PU1 is supplied with the maximum clock frequency allowed by CPU1.

In the embodiment described above, the interrupt monitoring unit 2 for monitoring the interrupt signal, the clock control unit 3 for controlling the supply clock, and the processing end notification for notifying the interrupt monitoring unit 2 of the end of the software processing. Performs multi-stage clock change processing, and the clock control unit 3 internally stores C
A clock frequency that is a multiple of the upper limit of the supply clock of the PU1 is input from the outside, and the CPU1 is set as an initial value of the frequency division ratio.
Hold the frequency division ratio close to the maximum allowable clock frequency of
The division ratio of the clock is calculated, and the division ratio is initialized according to the type of the interrupt signal notified.

The clock is supplied to the CPU 1 via a supply clock control unit 3. The end of the CPU processing is notified to the supply clock control unit 3 via the interrupt monitoring unit 2 using the interrupt port.

On the other hand, external interrupts such as the keyboard 4 and the various control signal transmitting units 5 are transmitted to the C
Notify PU1. At this time, the interrupt monitoring unit 2 notifies the supply clock unit 3 of the type of interrupt from outside. The supply clock control unit 3 obtains the frequency division ratio by referring to the processing end number notification or the count number of the external clock.

As a result, in the present embodiment, control for automatically changing the supply clock of the CPU 1 in multiple stages according to the amount of calculation processing can be performed, and the processing amount of the CPU 1 changes at certain time intervals. In addition, it is possible to change the supply clock of the computer device used for the real-time processing which continues to operate for a long time in multiple stages.

Therefore, by using the present invention, the supply clock can be dynamically switched in accordance with the calculation processing amount of the CPU 1 without the need for static information and means for designating the operating frequency. , The capacity of the CPU 1 can be maximized, and the power consumption can be reduced.

[0026]

As described above, the clock multi-stage change control apparatus and the clock multi-stage change control method of the present invention automatically change the supply clock of the CPU in multiple stages according to the calculation processing amount. Does not require static information or means for specifying the operating frequency,
Since the supply clock can be dynamically switched according to the calculation processing amount, it is possible not only to maximize the capacity of the CPU but also to reduce the power consumption. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment of a clock multi-stage change control device and a frequency multi-stage change control method according to the present invention.

FIG. 2 is a flowchart for explaining the operation of the clock frequency multi-stage change control device shown in FIG. 1;

FIG. 3 is a block diagram illustrating a specific configuration of the clock frequency multi-stage change control device illustrated in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Interrupt monitoring part 3 Supply clock control part 4 Keyboard 5 Various control signal transmission parts 8 External supply clock 9 Clock frequency dividing circuit 11 Interrupt signal 12 Arithmetic circuit 13 Register 14 Division rate calculating part

Claims (10)

[Claims] 1. An external clock supply means for supplying an external clock, a clock control means for controlling with a clock signal supplied from the external clock supply means, and a central processing means for performing central control based on the clock signal. A clock control device provided with: a termination signal input unit for inputting a processing end signal based on the processing information stored in the storage unit; and an interrupt signal input from outside for notifying the central processing unit. A notification unit for instructing the clock control unit on the type of an external interrupt signal notified to the central processing unit; and a monitoring unit configured to monitor processing of the interrupt signal and the central processing unit. A clock frequency multi-stage change control device, comprising: monitoring means; 2. The clock frequency multi-stage change control according to claim 1, further comprising a second notifying means for monitoring the end of processing from said central processing means and notifying said clock control means. apparatus. 3. The clock frequency multi-stage change control device according to claim 1, further comprising processing end notifying means for notifying the monitoring means of the end of the software processing. 4. An external clock supply means for supplying an external clock, a clock control means for controlling by a clock signal supplied from the external clock supply means, and a central processing means for performing central control based on the clock signal. A clock control device provided with: a termination signal input unit for inputting a processing end signal based on the processing information stored in the storage unit; and a notification for inputting an external interrupt signal to notify the central processing unit. Means for instructing the clock control means on the type of an external interrupt signal notified to the central processing means. 5. The clock control means includes: an input means for externally inputting a clock frequency that is a multiple of a clock signal supplied to the central processing means; and a dividing ratio required for an initial operation of the central processing means. Calculating means for calculating frequency division ratio information for obtaining the frequency division ratio according to the interrupt signal; storage means for storing the frequency division ratio information; and the external clock according to the frequency division ratio information stored in the storage means. The clock frequency multi-stage change control device according to claim 4, further comprising: clock frequency dividing means for transmitting a clock signal for frequency dividing the signal to the central control means. 6. The clock frequency multi-step change control according to claim 4, further comprising initialization means for initializing a frequency division ratio in accordance with a type of an interrupt signal notified to said notification means. apparatus. 7. An external clock supply means for supplying an external clock, a clock control means for performing control by a clock signal supplied from the external clock supply means, and a central processing means for performing central control based on the clock signal. A clock control device provided with: a step of inputting a processing end signal based on processing information stored in the storage means; a step of inputting an external interrupt signal to notify the central processing means; Instructing the clock control unit the type of the external interrupt signal notified to the central processing unit; andmonitoring the external interrupt signal and the end of the processing of the central processing unit. Characteristic clock frequency multi-stage change control method. 8. The method according to claim 1, further comprising the steps of: monitoring the end of processing from the central processing unit and notifying the clock control unit; and informing the monitoring unit of the end of software processing. 8. The control method for changing the clock frequency in multiple stages according to 7. 9. An external clock supply means for supplying an external clock, a clock control means for controlling by a clock signal supplied from the external clock supply means, and a central processing means for performing central control based on the clock signal. A clock control device provided with: a step of inputting a processing end signal based on processing information stored in the storage means; a step of inputting an external interrupt signal to notify the central processing means; And a step of instructing the clock control means of the type of the external interrupt signal notified to the central processing means. 10. A clock control means for externally inputting a clock frequency which is a multiple of a clock signal supplied to said central processing means, and a dividing ratio required for an initial operation of said central processing means. Obtaining the division ratio information to be obtained by calculation according to the interrupt signal; storing the division ratio information; dividing the external clock signal according to the division ratio information stored in the storage means. 10. The method according to claim 9, further comprising: transmitting a clock signal that circulates to the central control means; and initializing a frequency division ratio according to a type of an interrupt signal to be notified to the notifying means. The control method for changing the clock frequency in multiple stages as described above.