JPH1074845A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To significantly reduce the triple well system manufacturing process and to decrease the required number of photomasks. SOLUTION: A plurality of first n-type well regions 4, a plurality of second n-type well regions 5, and a plurality of first p-type well regions 6 are formed in a p-type semiconductor substrate 1. A second p-type well regions 7 is then formed in the first n-type well region 4, and impurity ions 3 are introduced over the entire surface without using masks, thus forming channel-dose regions 8-10 for controlling the threshold value of a transistor being formed in each well regions 5-7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device characterized by a method of forming a channel dose region of a triple-well type SRAM (static random access memory). The present invention relates to an apparatus and a method for manufacturing the same.

[0002]

2. Description of the Related Art With the recent increase in the degree of integration and performance of semiconductor devices, circuit malfunction due to incidence of α-rays (alpha-rays) has occurred.
That is, a soft error has become a problem, and in order to suppress such a soft error, it has been attempted to reduce the generation of electron-hole pairs due to α-ray incidence, which is one of the causes. One known method is to reduce the depth of a well region in which memory cells are arranged.

Here, referring to FIG. 4, a conventional SRAM
Will be described. FIG. 4 is a schematic cross-sectional view of one transistor constituting a flip-flop (FF) in a memory cell of an SRAM.
The n-type drain region 43 and the n-type source region 44 which are formed in the p-type well region 42 provided in the semiconductor device 1 and constitute a node, are constituted by a gate insulating film 45, and a word line 46.

When α rays 47 enter the inside of this transistor, the α rays 47 form an electron-hole pair consisting of electrons 48 and holes 49 inside the p-type well region 42 and the n-type silicon substrate 41. Occurs, electrons 48 of which are collected in the n-type drain region 43 by the depletion layer, and serve as a new input to the flip-flop, destroying the stored information stored in the node.

Since such a soft error depends on the amount of electron-hole pairs generated, that is, the penetration distance of the α-ray 47, the active region of the n-channel transistor is replaced with the n-type region as shown in FIG. Surrounding, that is, providing a p-type well region 42 and n
This can be suppressed by reducing the number of electrons 48 flowing into the mold drain region 43.

In this case, the depth of the p-type well region 42 is made shallower as shown by a broken line in the figure, thereby providing
The number of electrons 48 flowing into the mold drain region 43 can be further reduced.

However, when the n-type silicon substrate 41 is used to form the p-type well region 42 as shown in FIG. 4, the n-type silicon substrate is more expensive than the p-type silicon substrate, so that There is a problem that the SRAM is also expensive.

In order to solve such a price problem,
A so-called triple well system in which an n-type well region is formed on an inexpensive p-type silicon substrate and a p-type well region is provided in the n-type well region is employed. This will be described with reference to FIG.

Referring to FIG. 5A, in the case of the triple well method, first, an element isolation oxide film 52 is formed on a p-type silicon substrate 51 by selective oxidation, and then a P-type silicon film 51 is formed using a first photoresist 53 as a mask.
After the (phosphorus) ions 54 are selectively implanted, drive-in diffusion is performed by heat treatment to form an n-type well region 55 for forming an n-channel transistor constituting a memory cell and a part of a peripheral circuit. An n-type well region 56 for forming a p-channel transistor to be formed is formed.

[0010] Next, after removing the first photoresist 53, a new second photoresist 57 is formed and a p-type well region is formed in the n-type well region 55. This second
An ion implantation region 59 is formed by selectively implanting B (boron) ions 58 using the photoresist 57 as a mask.

Next, after the second photoresist 57 is removed, a new third photoresist 60 is formed, and B ions 61 are selectively used using the third photoresist 60 as a mask. And then drive-in diffusion by heat treatment to form a p-type well region 62 for forming an n-channel transistor forming a part of a peripheral circuit.
At the same time, the p-type well region 63 is formed by drive-in diffusion of B in the ion implantation region 59.

Next, after the third photoresist 60 is removed, a new fourth photoresist 64 is formed, and B ions 65 are selectively used by using the fourth photoresist 64 as a mask. by ion implantation, the channel comprising a p-type well region 52 and p-type well region 53 from the p ⁺ -type region
Stops 66 and 67 are formed.

In this case, the ion implantation is performed by controlling the acceleration voltage of the ion implantation so that the peak of the concentration of B constituting the channel stops 66 and 67 is located immediately below the element isolation oxide film 52.

Next, after removing the fourth photoresist 64, a new fifth photoresist 68 is formed, and B ions 69 are selectively used with the fifth photoresist 68 as a mask. A channel dose region 70 is formed on the surface of the p-type well region 62 by ion implantation, and the threshold voltage of an n-channel transistor formed in the p-type well region 62 is controlled to an arbitrary value.

Next, after removing the fifth photoresist 68, a new sixth photoresist 71 is formed. Using the sixth photoresist 71 as a mask, B ions 72 are selectively formed. A channel dose region 73 is formed on the surface of the p-type well region 63 by ion implantation, and the threshold voltage of an n-channel type transistor constituting a memory cell formed in the p-type well region 63 is set to an arbitrary value. Control to a value.

Next, after the sixth photoresist 71 is removed, a new seventh photoresist 74 is formed, and B ions 75 are selectively used with the seventh photoresist 74 as a mask. A channel dose region 76 is formed on the surface of the n-type well region 56, and the threshold voltage of the p-channel transistor formed in the n-type well region 56 is controlled to an arbitrary value.

Next, although not shown, a gate insulating film, a gate electrode, and a source / drain region are formed in each well region, and a predetermined wiring or the like is formed.
Complete the RAM.

[0018]

However, in such a triple well system, although an inexpensive p-type silicon substrate can be used as a substrate, there is a problem that the manufacturing process becomes complicated.

That is, in the manufacturing process of the triple well type SRAM, three photolithography processes and ion implantation processes are required for controlling the threshold voltage of the transistor formed in each well region.

Also, three photomasks used in such a photolithography process are required, but FIG.
In the step of FIG. 5C, the photomask used in the step of FIG. 5C can be used. In the step of FIG. 7F, the photomask used in the step of FIG. Therefore, one new photomask is required for the process of FIG.

Accordingly, an object of the present invention is to greatly reduce the number of manufacturing steps of a triple well system and to reduce the number of required photomasks.

[0022]

FIG. 1 is an explanatory view of the principle configuration of the present invention. Referring to FIG. 1, means for solving the problems in the present invention will be described. See FIG. 1. (1) In the present invention, a plurality of first n-type well regions 4, a plurality of second n-type well regions 5, and a plurality of first p-type wells are formed in a p-type semiconductor substrate 1. In a semiconductor device in which a region 6 is provided and a second p-type well region 7 is provided in a first n-type well region 4, each channel dose for controlling a threshold value provided in each of the well regions 5 to 7 is provided. The difference between the impurity concentration of the regions 8 to 10 and the impurity concentration of each of the well regions 5 to 7 is the same.

As described above, in the triple well type semiconductor device, the channel / dose regions 8 to 1 can be maskless.
0 is formed, each channel / dose region 8 to 1
A major feature in the element configuration is that the difference between the impurity concentration of 0 and the impurity concentration of each of the well regions 5 to 7 is the same.

(2) According to the present invention, in the above (1), a pair of driver transistors and a pair of access transistors constituting a flip-flop circuit together with a pair of load elements are provided in the second p-type well region 7. In addition, a transistor constituting a peripheral circuit is provided in the second n-type well region 5 and the second p-type well region 6.

As described above, the triple-well SRAM is used.
, The impurity concentration of each of the well regions 5 to 7 is controlled to a predetermined value in advance, so that the difference between the impurity concentration of each of the channel dose regions 8 to 10 and the impurity concentration of each of the well regions 5 to 7 is the same. In other words, channel without mask
Even if the dose regions 8 to 10 are formed, the well regions 5 to 7
Can be arbitrarily controlled.

(3) Further, according to the present invention, in the method for manufacturing a semiconductor device, a plurality of first n
Forming a plurality of second well regions 4, a plurality of second n-type well regions 5, and a plurality of first p-type well regions 6;
After forming the second p-type well region 7 in the first n-type well region 4, the impurity ions 3 are formed on the entire surface without using a mask.
To control the threshold voltage of the transistor formed in each of the well regions 5 to 7.
It is characterized in that dose regions 8 to 10 are formed.

As described above, in the manufacturing process of the triple-well type semiconductor device, the channel dose regions 8 to 10 are formed in the well regions 5 to 7 only by one ion implantation step without using a mask. Since three photolithography steps and two ion implantation steps in the channel / dose region forming step are not required and one photomask can be omitted, the manufacturing process can be greatly simplified. it can.

(4) According to the present invention, in the above (3), a pair of driver transistors and a pair of access transistors constituting a flip-flop circuit together with a pair of load elements are provided in the second p-type well region 7. In addition, a transistor forming a peripheral circuit is formed in the second n-type well region 5 and the second p-type well region 6.

As described above, by forming the channel dose regions 8 to 10 at a time by the maskless ion implantation process, the manufacturing process of the triple well type SRAM can be greatly reduced, and therefore, the cost can be reduced. S
RAM can be provided.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Here, a first embodiment of the present invention will be described with reference to FIGS. The steps up to the step of forming a channel stop are basically the same as the steps of manufacturing a conventional triple-well SRAM.

Referring to FIG. 2A, first, after an element isolation oxide film 12 is formed on a p-type silicon substrate 11 by selective oxidation, a first photoresist 1 is formed.
3 is used as a mask to accelerate P ions 14 to an acceleration energy of 300.
keV is selectively implanted at a dose of 2 × 10 ¹³ cm ⁻² , and then heat-treated for 5 hours in a nitrogen atmosphere at 1150 ° C. to drive-in and diffuse the implanted P, thereby memory cells are implanted. An n-type well region 15 for forming a constituent n-channel transistor and an n-type well region 16 for forming a p-channel transistor forming a part of a peripheral circuit are formed.

Next, after removing the first photoresist 13, a new second photoresist 17 is formed, and a p-type well region is formed in the n-type well region 15. This second
Forming an ion implanted region 19 by the selective ion implantation of B ions 18 using the photoresist 17 as a mask in a dose of an acceleration energy ^{180keV, 5 × 10 13 cm -2} .

Next, after the second photoresist 17 is removed, a new third photoresist 20 is formed, and the B photoresist 21 is accelerated by using the third photoresist 20 as a mask. After selective ion implantation at a dose of 180 keV and 2 × 10 ¹³ cm ⁻² , heat treatment is performed for 1 hour in a nitrogen atmosphere at 1150 ° C. to drive-diffuse the implanted B, thereby forming a peripheral circuit. Is formed at the same time as forming the p-type well region 22 for forming the n-channel transistor constituting a part of the P-type region, and the B of the ion implantation region 19 is also drive-in diffused to form the p-type well region 23 having a depth of 1 μm.

As a result of the twice drive-in diffusion, the depth of the n-type well region 15 and the n-type well region 16 for forming the p-channel type transistor forming a part of the peripheral circuit are 5 μm. Becomes

Next, after the third photoresist 20 is removed, a new fourth photoresist 24 is formed, and the B ions 25 are accelerated using the fourth photoresist 24 as a mask. By selectively implanting ions at a dose of 100 keV and 5 × 10 ¹³ cm ⁻² , the p-type well region 22 and the p-type well region are positioned so that the B concentration peak is located immediately below the element isolation oxide film 12. At 23, channel stops 26 and 27 made of p ⁺ -type regions are formed.

Next, after the fourth photoresist 24 is removed, the B ions 28 are irradiated without mask with an acceleration energy of 18 keV and at a rate of 18 keV.
By implanting ions over the entire surface at a dose of 2 × 10 ¹² cm ⁻² , the channel dose regions 29 to 3 are formed on the surfaces of the p-type well regions 22 and 23 and the n-type well region 16.
Form one.

Next, although not shown, a pair of driver transistors and a pair of load elements and a pair of access transistors forming a flip-flop circuit are formed in the p-type well region 23 in the same manner as in the conventional manufacturing process. After forming transistors constituting a peripheral circuit in the p-type well region 22 and the n-type well region 16, predetermined wirings and the like are formed to complete the SRAM.

The load element in this case is MISFE
T, a thin film transistor (TFT), a polycrystalline silicon resistance element, or the like.

As described above, in the embodiment of the present invention, by controlling the dose at the time of forming each well region to a predetermined value, the threshold value of each transistor can be controlled by a single maskless ion implantation step. Since the channel dose regions 29 to 31 for controlling the value voltage can be formed, three photoresist steps in the conventional manufacturing process can be omitted, and three times in the conventional manufacturing process can be eliminated. It is possible to eliminate the need for two ion implantation steps of the above ion implantation steps.

Further, since the maskless ion implantation is used, a new single photomask required in the conventional channel / dose region forming step is not required, so that the photomask manufacturing process and its cost are reduced. It becomes unnecessary.

The structure of the SRAM according to the present invention is characterized in that the impurity concentration of each of the channel dose regions 29, 30, and 31 is different from that of each of the channel dose regions 29, 30, and 31.
Dose and well regions 22 and 2 for forming
Therefore, the difference obtained by subtracting the impurity concentration of each of the well regions 22, 23, and 16 from the impurity concentration of each of the channel dose regions 29, 30, and 31 is:
The dose becomes a common dose and becomes equal within a range such as a variation in the distribution of the dose in the wafer surface in the ion implantation process.

In the above description of the embodiment, the element isolation oxide film is formed in the first step. However, it may be formed by performing selective oxidation after forming the well regions 16, 22, and 23. Also, selective oxidation is performed after the formation of the n-type well region 16 and then the well regions 22 and 2 are formed.
3 may be formed.

Further, such an element isolation oxide film does not need to be a selective oxide film, and after forming a groove, a CV is formed in the groove.
D (Chemical Vapor Deposition)-It may be formed by burying an insulating film.

In the above description of the embodiment, the ion implantation for forming the p-type well region 23 is performed, and then the ion implantation for forming the p-type well region 22 is performed. It may be performed in the reverse order.

In the above description of the embodiment, although the channel stop is not formed because the impurity concentration of the n-type well region 16 is high, the P ion is ionized depending on the impurity concentration of the n-type well region. Inject,
A channel stop composed of an n ⁺ -type region may be formed so that the peak of the P concentration is located immediately below the element isolation oxide film 22.

[0046]

According to the present invention, when a semiconductor device such as a triple-well SRAM is formed using an inexpensive p-type silicon substrate, the threshold value of a transistor formed in each well region is controlled. Maskless ion implantation
By performing the steps in one step, the number of manufacturing steps can be significantly reduced, and the number of photomasks to be used can be reduced, so that an SRAM having excellent soft error resistance can be manufactured at low cost and with high throughput. Can be manufactured.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process partway through an embodiment of the present invention.

FIG. 3 is an explanatory view of a manufacturing process of the embodiment of the present invention after FIG. 2;

FIG. 4 is an explanatory diagram of a conventional soft error.

FIG. 5 is an explanatory diagram of a manufacturing process of a conventional triple-well type memory cell up to a certain point.

FIG. 6 shows a conventional triple well type memory cell.
It is explanatory drawing of the following manufacturing process.

FIG. 7 shows a conventional triple well type memory cell.
It is explanatory drawing of the following manufacturing process.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 p-type semiconductor substrate 2 element isolation oxide film 3 impurity ion 4 n-type well region 5 n-type well region 6 p-type well region 7 p-type well region 8 channel dose region 9 channel dose region 10 channel dose region 11 p Type silicon substrate 12 Element isolation oxide film 13 First photoresist 14 P ion 15 n-type well region 16 n-type well region 17 second photoresist 18 B ion 19 ion implantation region 20 third photoresist 21 B ion 22 p-type well region 23 p-type well region 24 fourth photoresist 25 B ion 26 channel stop 27 channel stop 28 B ion 29 channel dose region 30 channel dose region 31 channel dose region 41 n-type silicon substrate 42 p-type well region 43 n Type drain region 44 n-type source region 45 gate insulating film 46 word line 47 α-line 48 electron 49 hole 51 p-type silicon substrate 52 element isolation oxide film 53 first photoresist 54 P ion 55 n-type well region 56 n-type Well region 57 Second photoresist 58 B ion 59 Ion implantation region 60 Third photoresist 61 B ion 62 p-type well region 63 p-type well region 64 fourth photoresist 65 B ion 66 channel stop 67 channel Stop 68 fifth photoresist 69 B ions 70 channel dose region 71 sixth photoresist 72 B ions 73 channel dose region 74 seventh photoresist 75 B ions 76 channel dose region

Claims (4)

[Claims] A plurality of first n-type well regions, a plurality of second n-type well regions, and a plurality of first p-type well regions provided in a p-type semiconductor substrate; N
In a semiconductor device in which a second p-type well region is provided in a type well region, a difference between an impurity concentration of each channel dose region for controlling a threshold provided in each of the well regions and an impurity concentration of each of the well regions. Are the same. 2. A pair of driver transistors and a pair of access transistors constituting a flip-flop circuit together with a pair of load elements in the second p-type well region, and the second n-type well region and the second n-type well region are provided. 2. The semiconductor device according to claim 1, wherein a transistor forming a peripheral circuit is provided in the second p-type well region. 3. A plurality of first n-type well regions, a plurality of second n-type well regions, and a plurality of first p-type well regions are formed in a p-type semiconductor substrate. After forming a second p-type well region in one n-type well region, impurity ions are introduced into the entire surface without using a mask, thereby controlling a threshold value of a transistor formed in each of the well regions. A method for manufacturing a semiconductor device, comprising forming a channel dose region for the semiconductor device. 4. A pair of driver transistors and a pair of access transistors forming a flip-flop circuit together with a pair of load elements in the second p-type well region, and the second n-type well region and 4. The method according to claim 3, wherein a transistor forming a peripheral circuit is formed in the second p-type well region.