JP2000058676A - Manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which permits the number of times of mask use to be reduced by one. SOLUTION: Using a first mask 2, a second conductivity-type buried well 3 is formed, and a second conductivity-type impurity ion for determining the threshold of the transistor of a memory cell is implanted in a memory cell part 1. Using a second mask 9, a first conductivity-type wells 10, 10 are formed respectively at the memory cell part 1 and a second conductivity-type MOS transistor part 8. Using the second mask 9, an n+ diffused layer 11 and n+ diffused layer 14 are formed for determining the threshold of the transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method of manufacturing a semiconductor device, and more particularly to a triple-well static random access memory (hereinafter referred to as an SRA) including a memory cell and a peripheral circuit.
M).

[0002]

2. Description of the Related Art With the recent increase in the degree of integration and performance of semiconductor devices, circuit malfunctions due to incidence of α-rays, that is, soft errors, have become a problem. Attempts have been made to reduce the generation of electron-hole pairs due to the incidence of α-rays, which is known as one method of reducing the depth of a well region where memory cells are arranged. ing.

Here, referring to FIG. 3, a conventional SRAM
Will be described. FIG. 3 is a schematic cross-sectional view of one transistor constituting an FF (flip flop) in the memory cell of the SRAM. This transistor is formed by a p-type transistor provided in an n-type silicon substrate 41.
N-type drain region 43, n-type source region 44, and gate insulating film 4
5 and a word line 46.

When α-rays 47 enter the inside of the transistor, the α-rays 47 form an electron-hole pair consisting of electrons 48 and holes 49 inside the p-type well region 42 and the n-type silicon substrate 41. The generated electrons 48 are collected in the n-type drain region 43 by the depletion layer, and serve as a new input to the flip-flop, destroying the stored information stored in the node.

Since such a soft error depends on the amount of electron-hole pairs generated, that is, the penetration distance of the α-ray 47, the node region of the n-channel transistor is changed to the n-type region as shown in FIG. Surrounding, that is, electrons 48 flowing into the n-type drain region 43 by providing the p-type well region 42
Can be suppressed by reducing the number.

In this case, by making the depth of the p-type well region 42 shallower as shown by a broken line in the figure,
The number of electrons 48 flowing into the n-type drain region 43 can be further reduced.

However, as shown in FIG.
When the n-type silicon substrate 41 is used for forming the semiconductor device, the n-type silicon substrate is more expensive than the p-type silicon substrate.

In order to solve such a price problem, a so-called triple well system in which an n-type well region is formed on an inexpensive p-type silicon substrate and further a p-type well region is provided in the n-type well region Has been adopted.

The present invention relates to a method for forming a diffusion layer of a transistor in a memory cell portion in an SRAM using such a triple well structure.

Conventionally, most of the number of transistors used in a memory cell portion of a transistor used in an SRAM is used in a memory cell portion in order to make a standby current approximately equal to that of a memory cell in a peripheral portion. For this reason, the threshold value of the transistor in the memory cell portion is set to a higher value than the threshold value of the peripheral circuit.

For this reason, in the SRAM using the triple well structure as a countermeasure against soft errors, the threshold value of the transistor in the memory cell portion is determined by implanting the channel of the transistor in the peripheral circuit and then implanting it. It is adjusted by the method.

FIG. 4 is a diagram showing an outline of a conventional method of forming a well and forming a diffusion layer. FIG.
FIG. 4 is a diagram illustrating a manufacturing process of a method for forming a well and a diffusion layer using a cross-sectional view of a semiconductor device.

In FIG. 5, a memory cell portion and a peripheral circuit portion formed on one substrate are extracted and drawn.

Referring to FIG. 5A, mask 2 is formed on p-type substrate 21 to cover PMOS portion 4 and NMOS portion 8 and has an opening above memory cell portion 1. Using the mask 2, n-type impurity ions are implanted into the semiconductor substrate 21 to form an embedded N well 3 for countermeasures against soft errors. After that, the resist 2 is removed.

Referring to FIG. 5B, the PMO of the peripheral circuit
An opening on the S portion 4 and a field oxide film 22
The mask 5 having an opening on a part of the surface of the semiconductor substrate 21 is formed on the semiconductor substrate 21. Using the mask 5, n-type impurity ions are implanted into the semiconductor substrate 21 and N
A well 6 is formed. At this time, the P ⁻ layer 2 is connected to the N well 3 immediately below the field oxide film 22.
The side wall portion 24 of the N well 3 surrounding the N well 3 is also formed. Further, using a mask 5, N ⁺ impurity ions are implanted, and P
A MOS N ⁺ diffusion layer 7 is also formed. The resist 5 is thereafter removed.

Referring to FIG. 5C, the NMO of the peripheral circuit
A mask 9 having an opening on the S portion 8 and the memory cell portion 1 is formed on the semiconductor substrate 21. Using the mask 9, p-type impurity ions are implanted, and the P wells 10 and 1 are implanted.
0 is formed. Subsequently, n-type impurity ions are implanted using the mask 9 to form an N ⁺ diffusion layer 11 in the NMOS 8 portion and an N ⁺ diffusion layer (described later, before additional implantation) 12 in the memory cell portion 1. . After that, the resist 9 is removed.

Referring to FIG. 5D, memory cell portion 1
A mask 13 having an opening only on the semiconductor substrate 2
1 is formed. Using the mask 13, p-type impurity ions are additionally implanted to form an N ⁺ diffusion layer 14 in the memory cell portion. When the resist 13 is removed and a memory cell, a PMOS transistor, and an NMOS transistor are formed in the portions 1, 4, and 8, a semiconductor device is completed.

[0018]

As described above, in the conventional method of forming a well and forming a diffusion layer, FIG.
Referring to FIG. 5 and FIG. 5, four masks are used. Therefore, there is a problem that the number of manufacturing steps is large and the manufacturing cost is high.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. By reducing the number of times a mask is used, the number of manufacturing steps of a semiconductor device can be reduced, and the manufacturing cost can be reduced. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which is improved as possible.

[0020]

The invention according to claim 1 is
The present invention relates to a method for manufacturing a semiconductor device having a triple well structure including a memory cell and a peripheral circuit. A first conductivity type semiconductor substrate is prepared. A first mask having an opening only on a portion where the memory cell is to be formed is formed on the semiconductor substrate. Using the first mask, impurity ions of the second conductivity type are implanted in the semiconductor substrate, and a buried well of the second conductivity type is formed in the semiconductor substrate. The first
Using the mask described above, impurity ions of the second conductivity type for determining the threshold value of the transistor of the memory cell are implanted into a portion where the memory cell is formed. A second mask having an opening is formed on the semiconductor substrate on a portion where the memory cell is to be formed and on a portion where the second conductivity type MOS transistor of the peripheral circuit is to be formed. Impurity ions of the first conductivity type are implanted into the surface of the semiconductor substrate using the second mask, and a portion for forming the memory cell and a portion for forming the second conductivity type MOS transistor are respectively implanted into the semiconductor substrate. A well of one conductivity type is formed. A threshold value of a transistor of the memory cell is determined in a portion where the memory cell is formed and a portion where the second conductivity type MOS transistor is formed by continuously using the second mask. MOS
A second conductivity type impurity ion for determining the threshold value of the transistor is implanted.

According to the present invention, the second conductivity type impurity ions for determining the threshold value of the transistor of the memory cell are continuously used by further using the first mask used for forming the buried well. Since the implantation is performed, the number of times the mask is used can be reduced by one. Thus, the number of manufacturing steps of the semiconductor device is reduced, and the manufacturing cost is reduced.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram for explaining an outline of a method for forming a well and a diffusion layer according to the present invention. FIG. 2 shows steps of a method for manufacturing a semiconductor device according to the present invention.
It is shown in a sectional view.

Referring to FIG. 2A, a mask 2 covering the PMOS portion 4 and the NMOS portion 8 and having an opening above the memory cell portion 1 is formed on the p-type semiconductor substrate 21. Using the mask 2, n-type impurity ions are implanted into the semiconductor substrate 21 to form a buried N-well 3 for soft error countermeasures.

By using the mask 2 continuously, ion implantation for additional implantation into the transistor of the memory cell portion 1 is performed to form an N ⁺ diffusion layer (additional implantation) 15. After that, the resist 2 is removed.

Referring to FIG. 2B, the PMO of the peripheral circuit
A resist 5 having an opening in the S portion 4 and having an opening on a part of the surface of the field oxide film 22 is formed on the semiconductor substrate 21. Using the mask 5, n-type impurity ions are implanted into the surface of the semiconductor substrate 21 to form the N well 6 of the PMOS portion 4. At the same time, the N well 3 is connected to the N well 3 immediately below the field oxide film 22. ^- layer 23
A sidewall portion 24 of the N well 3 is formed surrounding the N well 3. Further, using a mask 5, p-type impurity ions are implanted, and N
A PMOS P ⁺ diffusion layer 7 is formed on the surface of the well 6. After that, the resist 5 is removed.

Referring to FIG. 2C, the NMO of the peripheral circuit
A mask 9 having openings on the S portion 8 and the memory cell portion 1 is formed on the semiconductor substrate 21. Using the mask 9, p-type impurity ions are implanted into the surface of the semiconductor substrate 21 to form P wells 10. Mask 9
Is then used to implant n-type impurity ions,
The N ⁺ diffusion layer 11 of the memory cell and the N ⁺ diffusion layer 14 of the memory cell are formed. At this time, the impurity concentration of the N ⁺
The N ⁺ diffusion layer 11 is injected only in the step shown in FIG.
Higher than.

The structure of the well and the diffusion layer in each transistor portion formed by such a method is the same as that formed by the conventional method.

However, referring to FIG. 2A, buried N well 3 is formed using mask 2, and N ⁺ diffusion layer 15 for determining the threshold value of the transistor of the memory cell is formed. Is also formed, so that the number of times the mask is used is reduced by one. Therefore, the number of manufacturing steps of the semiconductor device can be reduced, and the manufacturing cost can be reduced.

[0030]

As described above, according to the present invention, the number of times of using the mask can be reduced by one time as compared with the conventional method, and the manufacturing process of the semiconductor device can be reduced and the manufacturing cost can be reduced. Can be achieved.

[Brief description of the drawings]

FIG. 1 is a diagram for illustrating an outline of a method for manufacturing a semiconductor device according to an embodiment.

FIG. 2 is a cross-sectional view of the semiconductor device, illustrating a method for manufacturing the semiconductor device according to the embodiment;

FIG. 3 is a diagram for explaining a soft error.

FIG. 4 is a diagram showing an outline of a conventional method for manufacturing a semiconductor device.

FIG. 5 is a cross-sectional view of a semiconductor device illustrating a method for manufacturing a conventional semiconductor device.

[Explanation of symbols]

1 memory cell part, 2 mask, 3 buried N well, 4 PMOS part, 5 mask, 6 N well, 8
NMOS part, 9 mask, 10 P well, 11
N ⁺ diffusion layer, 15 N ⁺ diffusion layer.

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device having a triple well structure including a memory cell and a peripheral circuit, comprising: providing a semiconductor substrate of a first conductivity type; and forming the memory cell on the semiconductor substrate. Forming a first mask having an opening only on a portion to be formed; and implanting a second conductivity type impurity ion into the semiconductor substrate using the first mask, thereby forming the semiconductor. Forming a buried well of the second conductivity type in the substrate; and continuously using the first mask to form impurity ions of the second conductivity type for determining a threshold value of the transistor of the memory cell. Implanting into the portion where the memory cell is to be formed; and forming the second conductivity type MOS transistor of the peripheral circuit over the portion where the memory cell is to be formed on the semiconductor substrate. Forming a second mask having an opening thereon; using the second mask, implanting first conductivity type impurity ions into the surface of the semiconductor substrate to form the memory cell; and A step of forming a first conductivity type well in each of the portions forming the second conductivity type MOS transistor; and a portion forming the memory cell and the second conductivity type using the second mask continuously. A step of determining a threshold value of a transistor of the memory cell and implanting a second conductivity type impurity ion for determining a threshold value of the second conductivity type MOS transistor into a portion where a MOS transistor is formed; A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the first conductivity type is p-type, and the second conductivity type is p-type.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the conductivity type is n-type.