JPH1074791A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH1074791A JPH1074791A JP8231114A JP23111496A JPH1074791A JP H1074791 A JPH1074791 A JP H1074791A JP 8231114 A JP8231114 A JP 8231114A JP 23111496 A JP23111496 A JP 23111496A JP H1074791 A JPH1074791 A JP H1074791A
- Authority
- JP
- Japan
- Prior art keywords
- pads
- pad
- bonding
- semiconductor device
- potential
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/49171—Fan-out arrangements
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H01L2924/01082—Lead [Pb]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、集積回路に使用さ
れる半導体装置に関し、詳しくはパッドの配置に関す
る。[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device used for an integrated circuit, and more particularly to a pad arrangement.
【０００２】[0002]
【従来の技術】半導体装置における入出力パッドのレイ
アウト面積を縮小するためのパッド配置が特開平５−29
1475号公報に開示されている。図４に示す如く、外部ピ
ンとして使用されるリードフレーム電極F2からダイパッ
ドY2上に形成された半導体基板Ｂ２のパッド電極H2へ直
接ワイヤボンディングすることができない場合、外部ピ
ンとして使用されないリードフレーム電極J1を使用す
る。外部端子E2からリードフレーム電極F2により半導体
集積装置内に配線され、ワイヤボンディングG2によりリ
ードフレーム電極F2からリードフレーム電極J1に、ワイ
ヤボンディングG2′によりリードフレーム電極J1からパ
ッド電極H2に接続される。外部ピンとして使用されるリ
ードフレーム電極F1からパッド電極H1へは直接ワイヤボ
ンディングされている。2. Description of the Related Art A pad arrangement for reducing a layout area of input / output pads in a semiconductor device is disclosed in Japanese Patent Laid-Open No. 5-29.
It is disclosed in Japanese Patent Publication No. 1475. As shown in FIG. 4, when wire bonding cannot directly be performed from the lead frame electrode F2 used as an external pin to the pad electrode H2 of the semiconductor substrate B2 formed on the die pad Y2, the lead frame electrode J1 not used as an external pin is used. Use The external terminal E2 is wired into the semiconductor integrated device by the lead frame electrode F2, and is connected to the lead frame electrode J1 from the lead frame electrode F2 by wire bonding G2 and from the lead frame electrode J1 to the pad electrode H2 by wire bonding G2 '. Wire bonding is directly performed from the lead frame electrode F1 used as an external pin to the pad electrode H1.
【０００３】従って高集積化に伴い多数の外部ピンが必
要になり、リードフレーム電極間のピッチが狭くなっ
て、パッド電極とリードフレーム電極とを直接接続する
にはボンディングワイヤが交叉する場合であっても、外
部ピンとして使用されない第２のリードフレーム電極を
介することにより、リードフレーム電極とパッド電極と
を容易に接続することができる。[0003] Therefore, a large number of external pins are required in accordance with the high integration, the pitch between the lead frame electrodes is narrowed, and bonding wires intersect to directly connect the pad electrodes and the lead frame electrodes. However, the lead frame electrode and the pad electrode can be easily connected via the second lead frame electrode that is not used as an external pin.
【０００４】また特開平６−168978号公報には、図５に
示す如く、集積回路チップ１の周縁部にボンディングパ
ッド２を２列に、互い違いに配置し、互いに隣合うボン
ディングワイヤの間隔を適切に維持し、それらが互いに
物理的に干渉しないように構成することにより、レイア
ウト面積の縮小を図る集積回路のパッド配置が開示され
ている。Japanese Patent Application Laid-Open No. 6-168978 discloses that, as shown in FIG. 5, bonding pads 2 are alternately arranged in two rows on the periphery of an integrated circuit chip 1 so that the distance between adjacent bonding wires is appropriately adjusted. In order to reduce the layout area, a pad arrangement of an integrated circuit is disclosed, which is configured so that they do not physically interfere with each other.
【０００５】[0005]
【発明が解決しようとする課題】図４に示す半導体集積
装置においては、例えば図６に示す如く、データ信号S1
用のボンディングワイヤ３と、データ信号S2用のボンデ
ィングワイヤ３と、クロック信号CLK 用のボンディング
ワイヤ３と、データ信号S3用のボンディングワイヤ３と
がこの順に隣接している。このようにレベルが変動する
信号用のボンディングワイヤが隣接する場合には、ボン
ディングパッド２同志及びボンディングワイヤ３同志の
寄生容量結合に起因する電気的干渉により信号にノイズ
が負荷されるという問題がある。In the semiconductor integrated device shown in FIG. 4, for example, as shown in FIG.
The bonding wire 3 for the data signal, the bonding wire 3 for the data signal S2, the bonding wire 3 for the clock signal CLK, and the bonding wire 3 for the data signal S3 are adjacent in this order. When the signal bonding wires whose levels fluctuate in this manner are adjacent to each other, there is a problem that noise is applied to the signals due to electrical interference caused by the parasitic capacitance coupling between the bonding pads 2 and the bonding wires 3. .
【０００６】図６に示すようにデータ信号S1用のボンデ
ィングワイヤ３と、データ信号S2用のボンディングワイ
ヤ３と、クロック信号CLK 用のボンディングワイヤ３と
が隣接している場合のパッド近傍の信号線における等価
回路を図７に示す。データ信号S1用の信号線と、データ
信号S2用の信号線との間には寄生容量C31 が付加され、
データ信号S2用の信号線と、クロック信号CLK 用の信号
線（クロック線）との間には寄生容量C32 が付加され
る。チップ１内で生成されたデータ信号S2-0は２つのイ
ンバータ11, 12を経て、ボンディングパッド２及びボン
ディングワイヤ３を介してリードフレームへ伝達され
る。As shown in FIG. 6, a signal line near a pad when the bonding wire 3 for the data signal S1, the bonding wire 3 for the data signal S2, and the bonding wire 3 for the clock signal CLK are adjacent to each other. FIG. 7 shows an equivalent circuit in FIG. A parasitic capacitance C31 is added between the signal line for the data signal S1 and the signal line for the data signal S2,
A parasitic capacitance C32 is added between the signal line for the data signal S2 and the signal line (clock line) for the clock signal CLK. The data signal S2-0 generated in the chip 1 is transmitted to the lead frame via the bonding pads 2 and the bonding wires 3 via the two inverters 11 and 12.
【０００７】このときのクロック信号CLK ，データ信号
S2及びデータ信号S2-0の信号波形の例を図８に示す。ク
ロック信号CLK の周期がデータ信号S2-0の周期より短く
（1/3)、クロック信号CLK の立ち上がりでデータ信号S2
-0が立ち上がった場合、クロック線の電位が“Ｈ”から
“Ｌ”へ変化するとき、また“Ｌ”から“Ｈ”へ変化す
るときに、寄生容量結合による電気的干渉でデータ信号
S2にはノイズが発生する。図８では、データ信号がクロ
ック信号から電気的干渉を受ける場合を示しているが、
データ信号間においても同様の干渉が生じる。At this time, the clock signal CLK and the data signal
FIG. 8 shows an example of signal waveforms of S2 and the data signal S2-0. The cycle of the clock signal CLK is shorter than the cycle of the data signal S2-0 (1/3), and the data signal S2
When -0 rises, when the potential of the clock line changes from "H" to "L" or when it changes from "L" to "H", the data signal is generated due to electrical interference due to parasitic capacitive coupling.
Noise occurs in S2. FIG. 8 shows a case where the data signal receives electrical interference from the clock signal,
Similar interference occurs between data signals.
【０００８】図５に示す場合においても同様に、この電
気的干渉については考慮されていない。さらに図５に示
す場合は、ボンディングパッド２同志の間隔、及びボン
ディングワイヤ３同志の間隔が、図６に示す場合より狭
いので、ボンディングパッド２同志及びボンディングワ
イヤ３同志の寄生容量結合が大きい。これにより電気的
干渉がより顕著に現れ、大きいノイズが発生する。Similarly, in the case shown in FIG. 5, this electrical interference is not considered. Further, in the case shown in FIG. 5, the distance between the bonding pads 2 and the distance between the bonding wires 3 are smaller than in the case shown in FIG. 6, so that the parasitic capacitance coupling between the bonding pads 2 and the bonding wires 3 is large. As a result, electrical interference appears more remarkably, and large noise is generated.
【０００９】本発明は、斯かる事情に鑑みてなされたも
のであり、変動電位用のパッドの両側に固定電位用のパ
ッドを配置することにより、電気的干渉によるノイズの
発生を防止することが可能な半導体装置を提供すること
を目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and by arranging fixed potential pads on both sides of a variable potential pad, it is possible to prevent generation of noise due to electrical interference. It is an object to provide a possible semiconductor device.
【００１０】[0010]
【課題を解決するための手段】請求項１記載の発明は、
その周縁部に複数のパッドが設けられた半導体チップ
と、該パッドと電気的に接続された複数の導電性リード
とを備える半導体装置において、変動電位用のパッドの
両側に固定電位用のパッドが配置されていることを特徴
とする。According to the first aspect of the present invention,
In a semiconductor device including a semiconductor chip having a plurality of pads provided on a peripheral portion thereof and a plurality of conductive leads electrically connected to the pads, fixed potential pads are provided on both sides of the variable potential pads. It is characterized by being arranged.
【００１１】隣接するパッド同志、又はパッドと導電性
リードとを接続する隣接するボンディングワイヤ同志の
寄生容量結合が、電位が安定している固定電位用のパッ
ドの配置によりガードされ、ノイズの一因である電気的
干渉が回避され得る。[0011] Parasitic capacitive coupling between adjacent pads or between adjacent bonding wires connecting the pads and the conductive leads is guarded by the arrangement of fixed potential pads whose potentials are stable, which contributes to noise. Electrical interference can be avoided.
【００１２】請求項２記載の発明は、請求項１におい
て、変動電位用のパッドは、データ信号用のパッド又は
クロック信号用のパッドを含み、固定電位用のパッド
は、接地用のパッド又は電源用のパッドを含むことを特
徴とする。According to a second aspect of the present invention, in the first aspect, the pad for a variable potential includes a pad for a data signal or a pad for a clock signal, and the pad for a fixed potential is a grounding pad or a power supply. And a pad for use with the device.
【００１３】これにより隣接するパッド間の寄生容量結
合に起因する、ノイズの原因である電気的干渉を回避す
ることが可能であるので、電位が変動する例えばデータ
線にノイズが発生することを防止することができる。従
って各信号線では精度良く信号を入力又は出力すること
ができ、高精度の信号処理が実現する。This makes it possible to avoid electrical interference, which is a cause of noise, due to parasitic capacitive coupling between adjacent pads, thereby preventing the occurrence of noise in, for example, data lines whose potential fluctuates. can do. Therefore, each signal line can input or output a signal with high accuracy, and high-accuracy signal processing is realized.
【００１４】請求項３記載の発明は、請求項１又は２に
おいて、前記固定電位用のパッド又は該パッドに接続さ
れた導電性リードと、その動作用の固定電位とが、その
内部において短絡しないようになしてあることを特徴と
する。According to a third aspect of the present invention, in the first or second aspect, the fixed potential pad or a conductive lead connected to the pad and the fixed potential for operation thereof are not short-circuited inside. It is characterized by doing so.
【００１５】内部回路動作用の電源，接地等の固定電位
は、回路動作によってノイズを受けることがあるが、こ
の構成により回路動作によるノイズの影響を受けること
なく、より精度が高い信号処理を実現することができ
る。ノイズの影響を低減するには、固定電位用のパッド
と回路動作用のパッドとが短絡する位置を回路が動作し
ている場所から離すほど良く、完全に独立したものとす
ることが最も好ましい。A fixed potential such as a power supply or ground for operating the internal circuit may be affected by noise due to the circuit operation. This configuration realizes more accurate signal processing without being affected by noise due to the circuit operation. can do. In order to reduce the influence of noise, the position where the pad for fixed potential and the pad for circuit operation are short-circuited is preferably farther away from the place where the circuit is operating, and it is most preferable that the pad be completely independent.
【００１６】[0016]
【発明の実施の形態】以下、本発明をその実施の形態を
示す図面に基づき具体的に説明する。図１は本発明に係
る半導体装置の要部を示す模式図である。集積回路チッ
プ１の周縁部に、１辺 100μm の正方形のボンディング
パッド2a, 2b, 2c, 2d, 2e…が 160μm ピッチで配置さ
れている。ボンディングパッド2b, 2dは外部素子とデー
タ信号，クロック信号の送受を行うための信号入出力用
であり、ボンディングパッド2b, 2dの両側に隣接するボ
ンディングパッド2a, 2c, 2eは GND用とされている。 G
ND用のボンディングパッド2a, 2c, 2eは、集積回路チッ
プ１内において図示しない金属配線で全て短絡され回路
動作用の接地電位とは別の接地電位に固定されている。
金属配線は、配線抵抗を低減するために20μm 以上の線
幅となしてある。各ボンディングパッド2a, 2b, 2c, 2
d, 2e…は、ボンディングワイヤ３によってパッケージ
リードフレームと接続されている。ここでボンディング
ワイヤ３は物理的に交叉，短絡しないようになしてあ
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. FIG. 1 is a schematic view showing a main part of a semiconductor device according to the present invention. On the periphery of the integrated circuit chip 1, square bonding pads 2a, 2b, 2c, 2d, 2e... Having a side length of 100 μm are arranged at a pitch of 160 μm. Bonding pads 2b and 2d are used for signal input / output for transmitting and receiving data signals and clock signals to and from external elements, and bonding pads 2a, 2c and 2e adjacent to both sides of bonding pads 2b and 2d are used for GND. I have. G
The ND bonding pads 2a, 2c, and 2e are all short-circuited by metal wiring (not shown) in the integrated circuit chip 1 and are fixed to a ground potential different from the circuit operation ground potential.
The metal wiring has a line width of 20 μm or more to reduce wiring resistance. Each bonding pad 2a, 2b, 2c, 2
are connected to the package lead frame by bonding wires 3. Here, the bonding wires 3 are designed not to physically cross or short.
【００１７】図１に示すように GND用のボンディングパ
ッド2a, 2cと、データ信号用のボンディングパッド2b,
2dとが交互に配置されている場合のパッド近傍の信号線
における等価回路を図２に示す。一定電位である GND用
の信号線（ボンディングパッド2aを使用）と、データ信
号Ｓ用の信号線との間には寄生容量C1が付加され、デー
タ信号Ｓ用の信号線と、 GND用の信号線（ボンディング
パッド2cを使用）との間には寄生容量C2が付加され、 G
ND用の信号線（ボンディングパッド2cを使用）と、クロ
ック信号CLK 用の信号線との間には寄生容量C3が付加さ
れる。チップ１内で生成されたデータ信号S-0 は２つの
インバータ11, 12を経て、パッド2b及びボンディングワ
イヤ３を介してリードフレームへ伝達される。As shown in FIG. 1, bonding pads 2a and 2c for GND and bonding pads 2b and 2b for data signals are used.
FIG. 2 shows an equivalent circuit in a signal line near the pad when 2d and 2d are alternately arranged. A parasitic capacitance C1 is added between the GND signal line (using the bonding pad 2a), which is a constant potential, and the data signal S signal line, and the data signal S signal line and the GND signal A parasitic capacitance C2 is added between the wire (using the bonding pad 2c) and G
A parasitic capacitance C3 is added between the ND signal line (using the bonding pad 2c) and the clock signal CLK signal line. The data signal S-0 generated in the chip 1 is transmitted to the lead frame via the pad 2b and the bonding wire 3 via the two inverters 11 and 12.
【００１８】このときのクロック信号CLK ，データ信号
Ｓ及びデータ信号S-0 の信号波形の例を図３に示す。 G
ND用のボンディングパッド2a, 2cへ与えられる電位は原
理的に変化しない。従ってクロック信号CLK の周期がデ
ータ信号S-0 の周期より短く（1/3)、クロック信号CLK
の立ち上がりでデータ信号S-0 が立ち上がった場合、ク
ロック線の電位が“Ｈ”から“Ｌ”へ変化しても、また
“Ｌ”から“Ｈ”へ変化しても、これらの信号線の間に
存在する GND用の信号線が、ノイズの一因である、寄生
容量結合による電気的干渉を阻止する。従って従来（図
８）のようにデータ信号Ｓにノイズが発生することは回
避されている。FIG. 3 shows an example of signal waveforms of the clock signal CLK, the data signal S, and the data signal S-0 at this time. G
The potential applied to the ND bonding pads 2a and 2c does not change in principle. Therefore, the cycle of the clock signal CLK is shorter (1/3) than the cycle of the data signal S-0,
When the data signal S-0 rises at the rising edge of the signal line, even if the potential of the clock line changes from “H” to “L” or from “L” to “H”, The intervening GND signal line prevents electrical interference due to parasitic capacitive coupling, which contributes to noise. Therefore, the occurrence of noise in the data signal S as in the related art (FIG. 8) is avoided.
【００１９】本形態例では、変動電位用のパッドとし
て、データ信号用のパッド及びクロック信号用のパッド
を示しているが、他の制御信号用のパッド等、変動電位
が与えられるパッドであればよい。また、固定電位用の
パッドとして GND用のパッドを示しているが、電源用の
パッド等、原理的に一定電位が与えられるパッドであれ
ばよい。In this embodiment, pads for data signals and pads for clock signals are shown as pads for variable potential. However, any pad to which a variable potential is applied, such as another control signal pad, is used. Good. In addition, the pad for GND is shown as a pad for fixed potential, but a pad for applying a constant potential in principle, such as a power supply pad, may be used.
【００２０】また図５に示す如く、ボンディングパッド
２が２列（複数列）に、互い違いに配置されている場合
は、隣合うボンディングワイヤ３同志が変動電位用とな
らないようにボンディングパッド２を配置する。As shown in FIG. 5, when the bonding pads 2 are alternately arranged in two rows (a plurality of rows), the bonding pads 2 are arranged so that adjacent bonding wires 3 are not used for a variable potential. I do.
【００２１】[0021]
【発明の効果】以上のように本発明に係る半導体装置
は、変動電位用のパッドの両側に固定電位用のパッドを
配置することにより、隣接するパッド同志、又はパッド
と導電性リードとを接続する隣接するボンディングワイ
ヤ同志の寄生容量結合をガードすることが可能となる。
これによりノイズの一因である、動作時の互いの電気的
干渉が回避され得るので、高精度の信号処理が実現す
る。また固定電位用のパッドと回路動作用のパッドとを
半導体装置内で短絡しないように配置することにより、
回路動作によるノイズを低減することができる等、本発
明は優れた効果を奏する。As described above, in the semiconductor device according to the present invention, the pads for the fixed potential are arranged on both sides of the pads for the variable potential, so that adjacent pads or pads are connected to the conductive leads. It is possible to guard the parasitic capacitance coupling between adjacent bonding wires.
Thus, electrical interference during operation, which is a cause of noise, can be avoided, so that highly accurate signal processing is realized. Further, by arranging the pad for fixed potential and the pad for circuit operation so as not to be short-circuited in the semiconductor device,
The present invention has excellent effects, such as reduction of noise due to circuit operation.
【図１】本発明に係る半導体装置の要部を示す模式図で
ある。FIG. 1 is a schematic view showing a main part of a semiconductor device according to the present invention.
【図２】図１に示す半導体装置のパッド近傍の信号線の
等価回路図である。FIG. 2 is an equivalent circuit diagram of a signal line near a pad of the semiconductor device shown in FIG.
【図３】図１に示す半導体装置におけるクロック信号，
データ信号及びデータ信号を示す波形図である。FIG. 3 shows a clock signal in the semiconductor device shown in FIG.
FIG. 3 is a waveform diagram showing a data signal and a data signal.
【図４】従来の半導体集積装置のパッド配置を示す模式
図である。FIG. 4 is a schematic view showing a pad arrangement of a conventional semiconductor integrated device.
【図５】従来の集積回路のパッド配置を示す模式図であ
る。FIG. 5 is a schematic diagram showing a pad arrangement of a conventional integrated circuit.
【図６】図４に示す半導体集積装置の要部を示す拡大図
である。FIG. 6 is an enlarged view showing a main part of the semiconductor integrated device shown in FIG. 4;
【図７】図６に示すパッド近傍の信号線の等価回路図で
ある。FIG. 7 is an equivalent circuit diagram of a signal line near a pad shown in FIG. 6;
【図８】従来の半導体集積装置におけるクロック信号，
データ信号及びデータ信号を示す信号波形図である。FIG. 8 shows a clock signal in a conventional semiconductor integrated device,
It is a signal waveform diagram which shows a data signal and a data signal.
１ 集積回路チップ 2a, 2b, 2c, 2d, 2e ボンディングパッド ３ ボンディングワイヤ 1 integrated circuit chip 2a, 2b, 2c, 2d, 2e bonding pad 3 bonding wire
Claims (3)
半導体チップと、該パッドと電気的に接続された複数の
導電性リードとを備える半導体装置において、変動電位
用のパッドの両側に固定電位用のパッドが配置されてい
ることを特徴とする半導体装置。1. A semiconductor device comprising: a semiconductor chip having a plurality of pads provided on a peripheral portion thereof; and a plurality of conductive leads electrically connected to the pads. A semiconductor device, wherein a potential pad is arranged.
用のパッド又はクロック信号用のパッドを含み、前記固
定電位用のパッドは、接地用のパッド又は電源用のパッ
ドを含むことを特徴とする請求項１記載の半導体装置。2. The variable potential pad includes a data signal pad or a clock signal pad, and the fixed potential pad includes a ground pad or a power supply pad. The semiconductor device according to claim 1, wherein:
接続された導電性リードと、その動作用の固定電位と
が、その内部において短絡しないようになしてあること
を特徴とする請求項１又は２記載の半導体装置。3. The fixed potential pad or the conductive lead connected to the fixed potential pad and the fixed potential for operation thereof are prevented from being short-circuited in the inside thereof. Or the semiconductor device according to 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8231114A JPH1074791A (en) | 1996-08-30 | 1996-08-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8231114A JPH1074791A (en) | 1996-08-30 | 1996-08-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1074791A true JPH1074791A (en) | 1998-03-17 |
Family
ID=16918521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8231114A Pending JPH1074791A (en) | 1996-08-30 | 1996-08-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1074791A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007059884A (en) * | 2005-07-22 | 2007-03-08 | Marvell World Trade Ltd | Packaging for high-speed integrated circuit |
| KR101297192B1 (en) * | 2008-11-10 | 2013-08-19 | 삼성전자주식회사 | Image forming apparatus, chip, and chip package |
-
1996
- 1996-08-30 JP JP8231114A patent/JPH1074791A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007059884A (en) * | 2005-07-22 | 2007-03-08 | Marvell World Trade Ltd | Packaging for high-speed integrated circuit |
| KR101297192B1 (en) * | 2008-11-10 | 2013-08-19 | 삼성전자주식회사 | Image forming apparatus, chip, and chip package |
| US8884423B2 (en) | 2008-11-10 | 2014-11-11 | Samsung Electronics Co., Ltd. | Image forming apparatus, chip, and chip package |
| US9484295B2 (en) | 2008-11-10 | 2016-11-01 | Samsung Electronics Co., Ltd. | Image forming apparatus, chip, and chip package to reduce cross-talk between signals |
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