JPH1074386A - Semiconductor storage device and data processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To highly speed up access to a column system by supplying an initial address of the column system and an output address of an incrementer under a burst mode to a redundancy decision circuit in suitable timing and completing the decision of redundancy as early as possible. SOLUTION: The inrementer 51 for generating addresses of the column system in turn, a selection circuit 500 capable of fetching the initial address of the column system in the through state and selectively transmitting this and the output address of the incrementer to a circuit in the poststage, a mode decoder for forming a command decoding signal to be active when read operation or write operation is instructed and a selection control signal generating circuit 400 for transmitting the command decoding signal in the through state to the selection circuit, synchronizing this with an internal clock and holding this signal and then forming an operation control signal of the selection circuit are provided, so as to perform a selection of the initial address of the column system and the output address of the incrementer under the burst mode in suitable timing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for decoding a redundant address of a semiconductor memory device, for example, a synchronous dynamic random access memory (hereinafter abbreviated as "SDRAM") which can operate in synchronization with an external clock.
The present invention also relates to a technology that is effective when applied to a computer system including a semiconductor storage device.

[0002]

2. Description of the Related Art DRAM as an example of a semiconductor memory device
(Dynamic random access memory) includes an address buffer and a decoder as described in “LSI Handbook (pages 486-)” issued by Ohmsha on November 30, 1984. For a peripheral circuit such as a sense amplifier, a dynamic circuit that operates in synchronization with an internal clock is used. In DRAM, 1
A three-phase external clock is required, and an internal clock is generated based on these clocks to control the operation of the internal circuit. In such a DRAM, random access is mainly performed, and a row address,
Memory cells are selected by sequentially reading column addresses.

A normal DRAM performs a read / write operation asynchronously with a system clock when mounted on a system. On the other hand, an SDRAM is a semiconductor memory device operated in synchronization with a system clock. . This SDRAM can input and output data, addresses, and control signals in synchronization with the system clock.
A large-capacity memory similar to M (dynamic random access memory) can be operated at a high speed comparable to SRAM (static random access memory). On the other hand, the number of data to be accessed is specified by the burst length, and the selection state of the column system is sequentially switched by the built-in column address counter, so that a plurality of data can be read or written continuously. Such a continuous operation mode is called a burst mode.

[0004]

In a burst mode in an SDRAM, an address taken into an address counter via an input buffer or a latch circuit is used as an initial column address, and subsequent column addresses are used as column address counters ("burst addresses"). Counter). Then, the output address of the column address counter is compared with the redundant address in the redundancy judgment circuit. In this address comparison, if the addresses do not match, the output address of the predecoder is decoded by a subsequent Y-decoder (also referred to as a “column decoder”),
Y-switch (also called "column selection switch")
Is generated. In the address comparison of the redundancy judgment circuit, if the two addresses match, it means that the redundancy is being repaired, and a predetermined redundancy selection is performed instead of the normal column selection. Unless such redundancy judgment is completed, the column address decoding cannot be performed. Therefore, it is desirable to complete the redundancy judgment as soon as possible from the viewpoint of speeding up column access.

Usually, an output signal of a column address counter operated in synchronization with a clock is latched by a latch circuit,
After this latch, the output address of the latch circuit is compared with the redundant address in the redundancy judgment circuit in the subsequent stage. As a technique for starting the redundancy judgment early, the column-based initial address in the burst mode is not used. A method is considered in which the data is fetched by using the setup time of (1) and the output signal of the incrementer in the column address counter is transmitted to the redundancy judgment circuit for the address after the second.

As described above, when the setup time of the column initial address in the burst mode is used, or when the output signal of the incrementer is used, the column initial address and the address after the second generated by the incrementer are used. It is important at what timing the data is taken into the redundancy judgment circuit. Because the use of the setup time of the column-based initial address in the burst mode requires transmitting the column-based initial address to the redundancy judgment circuit at a timing faster than the internal clock for synchronizing the address latch, and This is because it is necessary to transmit the output address of the incrementer to the redundancy determination circuit by switching the address transmission path at an appropriate timing after transmitting the column-system initial address.

An object of the present invention is to supply a column initial address and an output address of an incrementer in a burst mode to a redundancy judgment circuit at an appropriate timing to complete a redundancy judgment as early as possible. It is an object of the present invention to provide a technique for speeding up system access.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, an incrementer (51) for sequentially generating a subsequent column-based address based on an externally-applied column-based initial address, and a column-based initial address supplied from outside are taken in in a through state. A selection circuit (500) capable of selectively transmitting the column-system initial address and the output address of the incrementer to a subsequent circuit; and a selection circuit arranged at a subsequent stage of the selection circuit, and an address signal selected by the selection circuit is redundant. A redundancy judgment circuit (213) for judging whether or not the address coincides with a preset redundancy address for rescue, and a command given by a combination of various signals from external terminals is taken in a through state and decoded. By doing so, while forming a control signal of the operation mode corresponding to the above command,
A mode decoder (316) for forming a command decode signal that becomes active when a read operation or a write operation is instructed by the command, and a command decode signal from the mode decoder is transmitted to the selection circuit in a through state. And a selection control signal generation circuit (400) for forming an operation control signal of the selection circuit by holding the logic state of the command decode signal in synchronization with the internal clock. Make up.

According to the above means, a command given by a combination of various signals from external terminals is taken in a through state and decoded to form a control signal of an operation mode corresponding to the command, and A command decode signal which becomes active when a read operation or a write operation is instructed by a command is formed, and the command decode signal is transmitted to a selection circuit in a through state, and the logic state of the command decode signal is synchronized with an internal clock. Forming the operation control signal of the selection circuit by holding the column address transmits the column initial address to the redundancy judgment circuit at a timing faster than the internal clock, and furthermore, the selection control signal is negated in synchronization with the internal clock. By doing so, the output address of the incrementer can be It switched to the selected state of the (second and subsequent address).

At this time, a latch for holding the output address of the selection circuit and the judgment output signal of the redundancy judgment circuit in synchronization with the internal clock in order to smoothly take in and decode the address in the column decoder. A circuit (214) may be provided so that the column system is selected based on the output signal of the latch circuit.

Further, a data processing device can be configured including the semiconductor memory device having the above configuration.

[0014]

FIG. 2 shows a computer system as an example of a data processing apparatus according to the present invention.

The computer system includes a CPU (central processing unit) 31 and an SD (SD) via a system bus BUS.
RAM 32, SRAM 33, ROM (read only
The memory 34, the peripheral device control unit 35, the display control unit 36, and the like are communicably connected to each other, and perform predetermined data processing according to a predetermined program. The CPU 31 is a logical core of the present system, and mainly includes address designation, reading and writing of information, data operation, sequence of instructions, acceptance of interrupts, activation of information exchange between a storage device and an input / output device, and the like. And has an arithmetic control unit, a bus control unit, a memory access control unit, and the like. The above SDRAM 32, SRAM 33,
The ROM 34 is positioned as an internal storage device. The SDRAM 32 is used as a work area in calculation and control by the CPU 30. The SRAM 33 functions as a cache memory or the like. The ROM 34 stores a read-only program. The peripheral device control unit 35 controls the operation of the external storage device 38 such as a hard disk, and controls the information input from the keyboard 39 and the like. The display control unit 36 controls information display on the CRT display 40. The display control unit 36 includes a semiconductor chip and an image memory for drawing processing.

FIG. 3 shows a configuration example of the SDRAM 32.

Although not particularly limited, the SDRAM 32 shown in FIG. 1 is formed on a single semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. The SDRAM 32 includes a memory array 200A forming a memory bank A and a memory array 200B forming a memory bank B. Each of the memory arrays 200A and 200B includes dynamic memory cells arranged in a matrix. The selection terminals of the memory cells arranged in the same column are coupled to a word line (not shown) for each column, and are connected to the same row. Data input / output terminals of the arranged memory cells are coupled to complementary data lines (not shown) for each row.

One word line (not shown) of the memory array 200A is driven to a selected level in accordance with a result of decoding a row address signal by the row decoder 201A. Complementary data lines (not shown) of memory array 200A are coupled to sense amplifier and column selection circuit 202A. The sense amplifier in the sense amplifier and column selection circuit 202A is an amplification circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from a memory cell. The column selection circuit in this case is a switch circuit for selecting complementary data lines individually and conducting the data to the complementary common data line 204. The column selection circuit is selectively operated according to the result of decoding the column address signal by the column decoder 203A. Similarly, the row decoder 201 is provided on the memory array 200B side.
B, a sense amplifier and column selection circuit 202B, and a column decoder 203B are provided. The complementary common data line 204 is connected to the output terminal of the input buffer 210 and the input terminal of the output buffer 211. Input buffer 210
And the output terminal of the output buffer 211 are connected to 16-bit data input / output terminals I / O0 to I / O15.

The SDRAM 32 is capable of performing a redundancy repair by a redundant configuration.
A and 200B are formed with redundant bit lines in addition to the normal bit lines.
In 03B, in addition to a normal column decoding unit for generating a normal bit line selection signal, a redundant decoding unit for generating a redundant bit line selection signal is formed. If the redundancy repair is not performed, the normal bit line is selected based on the output signal of the normal column decode unit. However, if the redundancy repair is performed, the normal bit line is selected based on the output signal of the redundant column decode unit. A redundant bit line is selected. When a redundant bit line is selected, a normal bit line is not selected.

The row address signal and the column address signal supplied from the address input terminals A0 to A11 are taken into the column address buffer 205 and the row address buffer 206 in an address multiplex format. The output of the column address buffer 205 is supplied as preset data of a column address counter 207. The column address counter 207 sequentially increments the column address signal as the preset data or the column address signal as an initial value according to the operation mode. The value obtained is input to the redundancy judgment circuit 213 and the latch circuit 21 in the subsequent stage.
Output to 4

In the redundancy judgment circuit 213, although not particularly limited, the column address output from the column address buffer 205 (initial address in burst mode)
The redundancy determination is started before the address incremented by the column address counter 207 is latched by the latch circuit 214. In other words, the input address is compared with the redundant address using the setup period when the address is latched by the latch circuit 214. In this address comparison, if the two addresses do not match, it means that the redundancy relief has not been performed for the address, and the address is incremented by the column address output from the column address buffer 205 or by the column address counter 207. The latched address is latched by the latch circuit 214 and transmitted to the column decoder 203A or 203B. However, in the address comparison by the redundancy judgment circuit 213, if both addresses match, it means that the address has been rescued by the redundancy bit, and thus the column address output from the column address buffer 205 or the column address An address for selecting a redundant bit instead of the address incremented by the address counter 207 is latched by the latch circuit 214 and transmitted to the column decoder 203A or 203B. Redundancy relief is performed by such address replacement. Here, the latch circuit 214 is used for the column address counter 207 and the redundancy repair circuit 213.
In other words, after the address comparison by the redundancy judgment circuit 213, the latch circuit 214
, The address comparison in the redundancy judgment circuit 213 can be started earlier than in a method in which an address is latched and an address judgment is made based on the latch output. By thus starting the address comparison early, the redundancy judgment circuit 21
3 is completed early, thereby speeding up column access.

The memory arrays 200A and 200B include dynamic memory cells, and it is necessary to perform a refresh operation at predetermined time intervals in order to maintain a storage state. The refresh operation is performed in the memory arrays 200A and 200A.
A refresh counter 208 is provided which is enabled by the word line selection of 00B and is capable of generating a refresh address for such a refresh operation.

The controller 212 includes, but is not limited to, a clock signal CLK and a clock enable signal CK.
E, chip select signal CS * (symbol * means that the signal attached thereto is a row enable signal), column address strobe signal CAS *, row address strobe signal RAS *, write enable signal WE *, etc. A command decode circuit 310 for generating an operation mode signal by decoding a command given by a combination of external control signals, and a timing control circuit 32 for forming an internal timing signal.
0 and a mode register 300 for holding operation mode information and test mode information.

The clock signal CLK, the clock enable signal CKE, the chip select signal CS *,
Column address strobe signal CAS *, row address strobe signal RAS *, and write enable signal W
Various control signals such as external control signals such as E *
31 via the system bus BUS. The clock signal CLK is used as a master clock of the SDRAM 32, and other external input signals are made significant in synchronization with the rising edge of the clock signal CLK. The chip select signal CS * indicates the start of a command input cycle by its low level. When the chip select signal is at a high level (chip unselected state), other signal inputs have no meaning. However, the internal operation such as the selected state of the memory bank or the burst operation is not affected by the change to the chip non-selected state. RAS *, CAS *, WE *
Are significant signals when defining a command cycle. The clock enable signal CKE is a signal indicating the validity of the next clock signal.
If KE is at a high level, the next rising edge of the clock signal CLK is made valid, and if KE is at a low level, it is made invalid. Further, although not shown, an external control signal for controlling the output enable of the output buffer 211 in the read mode is also supplied to the controller 212. When the signal is at a high level, for example, the output buffer 211 is set to a high output impedance state. .

The signal input from the address input terminal A11 is regarded as a bank selection signal in the row address strobe / bank active command cycle. That is, when the input signal from the address input terminal A11 is at a low level, the memory bank A is selected, and when it is at a high level, the memory bank B is selected. The selection control of the memory bank is not particularly limited, but only the row decoder of the selected memory bank is activated, all the column switch circuits of the unselected memory bank are not selected, the input buffer 210 and the output buffer of the selected memory bank only. 211
It can be performed by a process such as connection to.

In the precharge command cycle,
An input signal from the address input terminal A11 indicates a mode of a precharge operation for a complementary data line or the like, a high level thereof indicates that a precharge target is both memory banks, and a low level thereof indicates a state of A11. One of the designated memory banks is to be precharged.

The column address signal is supplied to A0 to A7 in a read command cycle or a write command cycle synchronized with the rising edge of the clock signal CLK.
Is defined by the logical level of Then, the column address defined in this way is used as a start address (column initial address) for burst access.

FIG. 4 shows a configuration example of the mode register 300 in the controller 212.

Although not particularly limited, the mode register 30
0 includes an operation mode register 300A and a test mode register 300B. When the mode set signal is asserted to a low level, information can be set (held). Although not particularly limited, each of the operation mode register 300A and the test mode register 300B has a 12-bit configuration. The seventh signal A7 is an enable bit, and the setting of the operation mode register 300A and the setting of the test mode register 300B are selected according to the state of the enable bit. For example, a chip select signal CS *, a row address strobe signal RAS *, a column address strobe signal CAS
When all of *, the write enable signal WE *, and the signal A7 are at the low level, setting to the operation mode register 300A is enabled. At this time, the test mode register 300B is reset. When the chip select signal CS *, the row address strobe signal RAS *, the column address strobe signal CAS *, and the write enable signal WE * are at a low level, and the signal A7 is at a high level, setting to the test mode register 300B is possible. It is said.

In the operation mode register 300A, although not particularly limited, bits 0 to 6 are set as an operation mode setting area. The operation mode information set in the operation mode setting area includes a burst length (BL), a burst type (BT), and a column address strobe signal C
A CAS latency (CL) indicating in which cycle data output is performed after AS * is asserted is included. Although not particularly limited, the burst length is up to eight types, the burst type is up to two types, and the CAS latency is up to eight types. The burst length is set in bits 0-2, the burst type is set in bit 3, and the CAS latency is set in bits 4-6. The set operation mode information is transmitted to the timing control circuit 320. This timing control circuit 320
Controls the operation of each part of the SDRAM 32 based on the operation mode information set in the operation mode register 300A.

FIG. 8 shows a configuration example of the command decode circuit 310.

Although not particularly limited, the command decode circuit 310 receives an externally applied clock CLK, a chip select signal CS *, a column address strobe signal CAS *, a row address strobe signal RAS *, and a write enable signal WE *. Input buffers 311 to 315, and inverters 318 and 3 for generating internal clock ICLK by slightly delaying the clock signal output from input buffer 311.
19, a mode decoder 316 for decoding the outputs of the input buffers 311 to 315, and a latch unit 317 for latching the output signal of the mode decoder 316 in synchronization with the internal clock ICLK. The mode signal MODE output from the latch unit 317 is used for timing generation in the timing control circuit 320 and the like.

In this example, the chip select signals CS *,
Column address strobe signal CAS *, row address strobe signal RAS *, write enable signal WE *
Are taken into the command decoder 316 in a through state, respectively. That is, the chip select signal CS
*, Column address strobe signal CAS *, row address strobe signal RAS *, write enable signal W
The command decoding is performed before each latch of E *. Therefore, the mode decoder 316
In the decoding of the command, the setup time of various signals input via the external terminal can be used, whereby the command decoding can be completed early. In other words, the setup time of a control signal supplied from the outside, such as the chip select signal CS *, the column address strobe signal CAS *, the row address strobe signal RAS *, and the write enable signal WE *, is defined by the specification. , Are taken with a predetermined margin, so that the various signals are taken into the mode decoder 316 without latching in synchronization with the clock, and
If the output signal of the mode decoder 316 is latched by the latch section 317 disposed at the subsequent stage of the mode decoder 316, the decoding can be performed as compared with the case where the signals are latched at the preceding stage of the mode decoder 316 and then decoded. , The command decode can be completed earlier.

A command decode signal MODEDEC * is formed by such a command decode. This command decode signal MODE
DEC * is a signal that is asserted to a low level when a read operation or a write operation is instructed by an external command.
07 is supplied to the selection control signal generation circuit 400 (to be described in detail later).

FIG. 1 shows the column address counter 20.
7 shows a configuration example.

As shown in FIG. 1, the column address counter 207 is not particularly limited, but includes a plurality of counter circuits 207 corresponding to the bit configuration of the column address signal.
, 207-2,..., 207-n and the selection control signal Y
Selection control signal generation circuit 40 for generating BCON *
0.

A plurality of counter circuits 207-1 and 207-
, 207-n have the same configuration. As a typical configuration example of the counter circuit 207-1 is shown, one counter circuit has a tri-state buffer 48 for taking in the address signal Y-ADD transmitted from the column address buffer 205, An inverter 50 for inverting the output logic of the buffer 48, a tri-state buffer 49 connected in parallel to the inverter 50, an inverter 47 for inverting the internal clock CCLK1, and an internal clock CCLK1 with the output values of the inverter 50 as initial values. Or an incrementer 5 for incrementing in synchronization with CCLK2
1. Tri-state buffers 53 and 54 for selecting the output signal of the incrementer 51 and the output signal of the inverter 50, and the tri-state buffers 53 and 54
And an inverter 55 for inverting the selected output signal. The inverter 50 and the tri-state buffer 49
Forms a latch circuit for latching the column address Y-ADD input via the tri-state buffer 48 in synchronization with the internal clock CCLK1. The incrementer 51 includes a counter circuit 207
-1, 207-2,..., 207-n. In the burst mode, the increment operation with an external input address as an initial value is performed as follows.
It is determined by the burst length set in the mode register 300.

The tri-state buffer 53,
The operation of the selection control signal YBCON * complements the function of the selection circuit 54 for selecting the output signal of the incrementer 51 and the output signal of the inverter 50. For example, the selection control signal YBCO
When N * is asserted to the low level, the output signal of the inverter 50 is selected by turning on the tri-state buffer 54, and the column address YA is selected.
The initial address (1st) in the DD is selectively transmitted to the redundancy determination circuit 213 and the latch 214 at the subsequent stage. At this time, tristate buffer 53 is turned off. When the selection control signal YBCON * is negated to the high level, the output signal of the incrementer 51 is selected by turning on the tristate buffer 53, and the second (2) in the burst mode is selected.
The address signals after nd) are selectively transmitted to the redundancy determination circuit 213 and the latch 214 at the subsequent stage. At this time, tristate buffer 54 is turned off. Initial address (1st) in column address Y-ADD
Is transmitted from an external terminal for inputting an address via the column address buffer 205. In the burst mode, this initial address is used as a start address for burst access. In the address transmission system from the external terminal for address input to the column address counter 207, no address latch is performed (through state). In addition, since the period during which the initial address is selected by the tristate buffer 54 is the low level period of the internal clock CCLK1, the initial address is transmitted to the tristate buffer 54 in a through state, and is further selected by the tristate buffer 54. Is transmitted to the subsequent circuit. To do so,
This is for promptly transmitting the column initial address input from the external terminal to the redundancy judgment circuit 213 to start the redundancy judgment as soon as possible.

The selection control signal generation circuit 400 for generating the selection control signal YBCON * is configured as follows.

The tri-state buffer 42 for taking in the command decode signal MODEDEC * (see FIG. 8) generated by using the setup in the command decode circuit 310, and for inverting the output signal of the tri-state buffer 42 Selection control signal generation circuit 400 including an inverter 44, a tri-state buffer 43 connected in parallel to the inverter 44, and an inverter 45 for inverting the output logic of the inverter 44.
Is formed. The operation of the tristate buffer 43 is controlled by the internal clock ICLK and a signal obtained by inverting the internal clock ICLK by the inverter 41. A latch circuit that holds the output signal of the tri-state buffer 42 is formed by a parallel connection circuit of the inverter 44 and the tri-state buffer 43. Internal clock ICL
In the low level period of K, the command decode signal MODED
EC * is taken in, and signal holding is performed during a half cycle of the internal clock ICLK, that is, during a high-level period of the internal clock ICLK. The selection control signal YBCON * thus generated is asserted to a low level only during a period (command cycle) in which a read command or a write command is externally provided, and is negated to a high level during a period other than the command cycle. You.

In a command cycle, when a read command or a write command is given from the outside, an address given almost simultaneously with the command is a column-system initial address. In this case, the selection control signal YBCON *
Is asserted to a low level, so that an address selection circuit 50 comprising tristate buffers 53 and 54 is asserted.
0 indicates the column system initial address (inverter 50).
Output address) is selectively transmitted to the subsequent circuit in a through state. When the selection control signal YBCON * is negated to a high level, the tristate buffer 53,
The output signal (the address after the second) of the incrementer 51 is selectively transmitted to the subsequent circuit by the address selection circuit 500 composed of 54.

FIG. 7 shows an example of the configuration of the incrementer 51.

As shown in FIG. 7, the incrementer 5
Reference numeral 1 denotes an increment unit 82 that performs an increment operation based on a preset value, a column-based initial address preset in the increment unit 82, and a second (second) address in a burst mode in synchronization with the internal clock CCLK1. And an increment control system 83 for generating an address after the third (third) address in the burst mode in synchronization with the internal clock CCLK2.

The increment control system 83 includes a p-channel MOS transistor 76 coupled to the high-potential-side power supply Vdd, and a p-channel M transistor
OS transistor 77, n-channel MOS transistors 79, 80, 81, inverters 71, 73, 7
4. The tri-state buffers 72 and 75 are combined. The source electrode of the n-channel MOS transistor 81 is coupled to the lower potential power supply Vss. MOS above
The transistors 76 to 81 form a tri-state buffer, and the inverter 73 is connected in anti-parallel to form a latch circuit.

The input signal of tristate buffer 72 is supplied with the output signal of inverter 50 shown in FIG. The output terminal of the increment section 82 corresponds to the output terminal of the incrementer 82. Increment part 8
2 is fed back to the tri-state buffer 75. The internal clock CCLK2 is input to the p-channel MOS transistor 78 and the tri-state buffer 75, and the signal obtained by inverting the internal clock CCLK2 by the inverter 74 is output to the n-channel MOS transistor 7
9 and the tri-state buffer 75. The internal clock CCLK1 is supplied to a p-channel MOS transistor 77 and a tri-state buffer 72, and a signal obtained by inverting the internal clock CCLK1 by an inverter 71 is output from an n-channel MOS transistor 80.
And supplied to the tristate buffer 72. When the column system initial address is input to the increment unit 82 and is preset in the increment unit 82, a second address is obtained from the output terminal of the increment unit 82. The output signal of the increment unit 82 is fed back to the tri-state buffer 75,
Address generation after the third address in the burst mode is performed in synchronization with the rising edge of the waveform of the internal clock CCLK2.

FIG. 5 shows an example of the configuration of the redundancy judgment circuit 213.

As shown in FIG. 5, the redundancy judgment circuit 213
Is a plurality of determination units 213-1 to 213-n arranged corresponding to the bit configuration of the column address, and AND for obtaining the AND logic of the output signals of the plurality of determination units 213-1 to 213-n. And a circuit 15.

The plurality of determination units 213-1 to 213-n
Have the same configuration. As a configuration example of the determination unit 213-1 is typically shown, one determination unit includes:
The clocked inverters 13 and 14 are provided, and the inverters 11 and 12 are coupled to each other to form an exclusive NOR (ENOR) for comparing one bit of the address. Thus, in the determination units 213-1 to 213-n, the column address I output from the column address counter 207 shown in FIG.
YA is compared bit-by-bit with the redundant address. Although the redundancy address is not particularly limited, it is output from a storage circuit using a fuse ROM or the like (not shown) and corresponds to a column address to be subjected to redundancy repair.
By obtaining the logical product of the output signals of the determination units 213-1 to 213-n by the AND circuit 706, it is possible to determine whether all bits of the column address and the redundant address match or not match. In this determination, for example, 1
If the logic is different even for the bits, it is determined that the addresses do not match. If the addresses do not match, the output signal of the AND circuit 15 is at a low level, and in that case, a normal bit is selected. However, in the case of an address match, the output logic of the AND circuit 15 is set to a high level, and in that case, a redundant bit is selected instead of a normal bit. When the redundant bit is selected, the normal bit is set to a non-selected state (inhibited state). The above-described bit selection based on the judgment result of the redundancy judgment circuit 213 is performed in the latch circuit 214 arranged at the subsequent stage of the redundancy judgment circuit 213.

FIG. 6 shows a configuration example of the latch circuit 214.

It comprises a plurality of 2-input NAND circuits 62-1 to 62n corresponding to the bit configuration of the column address, and an inverter 61 coupled thereto. The number of arrays of the two-input NAND circuits 62-1 to 62n corresponds to the number of output bits of the predecode logic 81. Redundancy judgment circuit 21
3 is transmitted to one of the input terminals of the two-input NAND circuits 62-1 to 62n via the inverter 61. Therefore, in the address comparison by the redundancy judgment circuit 213, the column address IYA and the redundancy are compared. If the addresses do not match, the output logic of the redundancy judgment circuit 213 is set to low level, and the 2-input NAND circuits 62-1 to 62n are activated, so that the column address IYA becomes
The data is transmitted to the normal decoders in the column decoders 203A and 203B via the subsequent latch units 63-1 to 63-n. In this case, the normal bits of the memory cell arrays 200A and 200B (see FIG. 3) are selected based on the decode output of the normal decoder.

In the address comparison by the redundancy judgment circuit 213, when the column address and the redundancy address match, the output logic of the redundancy judgment circuit 213 becomes high level, and at this time, the output logic of the inverter 61 becomes low level. Therefore, the two-input NAND circuits 62-1 to 62n are deactivated, so that the column address IYA is not transmitted to the latch units 63-1 to 63-n and the normal decoder. In this case, the high-level output of the redundancy judgment circuit 213 is output to the column decoder 203 via the latch 64 at the subsequent stage.
A, 203B, are transmitted to the redundant decoding unit, and a predetermined redundant bit selection is performed based on the output signal of the redundant decoding unit.

The latch units 63-1 to 63-n and 64 have the same configuration. As a representative configuration of latch section 63-1 is shown, one latch section includes a tri-state buffer 7 for taking in an address signal.
2, an inverter 74 for inverting the output logic of the tristate buffer 72, a tristate buffer 73 connected in parallel to the inverter 74, and an inverter 72 for inverting the column selection timing signal YSE.
And are combined. Column selection timing signal YS
The low level period of E is in a through state, and the signal is held during the high level period of the column selection timing signal YSE. The column selection timing signal YSE is a signal synchronized with the internal clock, and is generated by the controller 212.

FIG. 9 shows the operation timing of the main part of the SDRAM 32.

When a read command or a write command is externally applied and the command decode signal MODEDEC * is asserted low by the mode decoder 316, the selection control signal YBCON * is asserted low and the state is changed to the internal clock ICLK. For a high level period. When the selection control signal YBCON * is asserted to a low level, the tristate buffer 54 in the column address counter 207 is turned on, and the column initial address (1st) in the column address IYA is selected and supplied to the redundancy determination circuit 213. You. Since the column address is transmitted in a through state from the address input terminal to the redundancy judgment circuit 213 (clocking is not performed by the internal clock), the supply of the column system initial address (1st) causes the redundancy judgment circuit 213 to supply a row. The start timing of the address comparison
This is earlier than the waveform rising timing t1 of the first internal clock ICLK1 used for holding the signal in the selection control signal generation circuit 400. That is, by using the setup period, the first internal clock I
Redundancy determination can be started at a timing earlier than the waveform rising timing t1 of CLK1.

The column system initial address is incrementer 5
When it is input to 1, the second address (2nd) is generated in synchronization with the rising edge of the waveform of the internal clock CCLK1 slightly delayed from the internal clock ICLK. Second clock ICL of internal clock ICLK
Internal clock CCLK2 is generated slightly behind the rising edge timing of K2, and internal clock CCLK2 is generated.
In synchronization with the rising edge of the waveform No. 2, addresses after the third address (3rd) in the burst mode are generated. In order to accurately transmit the addresses sequentially generated by the address increment (the addresses after the second in the burst mode) to the latch circuit 214, the address selection by the address selection circuit 500 is performed by the selection control signal YBCON * as follows.

In a command cycle, when a read command or a write command is given from the outside, an address given almost simultaneously with the command is a column related initial address. In this case, the selection control signal YBCON *
Is asserted to a low level, so that an address selection circuit 50 comprising tristate buffers 53 and 54 is asserted.
0 indicates the column system initial address (inverter 50).
Is selectively transmitted to the subsequent circuit in a through state. When the selection control signal YBCON * is negated to a high level, the tri-state buffers 53 and 54
The output signal (the address after the second) of the incrementer 51 is selectively transmitted to the subsequent circuit by the address selection circuit 500 composed of.

Even after the command decode signal MODEDEC * from the mode decoder 316 is negated to the high level due to the end of the read command cycle or the write command cycle, the first internal command ICLK1 remains at the low level until the first internal command ICLK1 goes to the low level. The low level state of the selection control signal YBCON * is maintained by the selection control signal generation circuit 400. First internal command ICL
At the timing when K1 becomes low level, the selection control signal YB
CON * is negated to a high level, so that in the address selection circuit 500, the tri-state buffer 5
4, the output address of the incrementer 51 is selectively changed to the subsequent circuit (the latch circuit 214 and the redundancy judgment circuit 213) by the conduction of the tristate buffer 53.
Is transmitted to The selection control signal YBCON * is not asserted low unless a read command or a write command is input next. Therefore, until the next read command or write command is input, the output address of the incrementer 51 (address after the second in the burst mode) is selectively transmitted to the subsequent circuit by the address selection circuit 500.

As described above, the address selecting operation by the address selecting circuit 500 is performed by the command decode signal MODED.
Selection control signal YBCON * generated based on EC *
, The switching from the column-based initial address to the address after the second in the burst mode can be performed smoothly.

Then, the first internal command ICLK
1 transitions from high level to low level,
That is, the column selection timing signal YS is synchronized with the falling edge of the first internal command ICLK1.
By asserting E to a high level, the latch circuit 214 latches the column-related initial address (1st) in the burst mode. For example, when the column address and the redundant address do not match in the address comparison performed in the redundancy determination 213, the output signal of the redundancy determination circuit 213 becomes low level, and the column address IYA changes the NAND circuits 62-1 to 62-n. Through the latch units 63-1 to 63-n. But,
In the address comparison performed in the redundancy judgment 213, when the column address matches the redundancy address, the output signal of the redundancy judgment circuit 213 becomes high level, in which case the NAND circuits 62-1 to 62-n are inactive. Column state, the column address IYA is
63-n. In that case, the latch unit 64 latches the high-level signal from the redundancy determination circuit 213. A predetermined redundant bit line is selected based on the high level output of the latch circuit 213.

A third address (3rd) is generated in synchronization with the rising edge of the internal clock CCLK2 synchronized with the rising edge of the waveform of the second internal address ICLK2 in the internal address ICLK, and the waveform of the second internal address ICLK2 is generated. The second address is latched in synchronization with the falling edge. Thereby,
Redundancy determination for the second address can be started at a timing earlier than the waveform rising timing t2 of the second internal address ICLK2, and similarly, the second address can be started at a timing earlier than the waveform rising timing t3 of the third internal address ICLK3. Redundancy determination for the address can be started.

According to the above example, the following functions and effects can be obtained.

In order to start the redundancy judgment at a timing earlier than the waveform rising timing t1 of the internal clock ICLK, the selection control signal YBCON * for controlling the operation of the address selection circuit 500 is set earlier than the rising edge of the waveform of the internal clock ICLK. Must be asserted to a low level, and such a selection control signal YBC
Command decode signal MODED to generate ON *
The use of EC * is very effective. This is because the chip select signal CS * and the column address strobe signal C
Control signals supplied from the outside, such as AS *, row address strobe signal RAS *, and write enable signal WE *, have their setup times defined by specifications. The data is taken into the mode decoder 316 without latching in synchronization with the mode decoder 316.
The output signal of the mode decoder 316 is latched by a latch unit 317 disposed at the subsequent stage of the 16
This is because the start timing of decoding can be advanced as compared with the case where each of the above signals is latched and decoded before the mode decoder 316, so that command decoding can be completed earlier. Control signal YBC using command decode signal MODEDEC *, which is the decode output of
By generating ON *, the address selection circuit 500
In the above, switching between the column-based initial address (1st) input from the outside and the output address of the incrementer 51 can be performed accurately. That is, the selection control signal Y using the command decode signal MODEDEC * is used.
By generating BCON *, it is possible to transmit the column-related initial address to redundancy judgment circuit 213 at a timing earlier than the internal clock for synchronizing the address latch, and to synchronize with the falling edge of the waveform of internal clock ICLK. Then, the selection control signal YBCON * is negated to the high level, whereby the output address of the incrementer 51 (the address after the second) can be switched to the selected state at an appropriate timing.

When the setup time of the column initial address in the burst mode is used as described above, the latch section in the latch circuit 214 is controlled by the column selection timing signal YSE synchronized with the falling edge of the internal clock ICLK. 63-1 to 6-6
By controlling the operations of 3-n and 64 and latching the column address and the redundancy judgment result to determine the logic of the signal, it is possible to smoothly carry out address capture and decoding in the column decoders 203A and 203B. it can.

Although the invention made by the present inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. No.

For example, between the column address counter 207 and the latch circuit 214, the column address counter 2
A predecoder for predecoding the 07 output signal can be arranged. By doing so, the number of the NAND circuits 62-1 to 62-n and the number of the latch units 63-1 to 63-n in the latch circuit 214 can be reduced.

The SDRAM described above has a display control unit 3
6 can also be used as an image memory or the like.

In the above description, the invention made mainly by the inventor has been described in the SDR which
Although the description has been given of the case where the present invention is applied to AM, the present invention is not limited to this. The present invention is applied to a synchronous static random access memory in which memory cells are formed in a static form and can operate in synchronization with a clock. can do. Further, the present invention can be applied not only to a memory LSI, but also to a semiconductor memory device built in a single-chip microcomputer or the like.

The present invention can be applied on condition that at least a redundancy judgment circuit is included.

[0069]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a command given by a combination of various signals from external terminals is taken in a through state and decoded to form a control signal of an operation mode corresponding to the command, and a read operation or a read operation is performed by the command. A command decode signal which becomes active when a write operation is instructed is formed, and this command decode signal is transmitted to the selection circuit in a through state,
By maintaining the logic state of the command decode signal in synchronization with the internal clock to form an operation control signal for the selection circuit, the column-based initial address is transmitted to the redundancy judgment circuit at a timing earlier than the internal clock. In addition, since the selection control signal is negated in synchronization with the internal clock, the output address of the incrementer (the address after the second) can be switched to the selected state at an appropriate timing.

When the setup time of the column initial address in the burst mode is used as described above, the operation of the latch unit in the latch circuit is controlled by the column selection timing signal synchronized with the falling edge of the internal clock waveform. By controlling and latching the column address and the result of the redundancy judgment to determine the logic of the signal, it is possible to smoothly take in the address in the column decoder and decode it.

[Brief description of the drawings]

FIG. 1 is an example of a semiconductor memory device according to the present invention;
FIG. 3 is a circuit diagram illustrating a configuration example of a column address counter included in a DRAM.

FIG. 2 is a block diagram illustrating a configuration example of a computer system including the SDRAM.

FIG. 3 is a block diagram showing an overall configuration example of the SDRAM.

FIG. 4 is an explanatory diagram of a mode register included in the SDRAM.

FIG. 5 is a circuit diagram showing a configuration example of a redundancy judgment circuit in the SDRAM;

FIG. 6 is a circuit diagram showing a configuration example of a latch circuit in the SDRAM.

FIG. 7 is a circuit diagram illustrating a configuration example of an incrementer in the SDRAM.

FIG. 8 is a block diagram illustrating a configuration example of a command decode circuit in the SDRAM.

FIG. 9 is an operation timing chart of a main part of the SDRAM.

[Explanation of symbols]

 Reference Signs List 31 CPU 32 SDRAM 33 SRAM 34 ROM 35 Peripheral device control unit 36 Display control unit 38 External storage device 39 Keyboard 40 CRT display 51 Incrementer 201A, 201B Row decoder 202A, 202B Sense amplifier and column selection circuit 203A, 203B Column decoder 205 Column Address buffer 206 Row address buffer 207 Column address counter 208 Refresh counter 209 Column address register 210 Input buffer 211 Output buffer 212 Controller 213 Redundancy determination circuit 214 Latch circuit 300 Mode register 300A Operation mode register 300B Test mode register 310 Command decode circuit 316 Mode decoder 320 Timing control circuit 4 00 selection control signal generation circuit 500 address selection circuit

Claims (3)

[Claims] An incrementer for sequentially generating a subsequent column-based address based on an externally-applied column-based initial address, and an externally-applied column-based initial address are fetched in a through state. A selection circuit that can selectively transmit an initial address and an output address of the incrementer to a subsequent circuit; and an address signal that is arranged at a subsequent stage of the selection circuit and that is selected by the selection circuit. A redundancy judgment circuit for judging whether or not the address coincides with a preset redundancy address, and a command given by a combination of various signals from external terminals are taken in a through state and decoded to correspond to the above command. A control signal of the operation mode described above is formed, and a read operation or a write operation is specified by the above command. A mode decoder for forming a command decode signal that becomes active when indicated, a command decode signal from the mode decoder is transmitted to the selection circuit in a through state, and a logic state of the command decode signal is transmitted to an internal clock. And a selection control signal generation circuit for forming an operation control signal of the selection circuit by holding in synchronization with the selection circuit. 2. The selection control signal generation circuit, wherein a command decode signal from the mode decoder is transmitted to the selection circuit in a through state, and a logic state of the command decode signal is synchronized with a rising edge of a waveform of an internal clock. When the operation control signal of the selection circuit is formed by being held, the output address of the selection circuit and the judgment output signal of the redundancy judgment circuit are held in synchronization with the falling edge of the waveform of the internal clock. A semiconductor memory device provided with a latch circuit for performing a column selection based on an output signal of the latch circuit. 3. A data processing device including a central processing unit and a memory accessed by the central processing unit, wherein the semiconductor memory device according to claim 1 is applied as the memory.