JPH1074140A - Data transferring method decoding device, data transfer device, and data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely transfer inputted data and to reduce a load of a data transfer side with respect to a data transferring method and a decoding device to be used for a method. SOLUTION: This decoding device A is provided with a CPU I/F circuit 10, an FIFO buffer 20, a post processing circuit 30, a dummy data generation circuit 40, and a buffer control circuit 50. When a flash instruction indicating a completion of data input is sent from a CPU 60 to the circuit 50, dummy data are sent out of the circuit 40 and data in the buffer 20 are saturated. Therefore an FIFO reading request is sent out of the circuit 50 to the circuit 30, which executes reading.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer method and a data transfer device for transferring data and a data processing device, and more particularly to a data transfer method, a data transfer device and a data processing device for MPEG data. Things.

[0002]

2. Description of the Related Art Conventionally, data is transferred via a buffer. Here, when data is transferred from the CPU to a processing circuit that performs a decoding process, a buffer is generally provided between the processing circuit and the CPU.
That is, since the data bus width of the CPU is about 8 bits, data transfer from the CPU is usually performed in units of 8 bits each time. On the other hand, the processing circuit is designed to process data input to the processing circuit in a fixed unit at a time in order to process data at high speed and efficiently. It is necessary to transfer at high speed in units of. Therefore, between the processing circuit and the CPU,
A buffer having the above-mentioned fixed unit capacity is provided, and data transferred from the CPU is stored in units of 8 bits, and when the buffer becomes full, it is read from the processing circuit at once.

[0003]

However, data is transferred from the buffer to the processing circuit only when the amount of data in the buffer is full, so that the buffer may contain less data than the capacity of the buffer. When the data transfer from the CPU is completed, the data is not transferred to the processing circuit and the processing in the processing circuit is not performed. That is,
The total amount of transfer data transferred from the CPU may be an integral multiple of the buffer capacity, but the actual transfer data is not necessarily an integral multiple. Therefore, for example, when this processing circuit is an MPEG decoder, there arises a problem that a part or the whole of the last recorded picture cannot be decoded.
In particular, in a still image sequence, since the length of a bit stream is short, the entire sequence may not be decoded at all.

As a method for solving the above problem, it is conceivable that the CPU transfers dummy data after the data to be transferred.
Will increase the load. Further, a control circuit for controlling the processing circuit may force the processing circuit to read the data in the buffer even if the data in the buffer is not actually full, even if the data in the buffer is not actually full. However, in this method, since the data subsequent to the transfer data cannot be determined, the processing circuit may malfunction.

Accordingly, an object of the present invention is to provide a data transfer method capable of reliably transferring input data and reducing the load on the data transfer side. Is what you do.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and firstly, a buffer is interposed between a data transmitting side and a data receiving side. , Wherein dummy data is input to the buffer to saturate the data in the buffer. According to the data transfer method of the first configuration, since the data in the buffer is saturated by the dummy data, the transfer data remaining in the buffer is transferred to the receiving side by batch reading from the receiving side. Can be. Second, in the first data transfer method, dummy data is generated in the buffer when data input from a data transmission side is completed. According to the data transfer method in the second method, dummy data is generated when data input from the transmission side is completed, so that data in the buffer can be saturated after data output from the transmission side. Therefore, the transfer data remaining in the buffer can be reliably transferred to the receiving side.

Third, there is provided a decoding device for decoding image data, a processing circuit for performing a decoding process, an input unit for inputting data, and a buffer provided between the processing circuit and the input unit. And a dummy data generating circuit for generating dummy data for the buffer. In the decoding device having the third configuration, data is input from the input unit to the decoding device, and the data is sent to the processing circuit via the buffer. Here, since a dummy data generating circuit for generating dummy data is provided for the buffer, the data in the buffer becomes saturated, and the transfer data remaining in the buffer is transferred to the receiving side by batch reading by the processing circuit. can do. Therefore, the transfer data can be reliably decoded. Fourth, the third configuration is characterized in that the dummy data generation circuit generates dummy data when receiving information from the transmission side that the input has been completed. According to the decoding device of the fourth configuration, for example, dummy data is generated when data input from the transmission side is completed, and the data in the buffer may be saturated after data input from the transmission side. Therefore, the transfer data remaining in the buffer can be transferred to the receiving side. Information indicating that the input has been completed is sent, for example, from the transmission side that inputs data to the input unit.

Fifth, in the third or fourth configuration, when the data in the buffer is saturated by the dummy data, a read request is sent to the processing circuit, and the decoding device When there is free space in the storage unit provided in the circuit, reading is performed from the buffer. According to the decoding device of the fifth configuration, when the data in the buffer is saturated by the dummy data, the data is read out as soon as the memory in the processing circuit becomes available, so that the transfer data remaining in the buffer is deleted. It can be forwarded to the receiving side. Sixth, in any one of the third to fifth configurations, the image data to be transferred is MPEG-standard image data.
Therefore, it is possible to reliably decode the bit stream of the MPEG standard, and to prevent the last picture from being decoded.

Seventh, in a data transfer device for transferring data from a transmitting side to a receiving side, a buffer provided between the transmitting side and the receiving side of the data, at least data is input from the transmitting side. A buffer for transmitting the data in the buffer to the receiving side after the amount of data in the buffer reaches a predetermined amount, and a buffer for transmitting the predetermined data to the buffer from the transmitting side of the data. And a dummy data output circuit for outputting dummy data. In the data processing device having the seventh configuration, when the output of the data from the transmission side of the data to the buffer is completed, the dummy data output circuit outputs the dummy data to the buffer. That is, the dummy data is preferably added after the predetermined data. When the amount of data in the buffer reaches the predetermined amount, the buffer outputs data to the receiving side. Therefore, the data transmitted from the transmission side can be reliably transferred to the reception side. Eighthly, in the seventh configuration, the predetermined amount is a capacity of the buffer.

Ninth, in the seventh or eighth configuration, the data amount of the dummy data output to the buffer is larger than the capacity of the buffer. Therefore, the data amount of the data in the buffer can be reliably set to the predetermined amount, and the data can be reliably transferred to the receiving side. Tenth,
In the seventh or eighth configuration, the data amount of the dummy data output to the buffer is the data amount calculated from the remaining data amount in the buffer or the remaining capacity in the buffer, and The data amount is a data amount necessary for setting the data amount to the predetermined amount. Therefore, the data amount of the data in the buffer can be reliably set to the predetermined amount, and the data can be reliably transferred to the receiving side.

Eleventh, a data processing device for receiving data and performing predetermined processing is provided. An input circuit for inputting externally transmitted data, and a predetermined processing for receiving data are performed. A processing circuit for performing the processing, and a buffer provided between the input circuit and the processing circuit, wherein at least a predetermined amount of data in the buffer to which data is input from the transmission side is input to the processing circuit. And a dummy data output circuit that outputs dummy data to the buffer after the output of predetermined data from the transmitting side of the data to the buffer is completed. In this data processing device, when data is externally input to an input circuit, the data is stored in a buffer. When the amount of data in the buffer reaches a predetermined amount, the data in the buffer is transmitted to the processing circuit. Then, after the data transmission from the data transmission side to the buffer is completed, the dummy data output circuit outputs the dummy data to the buffer. That is, the dummy data is preferably added after the predetermined data. Therefore, when the amount of data in the buffer reaches a predetermined amount,
The data in the buffer is transmitted to the processing circuit. Therefore, the data transmitted from the transmission side can be reliably transferred to the reception side. In a twelfth aspect, in the eleventh configuration, the predetermined amount is a capacity of the buffer.

In the thirteenth aspect, the eleventh or twelfth
Wherein the data processing device further comprises a control circuit for transmitting a read request to the processing circuit when the data amount of the data in the buffer has reached a predetermined amount. A memory for storing data is provided. When a read request is transmitted from the control circuit, the processing circuit determines whether or not there is free space in the memory. The circuit issues an output instruction to the buffer. Therefore, the data transmitted from the transmission side can be reliably transferred to the reception side.

Fourteenth, the eleventh to thirteenth are described.
In any one of the above configurations, the data amount of the dummy data output to the buffer is larger than the capacity of the buffer. Therefore, the data amount of the data in the buffer can be reliably set to the predetermined amount, and the data can be reliably transferred to the receiving side.

Fifteenth, the eleventh to the thirteenth
In any of the above configurations, the data amount of the dummy data output to the buffer is the data amount calculated from the remaining data amount in the buffer or the remaining capacity in the buffer, and the data amount of the data in the buffer is It is characterized in that it is an amount of data necessary to make the predetermined amount. Therefore, the data amount of the data in the buffer can be reliably set to the predetermined amount, and the data can be reliably transferred to the receiving side. In each configuration described above, the predetermined data includes a bit stream. Further, the dummy data is data which is meaningless to the processing circuit and can be skipped. In MPEG1 or MPEG2, all 0 or all 1 data is desirable.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, a decoding device A according to the present invention includes a CPU I / F circuit (hereinafter, referred to as “I / F circuit”) 10, a FIFO buffer (hereinafter, referred to as “buffer”) 20, a post-stage. Processing circuit 30
, Dummy data generation circuit 40 and buffer control circuit 5
0. Note that the decryption device A includes a CPU 6
Connected to 0. This decoding device is based on the MPEG standard, for example, MPEG1 or MPEG2.
It is based on the standard.

Here, the I / F circuit 10 includes a CPU 6
0 and controls the interface between the CPU 60 and the decoding device A. That is, this I / F circuit 10
Functions as an input unit for inputting data. The buffer 20 includes the I / F circuit 10 and the post-processing circuit 3.
It is connected between 0 and functions as a shock absorber. This buffer 20 has a capacity of 256 bytes. The post-processing circuit 30 as a processing circuit includes the buffer 2
0 and functions as a main circuit of the decoder.
The post-processing circuit 30 performs batch processing in units of the amount of data input from the buffer 20.

The dummy data generating circuit 40 includes:
The dummy data is generated, and the dummy data is input to the buffer 20. This dummy data generation circuit 40
Is configured, for example, as shown in FIG.
And a processor 44. Here, the processor 44 outputs dummy data, and the counter 42 counts the dummy data output from the processor 44. The buffer control circuit 50 controls the operation of each unit of the decoding device A, and the I / F circuit 1
0, the state of the buffer 20, the post-processing circuit 30, and the dummy data generation circuit 40 are monitored, and the operation and stop instructions are given to the above components. For example, the capacity of the data in the buffer 20 is monitored, and when it is detected that the capacity in the buffer 20 is full, a read request is made to the post-processing circuit 30.

The CPU 60 inputs the bit stream data as the predetermined data to the decoding device A. It is assumed that the bit stream data is MPEG bit stream data. Data transfer is performed in units of 8 bits or 16 bits. That is,
The data bus width of the CPU 60 is in units of 8 bits or 16
Since it is a bit unit, it is transferred in the above unit. That is, the data is transferred for each 8-bit or 16-bit transmission unit data. The predetermined data is data of a certain length longer than the transmission unit data, for example, data that satisfies a predetermined format and is meaningful to the post-processing circuit 30. The I / F circuit 10, buffer 20, dummy data generation circuit 40, and buffer control circuit 50 in the decoding device A function as a data transfer device, and the decoding device A functions as a data processing device.

Next, the operation of the decoding apparatus A having the above configuration will be described. In the following description, it is assumed that the data transfer of the CPU 60 is in units of 8 bits. First, the CPU 60
Performs a handshake with the I / F circuit 10 and inputs the bit stream data to the decoding device A. CPU 60 is 8
The above data is transferred in bit units. That is, CPU
Reference numeral 60 transfers the data to the decoding device A after confirming whether there is free space in the buffer 20 via the buffer control circuit 50. That is, as shown in FIG.
At 0, it is determined whether or not there is a free space in the buffer 20 (S10).
(S11). It should be noted that the CPU 60 has a CD
-Bit stream data is transmitted from a recording medium such as a ROM or a transmission path. Then, the I / F circuit 10 includes a CPU
The data transferred from 60 is written in the buffer 20.
The data written in the buffer 20 is stored in the buffer 2
Buffered at 0.

Next, the buffer 2 is processed by the post-processing circuit 30.
The data stored in “0” is read, and MPEG decoding processing is performed. The post-processing circuit 30 is designed to collectively process the data in units of 256 bytes in order to process the data quickly and efficiently, and reads the data stored in the buffer in units of 256 bytes. That is, when the amount of data in the buffer 20 becomes full, the buffer control circuit 50 detects this fullness and outputs a FIFO read request to the post-processing circuit 30. Then, the post-stage processing circuit 30
At the time when a DRAM as a storage unit provided in 0 is vacant, a read signal is transmitted to the buffer 20, and the buffer 20 outputs 256 bytes of data in response to the read signal.

Here, the CPU 60 transmits data, that is,
When the output of the bit stream data is completed, C
The PU 60 issues a flush command to the buffer control circuit 50. Then, the buffer control circuit 50 outputs the dummy data from the dummy data generation circuit 40 by controlling the dummy data generation circuit 40. The dummy data is not data that is meaningful to the post-processing circuit 30 such as pixel data, but is readable data that is meaningless to the post-processing circuit. That is, the dummy data is data that does not adversely affect the post-processing circuit 30, and is desirably all 0 or all 1 data. The data amount of the dummy data input to the buffer 20 is equal to or larger than the capacity of the buffer 20.
That is, dummy data of 256 bytes or more is input.
Specifically, when the processor 44 outputs the dummy data, the counter 42 counts the data amount of the output dummy data, and when the count of the counter 42 reaches a predetermined number, the processor 44 outputs the dummy data. Stop.

Then, after the data transferred from the CPU 60, that is, the bit stream data, the dummy data generated by the dummy data generating circuit 40 is written into the buffer 20. That is, the dummy data is added after the bit stream data. Therefore, even if data of less than 256 bytes among the data transferred from the CPU 60 remains in the buffer 20, the buffer 20 is filled with the dummy data from the dummy data generation circuit 40. In this specification, this state is also referred to as a pseudo-saturated state. Therefore, the buffer control circuit 5
From 0, a FIFO read request is output to the post-processing circuit 30, and the reading is performed by the post-processing circuit 30. After reading the data from the buffer 20, the post-processing circuit 30 performs a decoding process and outputs a video to the outside.

FIG. 4 is a flowchart showing a method of transferring data in the decoding device A. That is, first, the buffer control circuit 50 determines whether or not a flash command has been issued from the CPU 60 (S20). When the flash command has been issued, the dummy data generation circuit 40 is controlled to generate the dummy data. The dummy data is output from the circuit 40 (S21). If no flash command has been issued in step S20, the process proceeds to step S22.

Next, it is determined whether or not the data amount in the buffer 20 is full (S22). This determination is made by the buffer control circuit 50 in accordance with information from the buffer 20. That is, it is determined whether the amount of data in the buffer 20 is equal to the capacity of the buffer 20. When the buffer is full, the buffer control circuit 50
0, a FIFO read request is output (S2
3). When the dummy data is output from the dummy data generation circuit 40, the amount of data in the buffer 20 becomes full because the dummy data having a capacity larger than the capacity of the buffer 20 is output.

Then, the post-processing circuit 30 determines whether or not the DRAM provided in the post-processing circuit 30 has a free space (S24). And transmits a read signal (S2
5), the buffer 20 outputs 256 bytes of data in response to the read signal (S26). The processing of the flowchart shown in FIG. 4 is performed when data is input from the CPU 60.

As described above, according to the decoding apparatus A of this embodiment, when the output of the data from the CPU as the data transmitting side, that is, the bit stream data is completed, the dummy data is input to the buffer 20. By making the data in the buffer 20 saturated, the CPU 6
All data transferred from 0 is transferred to the post-processing circuit 30, and the data transferred from the CPU 60 can be decoded to the end.

In the above description, the buffer 2
Although the description has been made assuming that dummy data having a capacity of 0 or more is input to the buffer 20, the present invention is not limited to this. For example, the remaining data amount of data remaining in the buffer 20 is calculated,
It is also possible to calculate the dummy data required to be 256 bytes in total by subtracting the remaining data amount from the capacity of the buffer 20, and input the dummy data of the calculated data amount. Alternatively, the remaining capacity in the buffer 20 may be calculated, and dummy data of the calculated remaining capacity may be input. Also, the I / F circuit 10 of the decoding device A
Has been described as being connected to the CPU,
Other devices may be connected. For example, the I /
When the CPU and the DMA controller are connected to the F circuit 10, the bit stream data is input from the DMA controller to the decoding device A, and the flash command is
It will be input from the PU.

In the above description, the case where dummy data is input to the buffer in the MPEG decoder has been described. However, the present invention is not limited to this. The present invention can be widely applied to the case where data transfer is performed with a buffer interposed between the data and the receiving side. Also, the decryption device A
Is not limited to the MPEG standard, and may conform to other standards. In this case, the data to be transferred is not limited to the MPEG standard but may be data of another standard.

In the above description, the buffer 20 is provided in the decoding device A, and the data is transferred to the post-processing circuit 30 via the buffer 20, but the post-processing circuit 30 performs the decoding process. It does not have to be a circuit that performs the processing, and may be a circuit that performs other processing. That is, the decoding device A may be a device that performs processing other than decoding.

In the above description, it has been described that a read request is output to the post-processing circuit 30 when the data amount in the buffer 20 is full. When the predetermined amount is reached, a read request may be output to the post-processing circuit 30.

[0031]

According to the data transfer method of the present invention, since the data in the buffer is saturated by the dummy data, the transfer data remaining in the buffer by the batch reading from the receiving side is transferred to the receiving side. Can be transferred. According to the decoding device of the present invention, since the dummy data generation circuit is provided, the data in the buffer becomes saturated, and the transfer data remaining in the buffer is transferred to the receiving side by the batch reading by the processing circuit. The transfer data can be reliably decoded. Further, according to the data transfer device of the present invention, the data transmitted from the transmitting side can be reliably transferred to the receiving side. Further, according to the data processing device based on the present invention, the data transmitted from the transmission side can be reliably transferred to the reception side.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a decoding device based on an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a dummy data generation circuit.

FIG. 3 is a flowchart illustrating an operation of a CPU.

FIG. 4 is a flowchart for explaining the operation of the decoding device.

[Explanation of symbols]

 A Decoding device 10 CPU I / F circuit 20 FIFO buffer 30 Post-stage processing circuit 40 Dummy data generation circuit 50 Buffer control circuit 60 CPU

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Anpachi Hamamoto 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd.

Claims (15)

[Claims] 1. A data transfer method for transferring data by interposing a buffer between a data transmitting side and a data receiving side, wherein dummy data is generated for the buffer, and data in the buffer is generated. A data transfer method characterized by being in a saturated state. 2. The data transfer method according to claim 1, wherein when data input from the data transmission side is completed, dummy data is generated for the buffer. 3. A decoding device for decoding image data, comprising: a processing circuit for performing a decoding process; an input unit for inputting data; a buffer provided between the processing circuit and the input unit; And a dummy data generating circuit for generating dummy data. 4. The decoding device according to claim 3, wherein the dummy data generating circuit generates dummy data when receiving information from the transmitting side that the input has been completed. 5. When the data in the buffer becomes saturated due to the dummy data, a read request is sent to the processing circuit, and the decoding device determines from the buffer that there is free space in a storage unit provided in the processing circuit. The decoding device according to claim 3, wherein reading is performed. 6. The decoding device according to claim 3, wherein the transferred image data is image data of the MPEG standard. 7. A data transfer device for transferring data from a transmission side to a reception side, comprising: a buffer provided between the transmission side and the reception side of the data; A buffer for transmitting the data in the buffer to the receiving side after the amount becomes a predetermined amount; and a dummy data for the buffer after the output of the predetermined data from the transmitting side of the data to the buffer is completed. And a dummy data output circuit for outputting the data. 8. The data transfer device according to claim 7, wherein the predetermined amount is a capacity of the buffer. 9. The data transfer device according to claim 7, wherein a data amount of the dummy data output to the buffer is equal to or larger than a capacity of the buffer. 10. The data amount of the dummy data output to the buffer is the data amount calculated from the remaining data amount in the buffer or the remaining capacity in the buffer, and the data amount of the data in the buffer is determined by the predetermined amount. 9. The data transfer device according to claim 7, wherein the data amount is a data amount necessary for obtaining a fixed amount. 11. A data processing device for receiving data and performing predetermined processing, comprising: an input circuit for inputting externally transmitted data; a processing circuit for performing predetermined processing on received data; A buffer provided between the input circuit and the processing circuit, for transmitting the data in the buffer to the processing circuit after the amount of data in the buffer to which data is input from at least the transmission side reaches a predetermined amount; And a dummy data output circuit that outputs dummy data to the buffer after output of predetermined data from the data transmission side to the buffer is completed. 12. The data processing device according to claim 11, wherein the predetermined amount is a capacity of the buffer. 13. The data processing device further includes a control circuit for transmitting a read request to the processing circuit when the data amount of the data in the buffer reaches a predetermined amount. Is provided with a memory for storing data, and when a read request is transmitted from the control circuit, the processing circuit determines whether or not there is free space in the memory. 13. The data processing device according to claim 11, wherein the processing circuit issues an output instruction to the buffer. 14. The data amount of the dummy data output to the buffer is equal to or larger than the capacity of the buffer.
A data processing device according to claim 1. 15. The data amount of the dummy data output to the buffer is the data amount calculated from the remaining data amount in the buffer or the remaining capacity in the buffer, and the data amount of the data in the buffer is determined by the predetermined amount. 12. The data amount required for quantitative determination.
14. The data processing device according to 2 or 13.