JPH1070688A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure the S/N of a low luminance object by changing a potential to a common terminal of photo diodes depending on a storage state so as to improve the S/N at a low contrast. SOLUTION: Basic cells each consisting of a photo diode (1-1, 1-2,...1-n), an amplifier 2 provided with a feedback capacitive element 3 and a reset switch 4 between its input and output, and a selector switch 5 connecting an output of the amplifier 2 to a common signal line 6 are arranged linearly, a shift register 11 is provided to sequentially close the selector switch 5 (basic cell) for each picture element sequentially (to scan) thereby obtaining a video signal from the common signal line 6. Then a maximum value and a minimum value of a stored charge during the integration operation of each picture element of a monitor circuit 12 are detected. A photo diode transition control circuit 13 controls a potential of an anode control signal line 7 connecting in common to anodes of the photo diodes 1-1, 1-2,...1-n based on the minimum output. Moreover, an integration control circuit 14 controls an integration time of a line sensor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device such as a focus detection device for a camera, which converts a subject light into an image pickup signal and performs signal processing. The present invention relates to a solid-state imaging device that can be extracted.

[0002]

2. Description of the Related Art Generally, as a focus detection device of a camera,
A phase difference method that detects two images divided and projected by an optical system using a line sensor and detects the in-focus position based on the interval between the two images, or that the contrast on the sensor is maximized during focusing Such a contrast detection method is used.

[0003] In any of these focus detection methods, the detection accuracy is good when the contrast of the subject is large, and there is no problem. However, it is difficult to increase the detection accuracy when the contrast is low. Improvement proposals for such low-contrast subjects are disclosed in JP-A-64-85480 and JP-A-2-3668.
No. 1 and the like. Next, FIG. 9 and FIG. 10 show the block configuration diagrams, and the main points will be described.

In both the configurations shown in FIGS. 9 and 10, in order to obtain a video signal (V _OS or V _video ), a plurality of photoelectric conversion elements and a maximum value (V _max ) and a circuit for detecting the minimum value (V _min ) of the accumulated signal with the smallest accumulated charge, each of which amplifies the gain by A _S times based on the minimum value,
And so as to generate an output of _{A S × (V OS -V min} ).

[0005] This _AS is the difference V _max- between the maximum value and the minimum value.
V _min (= ΔV _C) is determined by, when [Delta] V _C is large small A _S, by increasing the A _S When [Delta] V _C is small, the object is also a low contrast, was amplified contrast component A signal can be obtained, and detection accuracy in the focus detection device can be improved.

[0006]

Now, let us consider the S / N of the contrast signal component and the noise component in the above conventional example. If the difference signal between the maximum value V _max and the minimum value V _min of the accumulated signal, that is, the contrast signal component is ΔV _C , the following equation (1) is obtained. ΔV _C = V _max −V _min (1)

[0007] The accumulated charge amount with respect to the V _max signal Q
Assuming that the accumulated charge amount for the _max and V _min signals is Q _min and the equivalent capacitance for converting the signal charges to the signal voltage is C _t ,
The following equations (2) and (3) hold. Q _max = C _t · V _max (2) Q _min = C _t · V _min (3) Also, Q _max and Q Assuming that the number of charges of _min is n _max , n _min , they are expressed by the following equations (4) and (5). n _max = Q _max / q ₀ (4) n _min = Q _min / q ₀ (5) where q ₀ is a unit The amount of charge.

In the case of a low-contrast object, fluctuation of light, that is, shot noise of photons, becomes a problem as noise, and the amount thereof becomes the square root of the number of signal charges. Considering the case of low contrast, if V _max ≒ V _min , the number of noise charges is (n _max ) ^1/2 . When this is converted as noise voltage V _n, it is expressed by the following equation (6). V _n = (n _max ) ^1/2 · q ₀ / C _t = (V _max · q ₀ / C _t ) ^1/2 (6) Therefore, S / N is calculated by the following equation (7) ). ΔV _C / V _n = (C _t ) ^1/2 × (V _max −V _min ) / (V _max · q ₀ ) ^1/2 (7) And the following equation (8). ΔV _C / V _n = (Q _max −Q _min ) / (Q _max · q ₀ ) ^1/2 (8)

As can be seen from the above equations (7) and (8),
To increase the S / N at low contrast, it is necessary to increase the accumulated charge amount, so that the amount of accumulated charge is not saturated is the maximum value V _max of the largest accumulation signal, in order to increase the accumulated charge amount In this case, _Ct, that is, the equivalent capacitance value of the charge-voltage conversion for converting the signal charge into the signal voltage must be increased. However, increasing C _t means lowering the signal output per unit signal charge amount, that is, lowering the sensitivity. Therefore, if C _t is increased, it is difficult to secure S / N for a low-luminance subject. Become.

Further, as shown in the conventional example, A _S
Amplifying to × (V _OS −V _min ) is effective when the S / N is determined by an A / D converter or the like at the subsequent stage of the output signal, but the S / N is determined by the shot noise of the photon. In this case, no matter how much the signal is amplified, the S / N is the same and there is no effect.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the conventional solid-state imaging device. The present invention increases the number of accumulated charges without lowering the sensitivity and increases the S / N at low contrast. It is a first object of the present invention to provide a solid-state imaging device capable of ensuring an S / N ratio for a low-luminance subject, which corresponds to the first object of the present invention. Further, according to the present invention, in a solid-state imaging device which achieves the first object, a second object is to further effectively use a signal range and to easily control an accumulation time.
The purpose of. This corresponds to the object of the present invention. A third object of the present invention is to further obtain an OB (optical black: light-shielded pixel) clamp output in the solid-state imaging device which achieves the first object. This corresponds to the object of the present invention.

[0012]

According to a first aspect of the present invention, a second conductive type diffusion layer formed on a first conductive type substrate is connected to a common first terminal. And a plurality of photoelectric conversion elements each having a plurality of first conductivity type diffusion layers formed on the second conductivity type diffusion layer as a second terminal, and corresponding to accumulated signal charges of the plurality of photoelectric conversion elements. Monitoring means for detecting the accumulation state of accumulated signal charges of the plurality of photoelectric conversion elements in a solid-state imaging device provided with scanning means for sequentially reading the output in series on the same substrate; A control circuit for changing a potential of a common first terminal of the plurality of photoelectric conversion elements based on a detection signal.

In the solid-state imaging device having such a configuration,
By changing the potential of the common first terminal of the plurality of photoelectric conversion elements, it is possible to increase the accumulated charge amount without lowering the sensitivity, and to improve the S / N for a low-contrast subject. it can.

According to a second aspect of the present invention, in the solid-state imaging device according to the first aspect of the present invention, the monitor means includes: A maximum detection circuit that detects the largest maximum value, a minimum detection circuit that detects the smallest minimum value of the charge stored in each of the photoelectric conversion elements, and an average that detects the average signal charge storage state of each of the photoelectric conversion elements. Any two circuits of the detection circuit are provided, and the control circuit changes the potential of the common first terminal of each of the photoelectric conversion elements so that the value of any one of the two circuits is maintained at a constant reference value. It is configured to be controlled. This makes it possible to use the signal range effectively and to easily control the accumulation time.

According to a ninth aspect of the present invention, in the solid-state imaging device according to the first aspect, a part of the plurality of photoelectric conversion elements is in a light-shielding state, and The monitor means includes a circuit for detecting an average value of the accumulated signal charges of the photoelectric conversion element in the light-shielded state, and the control circuit holds the average value of the accumulated signal charges of the photoelectric conversion element in the light-shielded state at a constant reference value. Thus, the configuration is such that the potential of the common first terminal of each of the photoelectric conversion elements is controlled. With this configuration, it is possible to obtain an OB clamp output.

[0016]

Next, an embodiment will be described. FIG. 1 is a circuit diagram showing a first embodiment of the solid-state imaging device according to the present invention. In this embodiment, the present invention is applied to a line sensor in which a capacitive feedback amplifier is provided for each basic cell to be a pixel. Each basic cell in the present embodiment includes photodiodes 1-1, 1-2,
.. 1-n, an amplifier 2 provided with a feedback capacitance element 3 and a reset switch 4 between input and output, and a selection switch 5 for connecting the output of the amplifier 2 to a common signal line 6. Note that 1 'is a parasitic capacitance of the photodiode.
By arranging the basic cells having such a configuration in a one-dimensional manner, providing a shift register 11 and sequentially turning on, ie, scanning, the selection switches 5 of the respective pixels (basic cells), a video signal is obtained from the common signal line 6. It has become.

Each of the above components is a basic component of the line sensor. In the present invention, in addition to the above components, the maximum value and the minimum value of the accumulated charge during the integration operation of each pixel are detected. A monitor circuit 12 is provided, and based on the output of the minimum value detected by the monitor circuit 12,
A photodiode potential control circuit 13 for controlling the potential of an anode control signal line 7 commonly connected to the anodes of the photodiodes 1-1, 1-2,... 1-n is provided. Is provided with an integral control circuit 14 for controlling the control.

Next, the structure of the photodiodes 1-1, 1-2,... 1-n constituting each basic cell will be described with reference to FIG. Each photodiode has a p-well diffusion layer 102 formed on an n-substrate 101 as an anode, and n ⁺ diffusion layers 103-1, 103-2,.
It has a structure in which n is a cathode. Here, the n ⁺ diffusion layers 103-1, 103-2, ..., 103-n correspond to the photodiodes 1-1, 1-2, ..., 1-n shown in FIG. n ⁺ diffusion layer 103-1 and 103-2, · · · 103-n is separated by a thick oxide film (LOCOS) 104, to form a cathode electrode of the independent corresponding to each pixel. On the other hand, the p-well diffusion layer 102 serving as the anode is common, and the p ⁺ diffusion layer 10 formed on the p-well diffusion layer 102 is formed.
5, the potential V _PD is applied.
This potential V _PD is the output voltage of the photodiode voltage control circuit 13 in FIG.

Next, the principle of improving the S / N at low contrast in the solid-state imaging device according to the first embodiment configured as described above will be described along with the operation. FIG.
, The capacitance value of the feedback capacitance element 3 is C _t , the value of the parasitic capacitance 1 ′ of the photodiode is C _pd , the photocurrent generated by the photodiode of the pixel with the largest incident light is I _max , and the minimum photocurrent is _Let it be I _min . Here, the feedback capacitance element 3 is reset by turning on the reset switch 4 in each pixel in FIG. 1, and integration is started when the reset switch 4 is turned off. Assuming that the initial value of each pixel voltage at the start of integration is V ₀ , the maximum value V _max and the minimum value V
_min is represented by the following equations (9) and (10). Here, t is the integration time, ΔV _PD is the common anode potential V of the photodiode.
_This is the amount of change in _PD . _{V max = V 0 + I max} · t / C t -ΔV PD · C pd / C t ····· (9) V min = V 0 + I min · t / C t -ΔV PD · C pd / C t ..... (10) the contrast signal [Delta] V _C is expressed by the following equation (11). ΔV _C = (I _max −I _min ) · t / C _t (11)

In a conventional solid-state imaging device, ΔV _PD =
0. Figure 3 shows the change of the maximum value V _max and the minimum value V _min for the integral time at that time. In FIG.
_sat indicates the saturation voltage. As can be seen from FIG.
It is necessary to terminate the integration before the time t ₀ when the maximum value V _max reaches the saturation voltage V _sat . In contrast, FIG.
The common anode potential V is set so that the minimum value V _min is always V ₀ by the photodiode voltage control circuit 13 shown in FIG.
Figure 4 shows the change in the output of the maximum value V _max and the minimum value V _min for the integral time when changing the _PD. Minimum value V
_In order to keep _min constant at the initial value V ₀ at the start of integration,
The change amount ΔV _PD of the common anode potential may be increased as shown by the following equation (12). ΔV _PD = I _min · t / C _pd (12)

As described above, by changing the common anode potential V _PD , as shown in FIG. 4, the contrast signal ΔV _C at the time t ₀ matches the ΔV _C in FIG. 3, but the output is not saturated. The integration can be continued until time t ₁ when this ΔV _C reaches the saturation voltage V _sat . Therefore, the amount of accumulated charges can be increased, and the S / N for photon shot noise is improved. At this time, the sensitivity to the contrast signal component does not change.

Next, a description will be given of an example of calculating the S / N with specific numerical values. To simplify the calculation, I _min =
3/4 · I _max, and V _sat = 5 · V _0. ΔV _PD = 0
The time t _{0 at} which V _max reaches V _sat in the case of is represented by the following expression (13) from the expression (9). t ₀ = 4 · V ₀ · C _t / I _max (13) At this time, the accumulated signal charge Q _max1 and the contrast signal charge ΔQ _C1 are given by the following equation (14). , (15). _{Q max1 = I max · t 0} = 4 · V 0 · C t ········· (14) ΔQ C1 = (I max -I min) · t 0 = V 0 · C t ··· (15) When the noise signal charge Q _n1 is obtained from the above equation (14), it is expressed as the following equation (16). _{Q n1 = q 0 · (Q} max1 / q 0) 1/2 = 2 · (V 0 · C t · q 0) 1/2 ······· (16) above (15), (16) From the equation, S / N when ΔV _PD = 0
Is represented by the following equation (17). S / N (ΔV _PD = 0) = ΔQ _C1 / Q _n1 == １ ／ · (V ₀ · C _t / q ₀ ) ^1/2 (17)

Next, S / N when ΔV _PD is controlled to be variable is determined. The integration time t _{1 at} which the maximum value V _max reaches the saturation voltage V _sat is determined by the contrast signal ΔV _C being (V
_(sat− V ₀ ), and is represented by the following equation (18) from the above equation (11). t ₁ = (V _sat −V ₀ ) · C _t / (I _max −I _min ) = 16 · V ₀ · C _t / I _max (18) At this time, the accumulated charge amount Q _max2 and the contrast signal charge ΔQ _C2 are represented by the following equations (19) and (20). Q _max2 = I _max · t ₁ = 16 · V ₀ · C _t (19) ΔQ _C2 = (I _max -I _min ) t ₁ = 4 · V ₀ · C _t (20) When the noise signal charge Q _n2 is obtained from the above equation (19), it is expressed as the following equation (21). _{Q n2 = q 0 · (Q} max2 / q 0) 1/2 = 4 · (V 0 · C t · q 0) 1/2 ······· (21) above (20), (21) From the equation, the S / N when the V _{PD is} variable is expressed as the following equation (22). S / N (V _PD variable) = ΔQ _C2 / Q _n2 = (V ₀ · C _t / q ₀ ) ^1/2 (22)

Here, comparing the expressions (17) and (22),
It can be seen that when V _PD is variable, twice the S / N is obtained when ΔV _PD = 0, that is, when V _PD is constant. Comparing Expressions (13) and (18), it can be seen that t ₁ is four times t _{0 for} the integration times t ₀ and t ₁ . Therefore, by making V _PD variable, the integration time can be quadrupled, that is, the accumulated charge amount can be quadrupled, indicating that S / N has been improved twice.

As described above, when the contrast signal component is smaller than the signal component, in the conventional solid-state imaging device, integration can be performed only until the maximum signal component reaches the saturation voltage. Can reach a saturation voltage, the integration time can be extended. As a result, the amount of accumulated charge increases, and the S / N of photons against shot noise can be improved.

In FIG. 4, the minimum value V of the stored charge signal is shown.
_Although the example in which the common anode potential V _PD of the photodiodes is controlled so that _min is constant, V _PD may be controlled such that the maximum value V _max of the accumulated charge signal is constant. FIG. 5 shows the output with respect to the integration time when V _PD is controlled so that the maximum value V _max is constant. As shown in FIG. 5, the initial voltage value V ₀ at the start of integration is reduced. When the saturation voltage is close to the saturation voltage V _sat , the signal range can be more effectively used by _keeping the maximum value V _max constant.

When the initial value V ₀ at the start of the integration is almost at the intermediate potential, as shown in FIG. 6, the average value of the maximum value and the minimum value, that is, (V _max + V _min ) / 2, always starts the integration. It is effective to control so as to be the initial value V ₀ at the time.

Next, a specific configuration example of the monitor circuit 12 and the photodiode voltage control circuit 13 will be described.
As a monitor circuit, the present inventor has previously filed Japanese Patent Application No. 8-97.
By using the peak detection circuit disclosed in Japanese Patent 307 can be configured V _max, the V _min detection circuit. FIG. 7 shows the circuit configuration. In FIG. 7, reference numeral 20 denotes a sensor array, and the output of each pixel of the sensor array 20 is n
Gates and pMO of MOS transistors 21-1 to 21-n
The drains of the nMOS transistor and the pMOS transistor are connected to the power supply _VDD or the ground, the sources are commonly connected to the signal line, and the source signal lines are connected to the S transistor 22-1 to 22-n. Is connected to a resistance load 23 or 24. Note that the nMOS transistors 21-1 to 21-n having the follower configuration and the pMOS
The transistors 22-1 to 22-n are formed with a common well serving as a back gate.

Each of the common source signal lines is a differential amplifier.
Connected to the non-inverting input terminals of the differential amplifiers 25 and 26
The gate between the output terminal and the inverting input terminal
Source-follower transistors 27 and 28 are connected to the output terminals 25 and 26, the drain is connected to the power supply _VDD or ground, and the source is connected to the resistive load 29 or 30 and connected to the inverting input terminal. Have been.

[0030] By using the V _max, V _min detecting circuit having such a configuration, it is possible to accurately detect the maximum value and the minimum value, then, the operation is described. The signal voltage of the common source signal line V _min side and V _max
On the other hand, _{assuming that} V _{i1 (+)} and V _{i2 (+)} respectively,
3), (24). _{V i1 (+) = k 1} v smin -V gsn ··············· (23) V i2 (+) = k 2 v smax + V gsp ······· (24) Here, v _smin and v _smax are the minimum and maximum values of the signal voltage of the sensor being integrated, and k ₁ and k ₂ are the gains due to the _body effect of the nMOS transistor and the pMOS transistor. It usually takes a value of about 0.6 to 0.9, depending on the process. V _gsn and V _gsp are nMOS
The voltage between the gate and the source of the transistor and the pMOS transistor. This value is not a constant since it varies with the voltage of the common signal line of the source due to the body effect.

A transistor having a source follower configuration
The input voltages to the transistors 27 and 28, that is, V _min and V _max are the output voltages of the transistors 27 and 28 in this source follower configuration,
That is, the voltage of the inverting input terminals of the differential amplifiers 25 and 26 is set to V
_{Assuming that i1 (−)} and V _{i2 (−)} , they are expressed by the following equations (25) and (26). _{V i1 (-) = k 1} V min -V gsn '·············· (25) V i2 (-) = k 2 V max -V gsp' ····· (26) Here, k ₁ and k ₂ are gain reductions due to the _body effect of the transistors 27 and 28 having the source follower configuration, and V _gsn ′,
V _gsp ′ is a gate-source voltage of the transistors 27 and 28 having a source follower configuration. Incidentally, k _1, k ₂ is the value determined by the process, the (23), and k _1, k ₂ of (24), if it is formed on the same substrate have the same value.

Assuming that the gains of the differential amplifiers 25 and 26 are large and the offset voltage is zero, V _{i1 (+)} =
Since V _{i1 (−)} and V _{i2 (+)} = V _{i2 (−)} hold, the following equations (27) and (28) hold. _{V min = v smin - (V} gsn -V gsn ') / k 1 ········ (27) V max = v smax + (V gsp -V gsp') / k 2 ····· (28) As can be seen from the above equation (27), the nMOS transistor
Gate-source voltage V _{gsn of} 21-1 to 21-n and nMO
By determining the load resistances 23 and 29 so that the gate-source voltage V _gsn ′ of the S transistor 27 becomes equal,
V _min = v _smin, and the smallest integral output in the sensor pixel from V _min signal output terminal (maximum voltage) appears. this is,
This shows that a voltage value without adding an offset or reducing the gain can be obtained with respect to the voltage being integrated by the pixel.

As can be seen from equation (28), pMO
And S transistors 22-1 to 22-n of the gate-source voltage V _gsp, as the voltage V _gsp 'between the gate and source of the pMOS transistor 28 are equal, by determining the load resistor 24, 30, V _max = V _smax , and a maximum integrated output (minimum voltage) is obtained from the V _max signal output terminal without being affected by the addition of an offset or a decrease in gain.

FIG. 8 is a diagram showing a configuration example of a photodiode voltage control circuit. In this configuration example, V ₀ which is an initial value and a reference value immediately after resetting of a pixel is applied to a non-inverting input terminal.
And a differential amplifier 31 having a minimum value _Vmin input to an inverting input terminal, and an output terminal of the differential amplifier 31 is connected to an inverting input terminal of a differential amplifier 36 via a capacitor 33. . A reset switch 34 and a feedback capacitor 35 are provided between the inverting input terminal and the output terminal of the differential amplifier 36, and the output terminal is connected to the anode terminal (V _PD ) of the photodiode. . A non-inverting input terminal of the differential amplifier 36 is supplied with an initial value V _PD0 of the anode potential of the photodiode. Note that a capacitor 32 is provided between the non-inverting input terminal and the output terminal of the differential amplifier 31, and is a phase compensation capacitor for suppressing system oscillation.

In the photodiode voltage control circuit configured as described above, when the reset switch 34 is turned on at the time of resetting, the _VPD output becomes the initial value _VPD0 . Then, when the reset switch 34 is turned off at the same time as the integration of the sensor is started, when a difference between V ₀ and V _min appears at the inverting input terminal of the differential amplifier 36, the V _PD output is changed to change V _min and V _0.
The feedback is applied so that the numbers match. Therefore, by using the photodiode voltage control circuit having such a configuration, V _PD can be changed so that V _min always becomes V ₀ .

[0036] The monitor circuit showed that constituted by the maximum value V _max and the minimum value V _min detection circuit may be configured by providing a circuit for detecting an average output V _ave of the other sensor. In that case, any two detection circuits of V _max , V _min , and V _ave are used, the output of one of the detection circuits is used as the input of the photodiode voltage control circuit, and the output of the other detection circuit is used as the input of the integration control circuit. do it. The output of each detection circuit may be selected according to the configuration of each pixel (basic cell) of the sensor, the nature of the subject, and the purpose of use of the sensor. Note that the above monitor circuit is connected to V _max and V _ave
The detection circuit or that may be composed of a detection circuit of the V _min and V _ave, of course.

Next, an application example of the solid-state imaging device according to the present invention will be described. The monitor circuit according to the embodiment of the present invention is configured by a circuit that detects the maximum, minimum, or average of the accumulated charge signal of the effective pixel to which light enters, but does not allow light to enter a part of the sensor pixel. The output of the light-shielded pixel is input to a monitor circuit, and the monitor circuit is provided with an average value detection circuit to output the average value of the light-shielded pixel output, thereby obtaining an equivalently OB clamped signal. be able to. That is, normally, the output of the light-shielded pixel changes due to dark current of the element even when light does not enter. Controlling the photodiode potential so that the output of the light-shielded pixel does not change is nothing more than subtracting and outputting a dark current component generated in an effective pixel.
Therefore, by adopting such a configuration, OB clamping is equivalently performed.

[0038]

As described above with reference to the embodiments, according to the first to eighth aspects of the present invention, the S / N of a low-contrast subject is increased by increasing the number of accumulated charges without lowering the sensitivity. It is possible to realize a solid-state imaging device that can improve the S / N for a low-luminance subject while improving the S / N ratio. According to the second to eighth aspects of the present invention, it is possible to effectively use the signal range and to easily control the accumulation time. According to the ninth aspect of the present invention,
An OB clamp output can be easily obtained.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram illustrating an embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a schematic sectional view showing a configuration of a photodiode part in the embodiment shown in FIG.

FIG. 3 is a diagram illustrating a change in a maximum value and a minimum value of a stored charge signal with respect to a storage time in a conventional solid-state imaging device.

FIG. 4 is a diagram illustrating an example of a change in a maximum value and a minimum value of a stored charge signal with respect to a storage time in the embodiment illustrated in FIG. 1;

FIG. 5 is a diagram showing another example of a change in the maximum value and the minimum value of the stored charge signal with respect to the storage time in the embodiment shown in FIG.

6 is a diagram showing still another example of a change in the maximum value and the minimum value of the stored charge signal with respect to the storage time in the embodiment shown in FIG.

FIG. 7 is a circuit configuration diagram showing a configuration example of a monitor circuit in the embodiment shown in FIG. 1;

FIG. 8 is a circuit configuration diagram showing a configuration example of a photodiode voltage control circuit in the embodiment shown in FIG. 1;

FIG. 9 is a diagram illustrating a configuration example of a conventional solid-state imaging device in which an improvement measure for a low-contrast subject is taken.

FIG. 10 is a diagram illustrating another configuration example of a conventional solid-state imaging device in which an improvement measure for a low-contrast subject is taken.

[Explanation of symbols]

1-1, 1-2,... 1-n photodiode 2 amplifier 3 feedback capacitance element 4 reset switch 5 selection switch 6 common signal line 7 anode control signal line 11 shift register 12 monitor circuit 13 photodiode voltage control circuit 14 Integration control circuit 20 Sensor array 21-1, 21-2,..., 21-n NMOS transistor 22-1, 22-2,..., 22-p PMOS transistor 23, 24, 29, 30 Resistive load 25, 26 Differential amplifier 27,28 Source follower transistor 31,36 Differential amplifier 32 Phase compensation capacitance 33 Capacitance 34 Reset switch 35 Feedback capacitance 101 n substrate 102 p-well diffusion layer 103-1,103-2, ... 103 -n n ⁺ diffusion layer 104 oxide film (LOCOS) 105 p ⁺ diffusion layer

Claims (9)

[Claims] 1. A plurality of first conductivity type diffusion layers formed on a second conductivity type diffusion layer, the second conductivity type diffusion layer formed on a first conductivity type substrate serving as a common first terminal. A solid-state imaging device provided with a plurality of photoelectric conversion elements each having a second terminal and scanning means for sequentially reading out outputs corresponding to accumulated signal charges of the plurality of photoelectric conversion elements in series on the same substrate And monitor means for detecting an accumulation state of accumulated signal charges of the plurality of photoelectric conversion elements, and changing a potential of a common first terminal of the plurality of photoelectric conversion elements based on a detection signal of the monitor means. A solid-state imaging device comprising a control circuit. 2. A monitor according to claim 1, wherein said monitor means comprises: a maximum detection circuit for detecting a maximum value of the stored signal charges of said photoelectric conversion elements; and a minimum detection circuit for detecting a minimum value of said stored signal charges. The solid-state imaging device according to claim 1, further comprising: 3. The monitor means detects an average signal charge accumulation state of each of the photoelectric conversion elements, and detects a smallest minimum value of the accumulated signal charges of each of the photoelectric conversion elements. The solid-state imaging device according to claim 1, further comprising a minimum detection circuit. 4. An average detection circuit for detecting an average signal charge accumulation state of each of the photoelectric conversion elements, and a maximum value among the accumulated signal charges of each of the photoelectric conversion elements. The solid-state imaging device according to claim 1, further comprising a maximum detection circuit. 5. A control circuit according to claim 1, wherein said control circuit controls a potential of a common first terminal of each of said photoelectric conversion elements such that a smallest minimum value among the accumulated signal charges of each of said photoelectric conversion elements is maintained at a fixed reference value. The solid-state imaging device according to any one of claims 1 to 3, wherein the solid-state imaging device is configured to control the following. 6. The control circuit controls a potential of a common first terminal of each of the photoelectric conversion elements such that an average value of accumulated signal charges of each of the photoelectric conversion elements is maintained at a constant reference value. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is configured as follows. 7. The control circuit according to claim 1, wherein a maximum value of the signal charges stored in each of said photoelectric conversion elements is maintained at a constant reference value. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is configured to control the following. 8. The control circuit controls each of the photoelectric conversion elements such that an average value of the largest maximum value and the smallest minimum value among the accumulated signal charges of each photoelectric conversion element is held at a constant reference value. The solid-state imaging device according to claim 1, wherein the potential of the common first terminal is controlled. 9. A part of the plurality of photoelectric conversion elements is in a light-shielded state, and the monitoring means includes a circuit for detecting an average value of accumulated signal charges of the photoelectric conversion elements in the light-shielded state,
The control circuit is configured to control a potential of a common first terminal of each of the photoelectric conversion elements so that an average value of accumulated signal charges of the photoelectric conversion elements in the light-shielded state is maintained at a constant reference value. The solid-state imaging device according to claim 1, wherein