JPH1069457A - 多数のアービタを有するコンピュータ・システムにおいて分散仲裁を処理するための回路 - Google Patents

多数のアービタを有するコンピュータ・システムにおいて分散仲裁を処理するための回路

Info

Publication number
JPH1069457A
JPH1069457A JP9196143A JP19614397A JPH1069457A JP H1069457 A JPH1069457 A JP H1069457A JP 9196143 A JP9196143 A JP 9196143A JP 19614397 A JP19614397 A JP 19614397A JP H1069457 A JPH1069457 A JP H1069457A
Authority
JP
Japan
Prior art keywords
bus
arbiter
signal
pci
computer system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP9196143A
Other languages
English (en)
Japanese (ja)
Other versions
JPH1069457A5 (enExample
Inventor
Dwight D Riley
ドワイト・ディー・リリー
James R Edwards
ジェームズ・アール・エドワーズ
David J Maguire
デーヴィッド・ジェイ・マグイリ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Publication of JPH1069457A publication Critical patent/JPH1069457A/ja
Publication of JPH1069457A5 publication Critical patent/JPH1069457A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP9196143A 1996-07-19 1997-07-22 多数のアービタを有するコンピュータ・システムにおいて分散仲裁を処理するための回路 Withdrawn JPH1069457A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US684412 1996-07-19
US08/684,412 US5954809A (en) 1996-07-19 1996-07-19 Circuit for handling distributed arbitration in a computer system having multiple arbiters

Publications (2)

Publication Number Publication Date
JPH1069457A true JPH1069457A (ja) 1998-03-10
JPH1069457A5 JPH1069457A5 (enExample) 2005-04-07

Family

ID=24747943

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9196143A Withdrawn JPH1069457A (ja) 1996-07-19 1997-07-22 多数のアービタを有するコンピュータ・システムにおいて分散仲裁を処理するための回路

Country Status (5)

Country Link
US (1) US5954809A (enExample)
EP (1) EP0820018A3 (enExample)
JP (1) JPH1069457A (enExample)
SG (1) SG65663A1 (enExample)
TW (1) TW336296B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001202327A (ja) * 2000-01-20 2001-07-27 Fujitsu Ltd バス使用効率を高めた集積回路装置のバス制御方式

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US6212590B1 (en) * 1997-12-22 2001-04-03 Compaq Computer Corporation Computer system having integrated bus bridge design with delayed transaction arbitration mechanism employed within laptop computer docked to expansion base
US6397279B1 (en) * 1998-01-07 2002-05-28 Vlsi Technology, Inc. Smart retry system that reduces wasted bus transactions associated with master retries
US6185520B1 (en) * 1998-05-22 2001-02-06 3Com Corporation Method and system for bus switching data transfers
US6209053B1 (en) * 1998-08-28 2001-03-27 Intel Corporation Method and apparatus for operating an adaptive multiplexed address and data bus within a computer system
US6570982B1 (en) * 1998-08-28 2003-05-27 Teltronics, Inc. Digital clocking synchronizing mechanism
US6523076B1 (en) * 1999-11-08 2003-02-18 International Business Machines Corporation Method and apparatus for synchronizing multiple bus arbiters on separate chips to give simultaneous grants for the purpose of breaking livelocks
US6460109B1 (en) 1999-12-16 2002-10-01 International Business Machines Corporation Integral portable computer input and output switching
US6571306B1 (en) * 2000-02-09 2003-05-27 Sun Microsystems, Inc. Bus request mechanism for bus master which is parked on a shared bus
US6874039B2 (en) * 2000-09-08 2005-03-29 Intel Corporation Method and apparatus for distributed direct memory access for systems on chip
US6877055B2 (en) 2001-03-19 2005-04-05 Sun Microsystems, Inc. Method and apparatus for efficiently broadcasting transactions between a first address repeater and a second address repeater
US6889343B2 (en) 2001-03-19 2005-05-03 Sun Microsystems, Inc. Method and apparatus for verifying consistency between a first address repeater and a second address repeater
US6735654B2 (en) * 2001-03-19 2004-05-11 Sun Microsystems, Inc. Method and apparatus for efficiently broadcasting transactions between an address repeater and a client
US6826643B2 (en) 2001-03-19 2004-11-30 Sun Microsystems, Inc. Method of synchronizing arbiters within a hierarchical computer system
US20020133652A1 (en) * 2001-03-19 2002-09-19 Tai Quan Apparatus for avoiding starvation in hierarchical computer systems that prioritize transactions
US6950893B2 (en) * 2001-03-22 2005-09-27 I-Bus Corporation Hybrid switching architecture
US6970986B1 (en) * 2002-05-21 2005-11-29 Adaptec, Inc. Software based system and method for I/O chip hiding of processor based controllers from operating system
US20040059862A1 (en) * 2002-09-24 2004-03-25 I-Bus Corporation Method and apparatus for providing redundant bus control
US7533195B2 (en) * 2004-02-25 2009-05-12 Analog Devices, Inc. DMA controller for digital signal processors
US8291145B2 (en) 2004-08-10 2012-10-16 Hewlett-Packard Development Company, L.P. Method and apparatus for setting a primary port on a PCI bridge
US20090037635A1 (en) * 2006-03-17 2009-02-05 Shanghai Magima Digital Information Co., Ltd. Bus arbitration device
US8095700B2 (en) * 2009-05-15 2012-01-10 Lsi Corporation Controller and method for statistical allocation of multichannel direct memory access bandwidth
WO2016068893A1 (en) * 2014-10-29 2016-05-06 Hewlett-Packard Development Company, L.P. Communicating over portions of a communication medium
FR3093830B1 (fr) * 2019-03-11 2021-03-12 St Microelectronics Rousset Procédé de gestion d’accès à un bus partagé, et dispositif électronique correspondant

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FR2482331B1 (fr) * 1980-05-06 1986-03-21 Thomson Csf Mat Tel Procede d'arbitration centralisee, et arbitreur centralise pour systeme multiprocesseur
US4473880A (en) * 1982-01-26 1984-09-25 Intel Corporation Arbitration means for controlling access to a bus shared by a number of modules
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JPS58222361A (ja) * 1982-06-18 1983-12-24 Fujitsu Ltd デ−タ処理システムにおけるアクセス要求の優先順位決定制御方式
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US4663756A (en) * 1985-08-29 1987-05-05 Sperry Corporation Multiple-use priority network
US4760515A (en) * 1985-10-28 1988-07-26 International Business Machines Corporation Arbitration apparatus for determining priority of access to a shared bus on a rotating priority basis
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US4980854A (en) * 1987-05-01 1990-12-25 Digital Equipment Corporation Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfers
US5388228A (en) * 1987-09-30 1995-02-07 International Business Machines Corp. Computer system having dynamically programmable linear/fairness priority arbitration scheme
JPH0786853B2 (ja) * 1988-02-29 1995-09-20 株式会社ピーエフユー バス転送制御方式
US4987529A (en) * 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
US5127089A (en) * 1989-07-03 1992-06-30 Motorola, Inc. Synchronous bus lock mechanism permitting bus arbiter to change bus master during a plurality of successive locked operand transfer sequences after completion of current sequence
US5151994A (en) * 1989-11-13 1992-09-29 Hewlett Packard Company Distributed fair arbitration system using separate grant and request lines for providing access to data communication bus
KR940002905B1 (en) * 1989-12-15 1994-04-07 Ibm Apparatus for conditioning priority arbitration in buffered direct memory addressing
EP0464237A1 (en) * 1990-07-03 1992-01-08 International Business Machines Corporation Bus arbitration scheme
JPH04192056A (ja) * 1990-11-27 1992-07-10 Fujitsu Ltd アービトレーション方式
US5265223A (en) * 1991-08-07 1993-11-23 Hewlett-Packard Company Preservation of priority in computer bus arbitration
US5369748A (en) * 1991-08-23 1994-11-29 Nexgen Microsystems Bus arbitration in a dual-bus architecture where one bus has relatively high latency
US5191656A (en) * 1991-08-29 1993-03-02 Digital Equipment Corporation Method and apparatus for shared use of a multiplexed address/data signal bus by multiple bus masters
EP0537899B1 (en) * 1991-09-27 1999-12-15 Sun Microsystems, Inc. Bus arbitration architecture incorporating deadlock detection and masking
US5301282A (en) * 1991-10-15 1994-04-05 International Business Machines Corp. Controlling bus allocation using arbitration hold
US5239631A (en) * 1991-10-15 1993-08-24 International Business Machines Corporation Cpu bus allocation control
US5708784A (en) * 1991-11-27 1998-01-13 Emc Corporation Dual bus computer architecture utilizing distributed arbitrators and method of using same
DE69319763T2 (de) * 1992-03-04 1999-03-11 Motorola, Inc., Schaumburg, Ill. Verfahren und Gerät zur Durchführung eines Busarbitrierungsprotokolls in einem Datenverarbeitungssystem
US5418920A (en) * 1992-04-30 1995-05-23 Alcatel Network Systems, Inc. Refresh control method and system including request and refresh counters and priority arbitration circuitry
JP2531903B2 (ja) * 1992-06-22 1996-09-04 インターナショナル・ビジネス・マシーンズ・コーポレイション コンピュ―タ・システムおよびシステム拡張装置
JPH0690695B2 (ja) * 1992-06-24 1994-11-14 インターナショナル・ビジネス・マシーンズ・コーポレイション コンピュータ・システムおよびシステム拡張装置
US5396602A (en) * 1993-05-28 1995-03-07 International Business Machines Corp. Arbitration logic for multiple bus computer system
EP0654743A1 (en) * 1993-11-19 1995-05-24 International Business Machines Corporation Computer system having a DSP local bus
US5471590A (en) * 1994-01-28 1995-11-28 Compaq Computer Corp. Bus master arbitration circuitry having improved prioritization
US5528766A (en) * 1994-03-24 1996-06-18 Hewlett-Packard Company Multiple arbitration scheme
US5632020A (en) * 1994-03-25 1997-05-20 Advanced Micro Devices, Inc. System for docking a portable computer to a host computer without suspending processor operation by a docking agent driving the bus inactive during docking
US5524235A (en) * 1994-10-14 1996-06-04 Compaq Computer Corporation System for arbitrating access to memory with dynamic priority assignment
US5596729A (en) * 1995-03-03 1997-01-21 Compaq Computer Corporation First arbiter coupled to a first bus receiving requests from devices coupled to a second bus and controlled by a second arbiter on said second bus
US5734850A (en) * 1995-07-05 1998-03-31 National Semiconductor Corporation Transparent bridge between of a computer system and a method of interfacing the buses to operate as a single logical bus
US5724529A (en) * 1995-11-22 1998-03-03 Cirrus Logic, Inc. Computer system with multiple PC card controllers and a method of controlling I/O transfers in the system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001202327A (ja) * 2000-01-20 2001-07-27 Fujitsu Ltd バス使用効率を高めた集積回路装置のバス制御方式

Also Published As

Publication number Publication date
SG65663A1 (en) 1999-06-22
EP0820018A3 (en) 1999-03-10
EP0820018A2 (en) 1998-01-21
TW336296B (en) 1998-07-11
US5954809A (en) 1999-09-21

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