JPH1069389A - Device that make good use of branch predictive cache without tag by rearrangement of branch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the performance by a super scalar computer system by using static technologies without adding extra hardware. SOLUTION: The method which makes good use of the tagless branch predictive cache by rearranging branches after applying other all optimization as the final path of a compiling process generates a path for instructions in each subprogram and arranges all branches using the branch predictive cache(BPC) in buckets corresponding to respective positions in the BPC 315. Together with the branches, directions which are predicted by profiling data or static heuristics 320 are recorded 325. Then respective buckets are inspected 330. As for a bucket including branches whose predicted directions are contradictious 340, some of those branches try to be moved to other buckets 345. It is ideal to perform the movement locally without exerting any influence on the bucket positions of other branches.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to computers, and more particularly, to an improved branch prediction method for a compiler.

[0002]

2. Description of the Related Art In modern superscalar computers, branch instructions introduce a significant delay and loss of potential performance if their direction (ie, taken or not taken) cannot be accurately predicted. This is because the processor must pause other operations while trying to calculate where the branch will go.
If the processor can predict where the branch will go, it can fetch the branch, eliminating the penalty associated with branch operation.

[0003] A branch prediction cache (BPC) is a hardware configuration that contributes to accurate branch prediction by storing information such as recent branch execution history relating to a branch of a program. This information will be used later to predict the direction the branch will take. The history of a particular branch is accessed using some function of that branch's address. The function maps several distinct branch addresses to the same entry on the table. In untagged BPC, the histories of many branches cannot be identified, thus combining the histories of the branches.

[0004] Unfortunately, when multiple branches with different "taken-not taken" execution patterns map to the same entry in the BPC, their histories interfere and as a result Incorrect branch prediction leads to associated performance penalties. Further, if multiple branches with similar "taken-not taken" execution patterns map to different entries in the BPC, the opportunity to reinforce the branch histories with each other is lost. Such enhancements improve prediction accuracy and allow BPC slots to be opened for use by other branches.

[0005] Prior art solutions have required mainly hardware techniques. For example, the BPC may be increased in size to reduce the likelihood of inconsistency, or the BPC may be tagged so that branches that map to the same location can be identified. It also uses a two-level prediction method to improve the accuracy of branch prediction by incorporating the "taken-not-taken" state of previously executed branches into the BPC look-up table. With this technique, it is easy to identify distinct branches that map to the same location. Such a method would require increased hardware costs and storage of excess data, and / or required comparisons to be made. Further, in the above method, it is not easy to share a common history between the same branches.

For example, refer to the following document.

[0007] E. Smith, A Study of Branch Pre
diction Strategies, 8th Symposium on Computer
Architecture, pp. 135-148, May 1981 (discussing branch prediction methods for maximizing prediction accuracy). Smith, J.M. Lee, Branch Prediction Strategies
and Branch TargetBuffer Design, Computer, pp. 6
-22, January 1984 (to select a good prediction method based on four IBM370 workloads of scientific, commercial, compiler and supervisor, and 26 program address traces classified as CDC6400 and DEC PDP-11 workloads) Discusses systematic methods. T. Pan, K. So, J. T. Rameh, Improving the Acc
uracy of DynamicBranch Prediction Using Branc
h Correlation, ASPLOS, pp. 76-84, October 1992
(Correlation-based method to improve prediction accuracy by incorporating not only information from the history of a specific branch but also information from the history of other branches) Patterson, J .; Hennessy, Computer Architectur
e: A Qualitative Approach, 2d ed. , Pp. 262-27
8, Morgan Kaufmann Publishers Inc. 1996 (Study of branch prediction method to improve accuracy of branch prediction mechanism)

[0008]

SUMMARY OF THE INVENTION There is provided a technique for improving the performance of a superscalar computer system without introducing additional hardware, that is, a technique for improving dynamic performance using a static technique. It would be advantageous.

[0009]

SUMMARY OF THE INVENTION The present invention provides a method and apparatus for utilizing an untagged branch prediction cache by relocating branches. After applying all other optimizations as the final pass in the compilation process, a path is created for the instructions in each subprogram, and all branches using the branch prediction cache (BPC) are It is arranged in each bucket corresponding to the position. With each branch, based on profiling data or static heuristics,
Record the expected direction (taken-not taken). Then each bucket is inspected. For buckets containing branches whose predicted directions are inconsistent, try to move some of those branches to other buckets. Ideally, the movement is performed locally so as not to affect the bucket position of other branches. If the position of other buckets is affected, restart the bucket inspection process after recalculating the bucket positions of all BPC branches. Moving branches that each have a matching predicted direction, but are now in separate buckets, into the same bucket allows the branch histories to reinforce each other. Heuristics can be used to specify which branches to think about, what code transformations to use to relocate branches, and whether to implement conflict avoidance and match enhancement.

[0010]

FIG. 1 is a block diagram outlining a uniprocessor computer architecture 10 that includes a processor cache. In the figure, a processor 11 includes a cache 12 that communicates with a system bus 15. The system memory 13 and one or more input / output devices 14 also communicate with the system bus.

In a compiling operation, a user gives a source code program, which is a program operating on a computer, to a compiler. A compiler accepts source code, processes the code, and creates an executable file optimized for a target computer architecture (eg, computer architecture 10).

FIG. 2 is a block diagram outlining a software compiler 20 used in connection with, for example, the computer architecture 10 shown in FIG. Compiler front end component 21 is a source code file
Read 100 and translate it into a high-level intermediate representation 110. The high-level optimizer 22 has a high-level intermediate representation 11
Optimize 0 for a more efficient format. Code generator 23
Replaces the optimized high-level intermediate representation with the low-level intermediate representation
Translate to 120. The low-level optimizer 24 optimizes the low-level intermediate representation 120 into a more efficient (machine-executable) form. Finally, the object file generator 25
Writes the optimized low-level intermediate representation into the object file 141.

The object file 141 is processed by the linker 26 with the object file 140 to produce an executable file 150 operable on the computer 10. In the invention described in this specification, the executable file
150, if it is running on computer 10,
Suppose that it can be implemented by compiler 20 and linker 26 so that an execution profile 160 is generated that can later be used by low-level optimizer 24 to better optimize low-level intermediate representation 120. Compiler 20
Will be described in detail below.

A program consists of a number of procedures, and branches in one procedure may conflict with branches in another procedure. The present invention does not address such inconsistencies directly. Instead, the present invention provides a technique for checking branches in a procedure. The linker chooses how to arrange such procedures with respect to each other. Although one aspect of the present invention addresses several cross-procedure problems, in general, the techniques disclosed herein operate on one procedure at a time.

In operation, the compiler performs a typical compilation process, ie, compilation and optimization. Therefore, the technique of the present application applies to every instruction in the procedure.
Assign a number starting from 0. This effectively gives each instruction an address. Also, the present technique creates an array of buckets. These buckets are intended to symbolize the location in the branch prediction cache where the branch instruction will be placed by the system hardware. There is one bucket for each element in the system hardware branch prediction cache. Accordingly, the present technique provides a procedure for initiating instruction walkthrough. Whenever a branch instruction is encountered, and the branch instruction is in a category that can be predicted by system hardware, the branch instruction is placed in a bucket. After all instructions are properly placed in the bucket, the inconsistency can be located and the inconsistent instructions can be relocated based on the application of various predetermined criteria.

There are several branches where the system hardware does not attempt to make predictions. The system hardware predicts the branch associated with the program counter. If the target address to which the branch is to branch is in a register, the system hardware does not make a prediction for that branch. Thus, the unpredictable kind of branch is an indirect call. Therefore, the present invention
When a branch is not taken, it can be applied to a branch that always goes to the same place, that is, a branch that goes only in two ways.

When a branch instruction that is taken or not taken is encountered, the present technique drops a record representing the instruction into a bucket where the instruction is mapped by system hardware. In addition to dropping a record representing the instruction into the bucket, a description of the direction in which the branch is expected to proceed is created. Such predictions are based, in part, on the notion that backward branches are more likely to be part of a loop and are more likely to be taken, while earlier branches are less likely to be taken because they are used to test various conditions. is there. Thus, the present invention is based, in part, on heuristics, i.e., empirical inferences about branches.

After deciding whether or not a branch is taken, the instruction is placed in a bucket. After all instructions are in the bucket, if they are predictable buckets, the present invention walks through the bucket.
If the bucket contains more than one branch record,
And if many branch records conflict in their expectations, i.e., one branch record is expected to be taken and some branch records are not expected to be taken, then a conflict occurs on the system hardware. If such a conflict is encountered, the present invention attempts to move some of the conflicting branches out of the bucket. This step changes the instruction stream in the object code.

Changing the instruction stream is not always easy. No operation (no-
If it moves down by inserting it into op), all instructions will move downstream. In such a case, all downstream buckets must be reconfigured. This method is computationally expensive.

Hewlett-Packard (Palo Alto, Calif.) Provides a system architecture with a feature called a delayed branch, where instructions can be placed immediately after a branch and the instruction is executed logically before the branch. I do. The branch can be moved down and the two instructions swapped, but this requires turning on a bit in the branch that indicates that the next instruction is not logically encountered before the current instruction . This mechanism allows a branch to be moved down without having to move all other branches. Unfortunately, there is already a branch in the bucket immediately below the current bucket, so moving the instruction down will create a new inconsistency.

FIG. 3 is a block diagram outlining a technique for utilizing an untagged branch prediction cache by branch relocation according to the present invention. The program procedure 200 is composed of a number of instructions 205. The described technique numbers the instructions 210 and creates a bucket array 220. A bucket can be thought of as a pointer to a list of branches that fall within the bucket. The total number of pointers will be equal in size to the system hardware branch prediction cache 230, with a typical machine having 256 entries. However, the branch prediction cache can be as large or small as desired for the intended architecture.

Initially, each bucket is empty. After initializing the buckets and instructions as described above, the next step is to perform an instruction walkthrough. For example,
Assume that instruction _ij is a conditional branch if x is greater than y for label c. Such a branch may go forward or backward so that it can predict whether the branch will be taken or not taken. The branch is examined and an informed decision is made as to whether the branch is about to be taken. A record is then generated for the branch that maps into the bucket using the address of the branch and characterizes the branch and the cache.

This process consists of another branch i _k, another conditional branch for another comparison with another label.
Until it encounters Assume that this branch is not being taken. This branch potentially maps into the same bucket. However, the instruction i
Suppose _k is determined not to be taken. Therefore, "nt (not t
aken) "and other instructions are labeled" t (taken) "as being taken. Continuing this process of walking through the instructions, describing the branches and putting them in buckets.

The system hardware uses the address modulo of the size of the table to determine the bucket in which to place the instruction. The address of the instruction is, for example, 257,
If the branch prediction cache is numbered 0-255, instruction 257 is located at position 1 in the branch prediction cache. Therefore, those instructions cause a hardware conflict if they have the same address modulo. Thus, inconsistencies can occur if there are enough instructions in the procedure where each bucket must be used for more than one instruction. Conversely, if all of the procedures have fewer instructions than the number of cache lines in the hardware, there is no need to walk through the instructions since there is no conflict.

After the present invention walks through all instructions, it is necessary to walk through the buckets. If the bucket encounters a conflict between the branches 240, the present invention seeks to resolve the conflict.

One way to avoid the inconsistency (described above) is
Removing one of the branches by moving it down. Thus, if one of the contradictory entries matches the next lower entry, the first entry can be moved down to the next bucket and the entries are the same Therefore, heuristics specify that no contradictions occur.

Therefore, the present invention enables the history of various branches to be shared, and can actually enhance the history. Thus, when the two instructions are the same, branch prediction is typically performed because the history of two branches does not need to experience untrained time with respect to the history of one branch when the history of one branch reinforces the other. Better than that.

If there is already an inconsistency in the bucket, it is possible to do a look-ahead, but at some point the system will continue to do the look-ahead and allow more time for the bucket to be reorganized. Spend. Therefore, the present invention preferably looks ahead only one bucket to see which instruction can move down without conflict. If not, the invention sums the amount of inconsistencies to see if anything can be done to reduce them. For example, if the same amount of inconsistency occurs in one bucket, but is much more likely to be taken than not taken in the next another bucket, the present invention will consider the instructions taken Move to bucket. this is,
This is because doing so reduces inconsistencies in the second bucket, for example, because the choices taken are strengthened. Thus, the bucket table helps the compiler make decisions about branches.

A bucket table can be thought of as a software abstraction of what the system hardware is trying to do. When a computer runs a program, a bucket table is represented in some hardware. When a branch is moved down in the table of buckets at the system hardware level, the system hardware executes it until object code encounters the branch. The system hardware has a branch prediction cache 230 that is the same size as the bucket data structure 220. The branch prediction cache has some, but not all, address bits and has the notation "taken" or "not taken".
In fact, the branch prediction cache remembers the last three historical events that occurred for that address. Therefore, that address is taken first, then not,
If taken, then the branch prediction indicates that more is taken than not taken, so the one taken is selected. This allows the branch prediction cache to adapt when the history changes.

FIG. 4 is a flowchart illustrating a technique for utilizing an untagged branch prediction cache by relocating branches according to the present invention. As shown in the figure, the technique of the present application needs to use the exact address where the instruction is located (if that is effective),
The present invention is preferably associated with the low level optimizer 24. Otherwise, if the object code that is about to run on the machine is available, it will not be possible to know the address it takes to the end of the compilation process.

As a final pass of the compilation process, after applying all other optimizations (300), a pass is created for the instructions in each subprogram (310) and the branch prediction cache (BPC) is used. All branches,
Each is arranged in a bucket corresponding to each position in the BPC (315). With each branch, record its expected direction (taken or not taken) based on profiling data or static heuristics (320) (325). Then inspect each bucket (33
0). If the bucket contains branches whose predicted directions are inconsistent (340), an attempt is made to move some of those branches to other buckets (345). Ideally, this movement is performed locally so as not to affect the bucket position of another branch. If the position of other buckets is affected (350), the bucket inspection process is resumed (360) after recalculating the bucket positions of all BPC branches (355). Moving branches that have matching predicted directions, but are now in separate buckets, into the same bucket (370) will enhance the history of the branches. Using heuristics, it is possible to specify which branches to think about, what code transformations to use to relocate branches, and whether to implement conflict avoidance and match enhancement.

The following is a pseudo code example of a routine that takes advantage of the untagged branch prediction cache by relocating branches.

1 For each step in the program, 2 Compile and optimize the code for that step, 3 number the instructions in the step starting from 0, 4 create a bucket array, and the length of the array is The branch prediction cache size, for each instruction in 5 steps, 6 if the branch instruction is to be predicted by hardware, 7 is placed in the bucket for the modulo branch prediction cache size of the instruction, and 8 branches are advanced State the expected direction, 9 for each bucket, 10 try to move some of the conflicting branches to the next bucket if the bucket contains more than one branch and if the directions conflict. Try.

Thus, the present invention implements branch prediction for a procedure from a program by taking the instruction lines from the procedure and organizing them in numerical order.
The present invention then looks for branch instructions and assigns the branch instructions to the bucket array based on the modulo number. This array is very large, but there are more instructions in the array than buckets. If the number of instructions in the array is not greater than the bucket, then no inconsistency occurs and the present invention places branch instructions in the bucket.

However, in many cases, the number of instructions is
More than the number of locations in the bucket array. After some time, some of the buckets will contain branch instructions that conflict with each other. When a conflict occurs, if the location contains the same instruction branch, or if the lower location is empty, a choice must be made as to whether to move the conflicting instruction lower in the bucket array. If the subordinate position results in another inconsistency, it is necessary to determine if it is useful to move the branch instruction. The branch prediction cache can collect this branch information during the operation of the code and generate a history as to what actually happens during the processing of the code. This is because when data is entered into the program, the branch will be different from the branch encountered at compile time (because the compiler was not using the actual data).

In an alternative embodiment of the invention, another conversion trial is used to place the one taken into an odd number of buckets,
The one not taken can be placed in an even number of buckets. Thus, one can work within the array to organize the branches in a predetermined manner that makes more efficient use of system hardware.

While the present invention has been described with reference to preferred embodiments, those skilled in the art will recognize that other applications may be made instead of the embodiments without departing from the spirit and scope of the invention. Will be understood. Accordingly, the invention should only be defined by the claims.

[0038] In the following, an exemplary embodiment will be described which comprises a combination of various constituent features of the present invention.

1. An apparatus for utilizing an untagged branch prediction cache by rearranging a branch, the compiler including, for each procedure in a program, compiling and optimizing the procedure code, wherein the compiler executes each instruction in the procedure. The compiler creates a bucket array, and the compiler places instructions in a bucket for a modulo branch prediction cache size of the instruction number for each branch instruction in the procedure to be predicted, A compiler records the direction in which the branch instruction is expected to be taken (taken or not taken), and for each bucket, the compiler indicates if the bucket contains more than one branch and the direction of the branch If conflicts occur, attempt to move the conflicting branch to the next bucket. Apparatus.

2. 2. The apparatus according to claim 1, wherein a length of the bucket array is equal to a branch prediction cache size.

3. 2. The device according to item 1, wherein a rear branch is easily taken and a front branch is hard to be taken.

4. The apparatus of claim 1, wherein the compiler reinforces each other using the histories of the two branches.

5. The apparatus of claim 1, wherein the compiler sums the amount of inconsistencies to see if the compiler can reduce inconsistencies.

6. The apparatus of claim 1, wherein the compiler moves instructions to the next lower bucket to reduce inconsistencies in the next bucket by enhancing direction selection.

7. The apparatus of claim 1, further comprising a system hardware branch prediction cache that is the same size as the bucket array.

8. The apparatus of claim 1, wherein the branch prediction cache stores a plurality of recent history events for a particular address so that the branch prediction cache adapts as the branch history changes.

9. An apparatus that utilizes an untagged branch prediction cache, comprising: a compiler that creates a path for instructions in a subprogram after all other optimizations have been applied as a final path during the compilation process; Is a branch prediction cache (BP
C) place all the branches using the buckets corresponding to each location in the BPC, and the compiler, along with each branch instruction, the expected direction (taken based on profiling data or static heuristics) Is not recorded in the bucket, and the compiler examines each bucket, and for a bucket containing a branch whose predicted direction is inconsistent, the movement may cause or exacerbate another inconsistency in the other bucket. The apparatus wherein the compiler moves one or more of the branch instructions to another bucket if the inconsistency is reduced or eliminated in the bucket without causing the bucket instruction to be moved.

10. The apparatus of claim 9, further comprising: means for recalculating bucket positions of all BPC branch instructions; and means for restarting the bucket checking process.

11. 10. The apparatus of claim 9, wherein branch instructions having a matching predicted direction but currently in separate buckets are moved into the same bucket and the history of the branch instructions reinforce each other. .

12. The apparatus of claim 9, wherein the compiler further comprises a low-level optimizer.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overview of a uniprocessor computer architecture.

FIG. 2 is a block diagram outlining a software compiler used in connection with, for example, the computer architecture shown in FIG.

FIG. 3 is a block diagram outlining a technique for utilizing an untagged branch prediction cache by relocating branches according to the present invention.

FIG. 4 is a flowchart illustrating a technique for utilizing an untagged branch prediction cache by relocating branches according to the present invention.

[Explanation of symbols]

 200 Program Procedure 205 Instruction 220 Bucket Array 230 Branch Predictive Cache 240 Branch

Claims (1)

[Claims] 1. An apparatus for utilizing an untagged branch prediction cache by rearranging a branch, comprising: for each procedure in a program, a compiler for compiling and optimizing the procedure code; Numbering each instruction in the procedure; the compiler creating a bucket array; the compiler for each branch instruction in the procedure to be predicted, in the bucket for the instruction number modulo branch prediction cache size Instructions, wherein the compiler records the direction (taken or not taken) in which the branch instruction is expected to proceed;
Apparatus characterized by attempting to move the conflicting branch to the next bucket if it contains more than one branch and if the directions of the branches conflict.