JPH1069259A - LCD drive circuit - Google Patents

Abstract

(57) [Summary] When a liquid crystal panel is driven by a method of simultaneous sampling of multiple dots, it is possible to cope with both liquid crystal panels of a 1H inversion method and a dot inversion method. The driving signals SR1 to SR6 are provided by polarity setting means 18A to 18F for switching the operation according to a control signal.
Is inverted as necessary.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a case where a liquid crystal display panel is driven by a method of simultaneous sampling of multiple dots. The present invention makes it possible to cope with both the 1H inversion type and the dot inversion type liquid crystal display panel by inverting the polarity of each drive signal as needed.

[0002]

2. Description of the Related Art Conventionally, in a liquid crystal display device, the driving frequency of the liquid crystal display panel is reduced by reliably driving horizontally consecutive pixels of the liquid crystal display panel at the same time by a method of simultaneous sampling of multiple dots. It can be driven.

FIG. 7 is a block diagram showing a liquid crystal display device to which a multiple dot simultaneous sampling technique is applied. The liquid crystal display device 1 includes red, green, and blue liquid crystal display panels (LCD: Liquid Crystal Display).
2R, 2G, and 2B to drive each of the liquid crystal display panels 2R, 2R, and 2B.
The red, green, and blue images formed on G and 2B are projected onto the screen in a superimposed manner.

In the liquid crystal display device 1, a timing generator (TG) 3 generates various reference signals necessary for the operation of the liquid crystal display device 1 based on a horizontal synchronization signal and a vertical synchronization signal SYNC.

The driver 4 is composed of three signal processing circuits for processing red, green, and blue color signals SR, SG, and SB, and determines the offset voltage, amplitude, and linearity of each of the color signals SR, SG, and SB. By correcting, each color signal S
The signal levels of R, SG, and SB are displayed on the liquid crystal display panels 2R, 2R,
The signal level is corrected to a signal level suitable for driving G and 2B and output. In this signal processing, the driver 4 responds to the drive signal from the timing generator 3 to
The polarities of R, SG, and SB are switched and output every one horizontal scanning period.

The sample and hold circuits (SH) 5R, 5
G and 5B respectively receive red, green and blue color signals SR, SG and SB output from the driver 4 and sequentially output the color signals SR at timings corresponding to successive pixels of the liquid crystal display panels 2R, 2G and 2B. , SG, and SB are sampled and held, whereby the drive signals SR1
To SR6, SG1 to SG6, and SB1 to SB6.

In the liquid crystal display panels 2R, 2G, and 2B, six signal lines that are continuous in the horizontal direction are sequentially and cyclically connected in units of six, and drive signals of six channels are respectively connected to these parallel-connected signal lines. SR1 to SR6, SG1 to S
G6, SB1 to SB6 are supplied. In addition, the liquid crystal display panels 2R, 2G, and 2B respectively provide drive signals SR1 to SR6, SG1 to SG
6, so that SB1 to SB6 are sequentially and cyclically applied,
The selection signal SEL is supplied from the timing generator 3. Thus, the liquid crystal display panels 2R, 2G, and 2B
Six pixels that are continuous in the horizontal direction are simultaneously driven in parallel,
The frequency required for driving can be reduced to 1/6 as compared with the case where continuous pixels are driven at corresponding timings.

[0008] Further, as shown in FIG.
Is driven by the driver 4 when driving in this manner.
By inverting the polarities of the color signals SR, SG, and SB for each horizontal scanning period, the liquid crystal display panels 2R, 2G, and 2B are driven by switching the polarity for each line that is continuous in the vertical direction (that is, 1H inversion). In FIG. 8, the polarity is indicated by symbols + and-), thereby effectively avoiding deterioration of the liquid crystal display panels 2R, 2G, and 2B.

[0009]

By the way, in a liquid crystal display panel, driving is performed by so-called dot inversion, and 1
In some cases, a high-quality display screen can be formed as compared with the case of driving by H inversion. Here, in the driving by dot inversion, as shown in FIG. 9, the liquid crystal display panels 2 R, 2 G, 2
B is a method of driving B.

[0010] With respect to a liquid crystal display panel suitable for such a dot inversion drive, if the driver 4 can be used in common, the applicable range of this type of drive circuit can be increased and it is considered to be convenient. Can be

The present invention has been made in consideration of the above points, and is applied to a liquid crystal driving circuit based on a multiple dot simultaneous sampling method, and is applicable to both a 1H inversion method and a dot inversion liquid crystal display panel. It is intended to propose a liquid crystal driving circuit capable of performing the above.

[0012]

According to the present invention, there is provided a multi-channel polarity setting means for setting and outputting a plurality of driving signal polarities in accordance with a control signal. I do.

If the polarity of the drive signals of a plurality of channels is set and output in accordance with the control signal, the polarity is inverted between the pixels that are continuous in the horizontal direction by setting the polarity.
Alternatively, the liquid crystal display panel can be driven with the same polarity. Therefore, the liquid crystal display panel can be driven by dot inversion or 1H inversion.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(1) First Embodiment FIG. 1 is a block diagram showing a liquid crystal display device according to a first embodiment of the present invention. In the liquid crystal display device 10, the digital signal processing circuits 11R, 11G, and 11B process the respective color signals SR, SG, and SB into digital signals, and drive signals SR1 to SR6, SG1 to SG6, and SB1 to SB6.
Generate The digital signal processing circuits 11R and 11R
G and 11B have the same configuration except that the color signals to be processed are different and the signal levels to be set are different. Therefore, in FIG. 1, only the digital signal processing circuit 11R is described in detail. Describe.

That is, the digital signal processing circuit 11R,
11G and 11B are analog-to-digital conversion circuits (A /
D) 12 receives the color signals SR, SG, and SB, respectively, and, based on the clock output from the timing generator (TG) 3, sets the respective color signals SR based on the timing corresponding to the pixels of the liquid crystal display panels 2R, 2G, and 2B. , SG,
The SB is subjected to analog-to-digital conversion processing to generate a digital color signal.

The memory 13 holds a plurality of types of serial data input from the system control circuit, and stores the stored serial data in the corresponding brightness adjustment circuit 14, gain adjustment circuit 15, gamma adjustment circuit 16, inversion / non-inversion. Output to the circuit 18 respectively.

The brightness adjustment circuit 14 is provided in the memory 13
The offset voltage of the digital color signal output from the analog-to-digital conversion circuit 12 is corrected and output in accordance with the serial data value set as described above, whereby the brightness of the display screen of the liquid crystal display device 10 is adjusted.

The gain adjustment circuit 15 corrects the amplitude of the digital color signal output from the brightness adjustment circuit 14 in accordance with the serial data value set by the memory 13 and outputs the corrected signal. Adjust the gain of the display screen.

The gamma adjustment circuit 16 corrects the linearity of the digital color signal output from the gain adjustment circuit 15 in accordance with the serial data value set by the memory 13 and outputs the corrected signal. Adjust the gamma of the display screen at. The brightness adjustment circuit 14, the gain adjustment circuit 15, the gamma adjustment circuit 16
Constitutes a signal level adjusting circuit for adjusting the signal level of the digital color signal.

Serial / parallel conversion circuit (S / P) 17
Generates six systems of parallel data by sequentially and cyclically selecting continuous digital color signals, and outputs the six systems of parallel data DR1 to DR6 simultaneously and in parallel. Thus, the serial / parallel conversion circuit 17 constitutes a data conversion means for sequentially and cyclically selecting continuous digital video signals and generating drive signals for a plurality of channels.

The inversion / non-inversion processing circuits 18A to 18F
These parallel data DR1 to DR6 are input, and the parallel data DR1 to DR6 are input according to control data DC set by the system control circuit.
6 are set and output.

That is, as shown in FIG. 2, the inversion / non-inversion processing circuits 18A to 18F include selectors 19A to 19A, respectively.
An output signal Y (n) represented by the following equation is output according to the logic level of the selection signal SE input via the interface 19F. Here, X (n) is an inversion / non-inversion processing circuit 18A-18.
F indicates the digital value of the parallel data DR1 to DR6 input to F, and Xmax is the liquid crystal display panel 2R, 2X.
G, 2B.

(Equation 1)

Thus, the inversion / non-inversion processing circuits 18A-
18F are parallel data DR1 to DR1 centered on a predetermined center voltage in accordance with the logic level of the selection signal SE.
6 is switched.

On the other hand, the selectors 19A to 19F
As shown in FIG. 3, a polarity inversion pulse FRP (FIG. 3A) whose logic level is inverted every one horizontal scanning period is input from the timing generator 3, and the polarity inversion pulse FRP is input via inverter circuits 20A to 20F. FRP
The inverted pulse XFRP shown in FIG. 3A is input, and these two input pulses are selectively output according to control data DC set by the system control circuit.

Thus, the inversion / non-inversion processing circuits 18A-
18F, when the polarity inversion pulse FRP or the inversion pulse XFRP of the polarity inversion pulse FRP is set to be selectively input from any of the selectors 19A to 19F, the input parallel data DR1 to DR6 (FIG. 3B) ), The parallel data DR1O to DR6O having the same polarity are inverted in one horizontal scanning cycle 1H (FIG. 3).
(C)).

On the other hand, as shown in FIG. 4, odd-numbered inversion / non-inversion processing circuits 18A, 18C, 18E and even-numbered inversion / non-inversion processing circuits 18B, 18D, 18F.
Are set so that the polarity inversion pulse FRP and the inversion pulse XFRP of the polarity inversion pulse FRP are selectively input (FIGS. 4A and 4B), respectively, and the input parallel data DR1 to DR6 (FIG. 3). (B)), 1
Parallel data DR1O to DR whose polarity is inverted in the horizontal scanning cycle and whose polarity is inverted between adjacent channels.
6O (FIGS. 4D and 4E).

The digital signal processing circuit 1
1R, 11G, and 11B are generated in this way.
The parallel data DR1O to DR6O of the channels are subjected to digital-to-analog conversion processing to generate drive signals to which a multi-dot simultaneous sampling technique is applied. In the case shown in FIG. 3, a liquid crystal display panel is formed in units of one line. The polarities of the drive signals applied to the 2R, 2G, and 2B are switched, and the liquid crystal display panels 2R, 2G, and 2B can be driven under the 1H inversion condition.
In the case shown in FIG. 4, in addition to this, the polarity of the drive signal applied to the liquid crystal display panels 2R, 2G, and 2B is switched for each adjacent pixel. LCD panel 2
R, 2G, and 2B can be driven.

In this embodiment, the inverting / non-inverting processing circuits 18A to 18F adjust the conditions of the selectors 19A to 19F so that the liquid crystal display panels 2R, 2G and 2B are driven under the condition of 1H inversion. It has been made to be set.

Thus, the inversion / non-inversion processing circuit 18A-
Reference numeral 18F constitutes a polarity setting means for a plurality of channels for setting and outputting the polarities of the drive signals for the plurality of channels according to the control signal.

Digital-to-analog conversion circuit (D / A) 2
1A to 21F are the parallel data DR1O to D, respectively.
R6O is subjected to digital-to-analog conversion processing, and the
1 to SR6 (SG1 to SG6, SB1 to SB6).

The amplification / level shift circuits 23R, 23G,
23B is constituted by a 6-channel amplifier and a level shift circuit, respectively, and drive signals SR1 to SR6, SG
After amplifying 1 to SG6 and SB1 to SB6 with a predetermined gain,
The level of the inverted signal is shifted to the liquid crystal display panel 2R,
G, 2B.

In the above configuration, each color signal SR, S
G and SB (FIG. 1) are converted into digital color signals by analog-to-digital conversion circuits 12 of digital signal processing circuits 11R, 11G, and 11B, respectively, and thereafter, a brightness adjustment circuit 14, a gain adjustment circuit 15, a gamma adjustment circuit 16 , The signal level is corrected. Subsequently, the digital color signal is sequentially and cyclically selected by the serial / parallel conversion circuit 17 and divided into six systems of parallel data.
Are input to the inversion / non-inversion processing circuits 18A to 18F simultaneously and in parallel.

Here, these six systems of parallel data DR
The polarity of each of 1 to DR6 is independently set by the selectors 19A to 19F, and the polarity inversion pulse FRP or the polarity inversion pulse FR is output from any of the selectors 19A to 19F.
When the inverted pulse XFRP of P is set to be selectively inputted, the inputted parallel data DR1 to DR6
In contrast to FIG. 3 (B), the polarity is inverted in one horizontal scanning cycle, and the parallel data DR1O to DR6O having the same polarity as each other.
(FIG. 3C) is output. As a result, the polarity is switched every horizontal scanning period, and the liquid crystal display panels 2R, 2G, and 2B can be driven under the condition of 1H inversion.

The odd-numbered inversion / non-inversion processing circuit 18
A, 18C, 18E and even-numbered inversion / non-inversion processing circuits 18B, 18D, 18F respectively have a polarity inversion pulse FRP and an inversion pulse XFRP of the polarity inversion pulse FRP.
Are set to be selectively input (FIGS. 4A and 4B), the input parallel data DR1 to DR6 are input.
In contrast to (FIG. 4 (C)), parallel data DR1O to DR6O (FIG. 4 (D) and (E)) in which the polarity is inverted in one horizontal scanning cycle and the polarity is inverted between adjacent channels. Is output. Thus, the liquid crystal display panels 2R, 2G, and 2B can be driven under the dot inversion condition by switching the polarity for each adjacent pixel.

That is, these parallel data DR1O ~
DR60 is a digital-to-analog conversion circuit 21
Drive signal SR1 consisting of analog signals in A to 21F
To SR6, SG1 to SG6, and SB1 to SB6, and these drive signals SR1 to SR6, SG1 to SG6,
SB1 to SB6 are amplification / level shift circuits 23R and 23
G, 23B and amplified by the liquid crystal display panels 2R, 2R
G, 2B.

In the liquid crystal display panels 2R, 2G, and 2B, drive signals SR1 to SR6 of these six channels are provided.
SG1 to SG6 and SB1 to SB6 are sequentially and cyclically assigned to signal lines adjacent in the horizontal direction, and six pixels continuous in the horizontal direction are sequentially driven by the selection signal SEL supplied from the timing generator 3 to drive signals SR1 to SR6. S
R6, SG1 to SG6, and SB1 to SB6 are simultaneously driven in parallel to form an image corresponding to the color signals SR, SG, and SB, and this image is displayed on a predetermined screen.

According to the above arrangement, after successively and sequentially selecting digital color signals to generate parallel data of a plurality of channels, the polarities of these parallel data are set according to the control data DC and output. By doing so, the liquid crystal display panel can be driven according to the 1H inversion condition and the dot inversion condition as needed. Accordingly, the digital signal processing circuits 11R, 11G, and 11B, which are driving circuits for the liquid crystal display panel, can be applied to various liquid crystal display devices to improve usability.

(2) Second Embodiment FIG. 5 is a block diagram showing a liquid crystal display device according to a second embodiment. In FIG. 5, the same components as those of the above-described first embodiment are denoted by the same reference numerals, and duplicate description will be omitted.

In the liquid crystal display device 30, the digital signal processing circuits 31R, 31G and 31B apply the color signal S to the digital signal processing circuits 31R, 31G and 31B.
After inputting R, SG, and SB and converting them into digital color signals, the signal levels are corrected in a brightness adjustment circuit 14, a gain adjustment circuit 15, and a gamma adjustment circuit 16. After the serial / parallel conversion circuit 32 converts the data into parallel data of a plurality of channels, the inversion / non-inversion processing circuits 33A to 33F set the polarity.

The serial / parallel conversion circuit 32 is controlled by the system control circuit so as to be able to set the number of channels of the parallel data to be generated, thereby simultaneously driving six dots as in this embodiment. For the liquid crystal display panels 2R, 2G, and 2B,
While sequentially input digital color signals are sequentially divided into six systems to generate parallel data of six channels, for example, for a liquid crystal display panel of a type in which three dots are driven simultaneously, the sequentially input digital color signals are output. The signals are sequentially distributed to three systems to generate three-channel parallel data. Thereby, the digital signal processing circuit 31
The operation of R, 31G, and 31B can be switched according to the liquid crystal display panel to be driven.

Subsequent inversion / non-inversion processing circuits 33A to 33F
Are controlled by a system control circuit to switch the operation in conjunction with the serial / parallel conversion circuit 32.
When the parallel data of the channels is output, the inversion / non-inversion processing circuit 33A of all the channels is correspondingly output.
33F sets and outputs the polarity of the parallel data.
On the other hand, when parallel data of three channels is output from the serial / parallel conversion circuit 32, the inversion / non-inversion processing circuits 33A to 33A of three channels are correspondingly output.
3C sets and outputs the polarity of the parallel data and outputs the remaining 3
The channel inversion / non-inversion processing circuits 33D to 33F stop operating. Thereby, the inversion / non-inversion processing circuit 33A
-33F are designed to reduce power consumption.

Digital-to-analog conversion circuits 34A-34
F is, like the inversion / non-inversion processing circuits 33A to 33F,
Controlled by the system control circuit, the operation is switched in conjunction with the serial / parallel conversion circuit 32. For example, when three channels of parallel data are output from the serial / parallel conversion circuit 32, the three-channel digital / analog conversion circuits 34D to 34D are output. 34F stops operating, thereby reducing power consumption.

According to the configuration shown in FIG. 5, in addition to the configuration of the first embodiment, the number of channels can be switched in accordance with the driving object, so that in addition to the effect of the first embodiment, Further, the digital signal processing circuits 11R, 11G, and 11B, each of which further comprises a liquid crystal display panel driving circuit, can be applied to various liquid crystal display devices. Inverting / non-inverting processing circuits 33A to 33A according to the number of channels.
By stopping the operations of the 3F and digital-to-analog conversion circuits 34A to 34F, unnecessary power consumption can be effectively avoided, and power consumption can be reduced accordingly.

(3) Other Embodiments In the above embodiment, the case where the liquid crystal display panel is driven by the drive signals of six channels has been described. However, the present invention is not limited to this, and multiple dot simultaneous sampling is performed. The method can be widely applied to a case where a liquid crystal display panel is driven by a plurality of driving signals by applying the method. When the drive signal is driven by dot inversion when the number of channels of the drive signal is odd, the operation of the inversion / non-inversion processing circuit is switched in one dot cycle by the drive signal from the timing generator.

In the above-described embodiment, the case where the red, green, and blue liquid crystal display panels are driven has been described. However, the present invention is not limited to this. For example, as shown in FIG. Can be widely applied to the case of driving a single-panel type liquid crystal display panel 41 in which is disposed. That is, the liquid crystal display device 4 shown in FIG.
At 0, the red, green and blue color signals SR, SG,
The SB is input to the digital signal processing circuit 42, where it is converted into a digital color signal to correct the signal level. Further, after the polarities of these three digital color signals are set by an inversion / non-inversion processing circuit, the signals are converted into analog signals to directly generate a drive signal, and the drive signal is amplified by an amplifier circuit 43. Thus, the single-panel liquid crystal display panel 41
Can be driven by 1H inversion or dot inversion.

[0047]

As described above, according to the present invention, the liquid crystal display panel is driven by the multiple dot simultaneous sampling method by inverting the polarity of each drive signal as necessary, thereby achieving the 1H inversion method and the dot It can support both liquid crystal display panels by the inversion method.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an inversion / non-inversion processing circuit of the liquid crystal display device of FIG. 1 together with peripheral circuits.

FIG. 3 is a signal waveform diagram for explaining a case where the digital signal processing circuit of the liquid crystal display device of FIG. 1 is driven under the condition of 1H inversion.

FIG. 4 is a signal waveform diagram for explaining a case where the digital signal processing circuit of the liquid crystal display device of FIG. 1 is driven under dot inversion conditions.

FIG. 5 is a block diagram showing a liquid crystal display device according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing a liquid crystal display device according to another embodiment of the present invention.

FIG. 7 is a block diagram showing a conventional liquid crystal display device.

FIG. 8 is a schematic diagram for explaining the driving of the liquid crystal display panel by 1H inversion.

FIG. 9 is a schematic diagram used to explain driving of a liquid crystal display panel by dot inversion.

[Explanation of symbols]

1, 10, 30, 40 ... liquid crystal display device, 2R, 2G,
2B, 41: liquid crystal display panel, 3: timing generator, 11R, 11G, 11B, 42: digital signal processing circuit, 17, 32: serial / parallel conversion circuit, 18A to 18F, 33A to 33F: inversion / Non-inverting processing circuit, 19A to 19F ... selector, 21A to 2
1F, 34A to 34F ... Digital-to-analog conversion circuit

Claims (3)

[Claims] In a liquid crystal drive circuit for driving a liquid crystal display panel by outputting drive signals of a plurality of channels by a method of simultaneous sampling of multiple dots, the polarity of the drive signals of the plurality of precursor channels is set according to a control signal. A liquid crystal drive circuit, comprising: a plurality of channels of polarity setting means for outputting the signals. 2. The liquid crystal drive circuit according to claim 1, further comprising data conversion means for sequentially and cyclically selecting a continuous digital video signal to generate the drive signals of the plurality of channels. 3. The data conversion means switches the number of the plurality of channels in response to a control signal, and the polarity setting means stops the operation according to the number of channels of the data conversion means. The liquid crystal drive circuit according to claim 2, wherein