JPH1065158A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH1065158A JPH1065158A JP8219769A JP21976996A JPH1065158A JP H1065158 A JPH1065158 A JP H1065158A JP 8219769 A JP8219769 A JP 8219769A JP 21976996 A JP21976996 A JP 21976996A JP H1065158 A JPH1065158 A JP H1065158A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- type
- base layer
- square cells
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 16
- 229920005591 polysilicon Polymers 0.000 abstract description 16
- 230000015556 catabolic process Effects 0.000 abstract description 15
- 238000000034 method Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 31
- 238000010586 diagram Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置に関
し、特に、高破壊耐量を有する縦型半導体装置の構造に
関する。The present invention relates to a semiconductor device, and more particularly to a structure of a vertical semiconductor device having a high breakdown strength.
【０００２】[0002]
【従来の技術】従来のこの種の半導体装置について、Ｎ
型の縦型絶縁型半導体装置を例に挙げ、これを図３の
(Ｂ)に基づいて説明する。従来の上記半導体装置は、図
３の(Ｂ)に示すように、Ｎ型半導体基板１上のＮ型エピ
２中にＰ型ベ−ス層５を有し、このＰ型ベ−ス層５中に
Ｎ型ソ−ス層７を有するものである。なお、図３の(Ｂ)
において、３はゲ−ト酸化膜，４はポリシリコン，６は
Ｐ+ベ−ス層 ，８は層間絶縁膜，９はソ−ス電極，１０
は裏面電極である。2. Description of the Related Art A conventional semiconductor device of this type is
As an example, a vertical type insulated semiconductor device is shown in FIG.
Description will be made based on (B). The conventional semiconductor device has a P-type base layer 5 in an N-type epitaxial layer 2 on an N-type semiconductor substrate 1 as shown in FIG. It has an N-type source layer 7 therein. In addition, FIG.
In the figures, 3 is a gate oxide film, 4 is polysilicon, 6 is a P + base layer, 8 is an interlayer insulating film, 9 is a source electrode, 10
Is a back electrode.
【０００３】次に、上記半導体装置の従来技術による製
造方法について、Ｎ型の縦型電界効果型半導体装置を例
に挙げ、図３の(Ａ)および前掲の図３(Ｂ)に基づいて説
明する。なお、図３は、従来の半導体装置の工程Ａ〜工
程Ｂからなる製造工程順断面図である。Next, a conventional method for manufacturing the above semiconductor device will be described with reference to FIG. 3A and FIG. 3B, taking an N-type vertical field effect type semiconductor device as an example. I do. FIG. 3 is a cross-sectional view of a conventional semiconductor device in the order of manufacturing steps including steps A and B.
【０００４】まず、図３の(Ａ)に示すように、Ｎ型半導
体基板１上にＮ型エピ２を成長させ、このＮ型エピ２上
にゲ−ト酸化膜３およびポリシリコン４を形成する。次
に、フォトリソグラフィ技術を用いて窓開けを行った
後、ポリシリコン４をマスクとしてベ−スイオン注入を
行い、図３の(Ｂ)に示すＰ型ベ−ス層５の形成を行う。
この時にＰ型ベ−ス層５の形状が決定される。First, as shown in FIG. 3A, an N-type epi 2 is grown on an N-type semiconductor substrate 1, and a gate oxide film 3 and a polysilicon 4 are formed on the N-type epi 2. I do. Next, after opening a window using the photolithography technique, base ions are implanted using the polysilicon 4 as a mask to form a P-type base layer 5 shown in FIG. 3B.
At this time, the shape of the P-type base layer 5 is determined.
【０００５】さらに、図３の(Ｂ)に示すように、Ｐ+ベ
−ス層６，Ｎ型ソ−ス層７の形成を行い、続いて、層間
絶縁膜８を成長させ、フォトリソグラフィにより窓開け
を行い、ソ−ス電極９を形成する。最後に裏面電極１０
を形成し、図３の(Ｂ)に示す半導体装置を得る。Further, as shown in FIG. 3B, a P + base layer 6 and an N-type source layer 7 are formed, and subsequently, an interlayer insulating film 8 is grown and photolithography is performed. The window is opened, and the source electrode 9 is formed. Finally, the back electrode 10
Is formed to obtain the semiconductor device shown in FIG.
【０００６】ここで、従来の半導体装置の構造につい
て、図４を参照して説明する。なお、図４は、従来の半
導体装置の構造を説明する図であって、(Ａ)はその平面
図であり、(Ｂ)，(Ｃ)は、(Ａ)のＡ−Ａ線，Ｂ−Ｂ線の
断面図である。Here, the structure of a conventional semiconductor device will be described with reference to FIG. 4A and 4B are diagrams for explaining the structure of a conventional semiconductor device, wherein FIG. 4A is a plan view thereof, and FIGS. 4B and 4C are lines AA of FIG. It is sectional drawing of the B line.
【０００７】従来の半導体装置の構造は、図４の(Ａ)〜
(Ｃ)に示すように、正方セル１２が縦横等間隔に並べた
構造からなる。このため、対向する正方セル１２のセル
間隔“ｂ”は、隣接するセル間隔“ａ”よりも大きくな
っている(ｂ＞ａ)。なお、図４(Ａ)〜(Ｃ)中の１１は空
乏層であり、その他の符号は、前掲の図３と同一である
ので、その説明を省略する。The structure of a conventional semiconductor device is shown in FIGS.
As shown in FIG. 3C, the square cells 12 are arranged at equal intervals in the vertical and horizontal directions. For this reason, the cell interval “b” between the opposed square cells 12 is larger than the adjacent cell interval “a” (b> a). Note that 11 in FIGS. 4A to 4C is a depletion layer, and the other reference numerals are the same as those in FIG.
【０００８】また、従来技術の例として、特開昭64−39
069号公報に記載の電界効果型トランジスタを挙げる。
この例では、ベ−ス対向部分の中間にベ−スと同一導電
型の拡散層を形成し、ソ−ス電極とコンタクトをとるこ
とを特徴としている。As an example of the prior art, Japanese Patent Laid-Open No. 64-39
The field effect transistor described in Japanese Patent Application Publication No. 069 is mentioned.
This example is characterized in that a diffusion layer of the same conductivity type as that of the base is formed in the middle of the base facing portion to make contact with the source electrode.
【０００９】[0009]
【発明が解決しようとする課題】ところで、前掲の図４
(Ａ)〜(Ｃ)に示した従来の半導体装置の構造では、図４
(Ａ)に示すように、対角線上で対向する正方セル１２，
１２のゲ−トポリシリコン幅(セル間隔“ｂ”)が隣接す
る正方セル１２，１２のゲ−トポリシリコン幅(セル間
隔“ａ”)の約１．４倍以上になってしまう。このた
め、図４(Ｂ)に示すように、隣接セルで空乏層１１がつ
ながっていても、対角線上で対向するセル間では、図４
(Ｃ)に示すように、空乏層１１がつながっていない。However, FIG.
In the structure of the conventional semiconductor device shown in FIGS.
As shown in (A), square cells 12, diagonally opposed,
The gate polysilicon width of 12 (cell spacing "b") is about 1.4 times or more the gate polysilicon width of adjacent square cells 12 and 12 (cell spacing "a"). For this reason, as shown in FIG. 4B, even if the depletion layer 11 is connected in the adjacent cells, the cells in the diagonally opposite cells are not connected to each other.
As shown in (C), the depletion layer 11 is not connected.
【００１０】このため、コ−ナ部で電界集中によるブレ
−クダウンが起こり、これにより、ベ−ス電流が流れ、
素子破壊に至るという欠点を有している。このため、破
壊耐量が正方セル１２に依存してしまい、結果的に破壊
耐量が低下する原因になっていた。As a result, breakdown occurs due to electric field concentration at the corner portion, and a base current flows.
There is a disadvantage that the device is destroyed. For this reason, the breakdown strength depends on the square cell 12, and as a result, the breakdown strength is reduced.
【００１１】また、前掲の特開昭64−39069号公報に記
載のトランジスタの場合、対角線上で対向するベ−ス・
ベ−ス間に形成された拡散層とコンタクトをとる必要が
あり、そのため、その大きさに制限ができてしまい、単
位セル構造の縮小化が困難であるという問題があった。Further, in the case of the transistor described in the above-mentioned Japanese Patent Application Laid-Open No. 64-39069, base transistors opposed on a diagonal line are used.
It is necessary to make contact with the diffusion layer formed between the bases, so that the size can be limited, and there is a problem that it is difficult to reduce the unit cell structure.
【００１２】本発明は、上記欠点，問題点に鑑み成され
たものであって、その目的とするところは、ベ−ス間の
間隔を均一化することにより、部分的なブレ−クダウン
を防止して破壊耐量の向上を図ることが可能な半導体装
置を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks and problems. It is an object of the present invention to make uniform the intervals between bases to prevent partial breakdown. It is another object of the present invention to provide a semiconductor device capable of improving the breakdown strength.
【００１３】[0013]
【課題を解決するための手段】本発明に係る半導体装置
は、ベ−ス層中にソ−ス層を有する半導体装置におい
て、該ベ−ス層のコ−ナ部(ベ−スコ−ナ部)を凸状とす
ることを特徴とし、これによって、前記した目的とする
半導体装置を提供するものである。According to the present invention, there is provided a semiconductor device having a source layer in a base layer, wherein the base layer has a corner portion (base corner portion). ) Is formed in a convex shape, thereby providing the target semiconductor device described above.
【００１４】即ち、本発明は、「第一の導電型を有する
半導体基板上に第二の導電型のベ−ス層を有し、該ベ−
ス層中に前記第一の導電型のソ−ス層を有する半導体装
置において、前記ベ−ス層のコ−ナ部が凸状になってい
ることを特徴とする半導体装置。」(請求項１)を要旨と
する。That is, the present invention provides a semiconductor device having a second conductive type base layer on a semiconductor substrate having a first conductive type.
A semiconductor device having a source layer of the first conductivity type in a base layer, wherein a corner portion of the base layer is convex. (Claim 1).
【００１５】[0015]
【発明の実施の形態】以下、本発明の実施の形態を挙
げ、本発明について詳細に説明すると、本発明に係る半
導体装置は、前記したとおり、ベ−スのコ−ナ部を凸状
構造とすることを特徴とする。この凸状構造としては、
円弧状の凸状または多角形状の凸状とすることが好まし
い。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to embodiments of the present invention. As described above, a semiconductor device according to the present invention has a base corner portion having a convex structure. It is characterized by the following. As this convex structure,
It is preferable to use an arc-shaped convex shape or a polygonal convex shape.
【００１６】このようにベ−スのコ−ナ部を凸状構造と
することことで、対向するベ−ス間隔を隣接したベ−ス
間隔と同じか又はそれ以下にすることが可能となる。ま
た、ベ−スのコ−ナ部に部分的にソ−スを形成しない構
成とすることで、凸状の部分でソ−ス電極とコンタクト
させる必要がなく、幅を小さくすることができる。By making the corners of the bases have a convex structure in this manner, it is possible to make the spacing between the facing bases equal to or less than the spacing between the adjacent bases. . In addition, since the source is not formed partially at the corner of the base, it is not necessary to make contact with the source electrode at the convex portion, and the width can be reduced.
【００１７】[0017]
【実施例】次に、本発明の実施例を挙げ、本発明に係る
半導体装置を具体的に説明するが、本発明は、以下の実
施例にのみ限定されるものではない。EXAMPLES Next, the semiconductor device according to the present invention will be specifically described with reference to examples of the present invention. However, the present invention is not limited only to the following examples.
【００１８】（実施例１）図１は、本発明の一実施例
(実施例１)を示す図であって、(Ａ)はその半導体装置の
平面図であり、(Ｂ)，(Ｃ)は、(Ａ)のＡ−Ａ線，Ｂ−Ｂ
線断面図である。(Embodiment 1) FIG. 1 shows an embodiment of the present invention.
2A is a plan view of the semiconductor device, FIG. 2B is a plan view of the semiconductor device, FIG. 2B is a plan view of the semiconductor device, FIG.
It is a line sectional view.
【００１９】本実施例１の半導体装置２０は、図１の
(Ａ)〜(Ｃ)に示すように、従来の半導体装置と同様、正
方セル２２が縦横等間隔となるように並べられている。
また、正方セル２２のコ−ナ部２３が円弧状の凸状にな
っている。これによって、対角線上で対向する正方セル
２２，２２のゲ−トポリシリコン幅“ｂ”が、縦又は横
に隣接する正方セル２２，２２のゲ−トポリシリコン幅
“ａ”と同じか又はそれ以下になっている(ｂ≦ａ)。The semiconductor device 20 according to the first embodiment has a structure shown in FIG.
As shown in (A) to (C), the square cells 22 are arranged at equal intervals in the vertical and horizontal directions as in the conventional semiconductor device.
The corner 23 of the square cell 22 has an arcuate convex shape. As a result, the gate polysilicon width "b" of the diagonally opposed square cells 22, 22 is the same as the gate polysilicon width "a" of the vertically or horizontally adjacent square cells 22, 22, or It is less than that (b ≦ a).
【００２０】なお、本実施例１の半導体装置２０は、図
１の(Ｂ)に示すように、第一の導電型を有する半導体基
板１中に第二の導電型のＰ型ベ−ス層５を有し、このベ
−ス層５中に第一の導電型のＮ型ソ−ス層７を有してい
る。（図１中の符号２はＮ型エピ，３はゲ−ト酸化膜，
４はポリシリコン，６はＰ+型ベ−ス層，８は層間絶縁
膜である。この半導体装置２０のコ−ナ部２３以外の部
分は従来と同様であり、詳細な説明は省略する。）As shown in FIG. 1B, the semiconductor device 20 of the first embodiment has a P-type base layer of a second conductivity type in a semiconductor substrate 1 having a first conductivity type. The base layer 5 has an N-type source layer 7 of the first conductivity type. (Reference numeral 2 in FIG. 1 indicates an N-type epi, 3 indicates a gate oxide film,
4 is polysilicon, 6 is a P + type base layer, and 8 is an interlayer insulating film. Portions of the semiconductor device 20 other than the corner portion 23 are the same as those in the related art, and a detailed description thereof will be omitted. )
【００２１】前記したように、本実施例１の半導体装置
２０では、対角線上で対向する正方セル２２，２２のコ
−ナ部２３，２３が円弧状の凸状になっていて、図１
(Ｂ)に示す縦又は横に隣接する正方セル２２，２２のゲ
−トポリシリコン幅“ａ”より、図１(Ｃ)に示す対角線
上に対向する正方セル２２，２２のゲ−トポリシリコン
幅“ｂ”が、同一か又は小さくなっている(ｂ≦ａ)の
で、空乏層１１のつながりが均一になる。従って、正方
セル２２，２２のコ−ナ部２３でのブレ−クダウンがな
くなり、破壊耐量が向上する。実験では、破壊耐量が約
10％向上した。なお、正方セル２２，２２の対角線上で
のゲ−トポリシリコン幅“ｂ”は、縦横方向のゲ−トポ
リシリコン幅“ａ”の0.9〜1.0倍が望ましい。なお、コ
−ナ部２３を円弧状の凸状に形成する手段としては、ポ
リシリコン４のエッチングにより行うことができる。As described above, in the semiconductor device 20 according to the first embodiment, the corners 23 of the square cells 22 facing each other on the diagonal are convex in the shape of an arc.
From the gate polysilicon width "a" of the vertically or horizontally adjacent square cells 22, 22 shown in FIG. 1B, the gate polysilicon of the square cells 22, 22 opposed on the diagonal line shown in FIG. Since the silicon width “b” is the same or smaller (b ≦ a), the connection of the depletion layer 11 becomes uniform. Therefore, the breakdown at the corner 23 of the square cells 22, 22 is eliminated, and the breakdown strength is improved. In the experiment, the breakdown strength was about
10% improvement. The gate polysilicon width "b" on the diagonal line of the square cells 22, 22 is preferably 0.9 to 1.0 times the gate polysilicon width "a" in the vertical and horizontal directions. In addition, as a means for forming the corner portion 23 in an arc-shaped convex shape, it can be performed by etching the polysilicon 4.
【００２２】（実施例２）図２は、本発明の他の実施例
(実施例２)を示す図であって、そのうち(Ａ)は、その半
導体装置の平面図であり、(Ｂ)，(Ｃ)は、(Ａ)のＡ−Ａ
線，Ｂ−Ｂ線断面図である。本実施例２において、半導
体装置３０は、正方セル３２のコ−ナ部３３を多角形状
の凸状にしたものである。これによって、Ｎ型ソ−ス層
７の幅(ソース幅)を大きくとることができ、約５％程度
のＲｏｎ低減が図れるという利点を有する。なお、この
半導体装置３０のコ−ナ部３３以外の部分は従来と同様
であり、詳細な説明は省略する。(Embodiment 2) FIG. 2 shows another embodiment of the present invention.
7A and 7B are diagrams showing (Embodiment 2), in which (A) is a plan view of the semiconductor device, and (B) and (C) are AA of (A).
It is a sectional view taken along line BB. In the second embodiment, a semiconductor device 30 has a corner portion 33 of a square cell 32 having a polygonal convex shape. As a result, the width (source width) of the N-type source layer 7 can be increased, and there is an advantage that Ron can be reduced by about 5%. Note that portions of the semiconductor device 30 other than the corner portion 33 are the same as in the related art, and a detailed description thereof will be omitted.
【００２３】[0023]
【発明の効果】本発明は、以上詳記したとおり、ベ−ス
コ−ナ部を凸状とすることにより、空乏層のつながりを
均一化することができ、これによって、部分的なブレ−
クダウンを防止して破壊耐量を向上させることができる
という効果が生じる。According to the present invention, as described above in detail, the connection of the depletion layer can be made uniform by forming the base corner portion in a convex shape.
This has the effect of preventing breakdown and improving the breakdown strength.
【図１】本発明の一実施例(実施例２)を示す図であっ
て、(Ａ)はその半導体装置の平面図であり、(Ｂ)，(Ｃ)
は、(Ａ)のＡ−Ａ線，Ｂ−Ｂ線断面図である。FIG. 1 is a view showing one embodiment (Embodiment 2) of the present invention, wherein (A) is a plan view of the semiconductor device, and (B), (C)
FIG. 2 is a sectional view taken along line AA and line BB in FIG.
【図２】本発明の他の実施例(実施例２)を示す図であっ
て、(Ａ)はその半導体装置の平面図であり、(Ｂ)，(Ｃ)
は、(Ａ)のＡ−Ａ線，Ｂ−Ｂ線断面図である。FIGS. 2A and 2B are diagrams showing another embodiment (Embodiment 2) of the present invention, wherein FIG. 2A is a plan view of the semiconductor device, and FIGS.
FIG. 2 is a sectional view taken along line AA and line BB in FIG.
【図３】従来の半導体装置の工程Ａ〜工程Ｂからなる製
造工程順断面図である。FIG. 3 is a cross-sectional view of a conventional semiconductor device in the order of manufacturing steps including steps A and B.
【図４】従来の半導体装置の構造を説明する図であっ
て、(Ａ)はその平面図であり、(Ｂ)，(Ｃ)は、(Ａ)のＡ
−Ａ線，Ｂ−Ｂ線の断面図である。4A and 4B are diagrams illustrating the structure of a conventional semiconductor device, wherein FIG. 4A is a plan view thereof, and FIGS. 4B and 4C are diagrams of FIG.
It is sectional drawing of the -A line and the BB line.
１ Ｎ型半導体基板 ２ Ｎ型エピ ３ ゲ−ト酸化膜 ４ ポリシリコン ５ Ｐ型ベ−ス層 ６ Ｐ+ベ−ス層 ７ Ｎ型ソ−ス層 ８ 層間絶縁膜 ９ ソ−ス電極 １０ 裏面電極 １１ 空乏層 １２ 正方セル ２０，３０ 半導体装置 ２２，３２ 正方セル ２３，３３ コ−ナ部DESCRIPTION OF SYMBOLS 1 N-type semiconductor substrate 2 N-type epi 3 Gate oxide film 4 Polysilicon 5 P-type base layer 6 P + base layer 7 N-type source layer 8 Interlayer insulating film 9 Source electrode 10 Back surface Electrode 11 Depletion layer 12 Square cell 20, 30 Semiconductor device 22, 32 Square cell 23, 33 Corner
Claims (3)
二の導電型のベ−ス層を有し、該ベ−ス層中に前記第一
の導電型のソ−ス層を有する半導体装置において、前記
ベ−ス層のコ−ナ部が凸状になっていることを特徴とす
る半導体装置。A semiconductor device having a first conductivity type has a base layer of a second conductivity type on a semiconductor substrate having the first conductivity type, and has a source layer of the first conductivity type in the base layer. In a semiconductor device, a corner portion of the base layer has a convex shape.
を特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein said corner portion has an arcuate convex shape.
とを特徴とする請求項１に記載の半導体装置。3. The semiconductor device according to claim 1, wherein said corner portion has a polygonal convex shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8219769A JP2991123B2 (en) | 1996-08-21 | 1996-08-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8219769A JP2991123B2 (en) | 1996-08-21 | 1996-08-21 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1065158A true JPH1065158A (en) | 1998-03-06 |
| JP2991123B2 JP2991123B2 (en) | 1999-12-20 |
Family
ID=16740724
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8219769A Expired - Fee Related JP2991123B2 (en) | 1996-08-21 | 1996-08-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2991123B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019517150A (en) * | 2016-05-23 | 2019-06-20 | ゼネラル・エレクトリック・カンパニイ | Electric field shielding in silicon carbide metal oxide semiconductor (MOS) device cells using body region extensions |
| CN117690968A (en) * | 2024-02-02 | 2024-03-12 | 深圳天狼芯半导体有限公司 | MOS tube and preparation method thereof |
-
1996
- 1996-08-21 JP JP8219769A patent/JP2991123B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019517150A (en) * | 2016-05-23 | 2019-06-20 | ゼネラル・エレクトリック・カンパニイ | Electric field shielding in silicon carbide metal oxide semiconductor (MOS) device cells using body region extensions |
| CN117690968A (en) * | 2024-02-02 | 2024-03-12 | 深圳天狼芯半导体有限公司 | MOS tube and preparation method thereof |
| CN117690968B (en) * | 2024-02-02 | 2024-05-28 | 深圳天狼芯半导体有限公司 | MOS tube and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2991123B2 (en) | 1999-12-20 |
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