JPH1065101A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable ensuring a required electric capacity and further reducing by the area of occupation of a capacitive element and thus the size of a device forming electrode sections in proximity to each other in a layer-insulating film, and forming a capacitance at least between the electrode sections to form the capacitive element. SOLUTION: Base wirings 31, 32 are located on a layer insulating film that covers field-effect transistors and other elements, and a layer-flatting film 21 covers the base wirings. Capacitor electrodes 34, 34 and a buried contact electrode 35, connected with the base traces 31, 32, respectively, are buried in the layer flattening film 21, and upper layer wirings 36, 36, 37 are connected with the top of the capacitor electrodes and buried contact electrode, respectively. There is a pair of electrodes obtained by combining the base wirings 32, the buried capacitor electrode 34 and the upper layer wirings 36, and the pair of the electrodes constitutes a capacitive element. In the capacitive element, the pair of the electrodes is formed in the vertical direction and has a capacitance on the sides of the base wirings 32, the buried capacitor electrodes 34 and the upper layer wiring 36.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a capacitance element.

[0002]

2. Description of the Related Art In a semiconductor device such as an A / D converter that requires a large-capacity, high-withstand-voltage capacitive element (capacitor), a reduction in the size of the capacitive element and a corresponding reduction in the overall size of the device have become major issues. I have.

As a configuration of a capacitive element, polysilicon-
A capacitive element has been formed using parallel plate electrodes of aluminum, aluminum-aluminum, or the like.

[0004]

In recent semiconductor devices, the interlayer film is often flattened to enable fine processing. As a result, the interlayer film thickness tends to increase. Further, in order to prevent the processing speed of the device from being lowered, a structure using an interlayer film which reduces the electric capacity between layers has been adopted.

[0005] Under such circumstances, in order to form a capacitor composed of parallel plate type electrodes as described above,
A considerable electrode size is required to secure the required electric capacity, which hinders a reduction in the size of the device. Accordingly, it is an object of the present invention to reduce the area occupied by a capacitor in a semiconductor device having the capacitor while securing required electric capacity, and to reduce the size of the device.

[0006]

In order to achieve the above object, the present invention provides a capacitor having a structure in which electrode portions which are close to each other are provided in an interlayer insulating film and a capacitor is formed at least between the electrode portions. A semiconductor device is provided.

[0007] In the semiconductor device of the present invention, electrodes constituting a capacitive element are three-dimensionally arranged in an interlayer insulating film. The facing direction of the paired electrodes can be vertical or horizontal. The spatially vacant area can be effectively utilized, and the required capacitance can be secured by arranging the electrodes themselves three-dimensionally, so that the area occupied by the capacitor can be reduced.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to the present invention will be described. First Embodiment FIG. 2E shows a first embodiment of the capacitive element according to the semiconductor device of the present invention.
It is sectional drawing which shows embodiment.

The underlying wirings 31 and 32 are provided on the substrate on which the field-effect transistors and other elements are formed, or on the interlayer film covering those elements, and the interlayer planarizing film 21 is provided so as to cover the underlying wirings. . Buried capacitor electrodes 34 and 34 and buried contact electrodes 35 connected to the underlying wirings 31 and 32, respectively, are buried in the interlayer flattening film, and upper wirings 36, 36 and 37 are formed thereon.
Are connected respectively. A pair of electrodes formed by combining the base wiring 32, the buried capacitor electrode 34, and the upper wiring 36 forms a capacitive element in the drawing.

This capacitive element has a pair of electrodes formed in the vertical direction, and has capacitance on the side surfaces of the underlying wiring, the buried capacitor electrode, and the upper wiring. Therefore, the area occupied by the capacitor can be reduced while securing the necessary electric capacity. Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. First, FIG.
The process leading to (a) will be described. Form a field effect transistor by forming a gate electrode, etc. on a substrate, and a diffusion layer, etc. in the substrate, or form a bipolar transistor or other element by the same means, on the same substrate plane or on the electrodes of those transistors. Underlayer wirings 31 and 32 made of a conductor such as aluminum are provided on an interlayer film that is coated and planarized. In the figure, the display of elements such as a substrate and a transistor is omitted. The underlying wiring 31 may be connected to the diffusion layer or may be connected to another electrode. Two underlying wirings 3
2, 32 are insulated from each other. These underlying wirings 3
The interlayer flattening film 21 is formed by reflowing or etching back PSG or BPSG so as to cover 1 and 32. Resist R having capacitor hole pattern 1 and contact hole pattern 2 on interlayer planarization film 21
Form one.

Next, as shown in FIG. 1B, anisotropic etching such as RIE (reactive ion etching) is performed along the resist R1 to simultaneously open the capacitor hole PH and the contact hole CH. Underlay wiring 3
The surfaces of 1, 32 are exposed. Next, as shown in FIG. 1C, after removing the resist R1, a conductor such as tungsten is CVD-formed to form a buried wiring layer 33, and the capacitor hole PH and the contact hole CH are buried with the conductor.

Next, as shown in FIG. 2D, the buried wiring layer 33 is etched back to form buried capacitor electrodes 34, 34 and a buried contact electrode 35. Next, as shown in FIG. 2E, the buried capacitor electrodes 34 and 34 and the buried contact electrode 35 are formed.
Are formed by sputtering a conductor such as aluminum.
As a result, the underlying wiring 32, the embedded capacitor electrode 3
A pair of capacitor electrodes composed of the upper layer wiring 4 and the upper layer wiring 36 can be formed, and a capacitive element having capacitance on the side surfaces thereof is completed.

In this embodiment, a pair of electrodes is formed.
Multiple electrodes can be formed as needed. In this embodiment, since a resist having a capacitor hole pattern and a contact hole pattern is formed on the interlayer flattening film, the capacitor hole and the contact hole can be simultaneously opened. No mask is required. Also, the step of burying the buried capacitor electrode can be performed simultaneously with the burying of the contact plug. As described above, since it is not necessary to add a special process for forming the capacitor, the capacitor can be formed while suppressing the manufacturing cost.

Second Embodiment FIG. 4E shows a second embodiment of the capacitive element according to the semiconductor device of the present invention.
It is sectional drawing which shows embodiment. Base wirings 31 and 32 are provided on a substrate on which a field effect transistor and other elements are formed, or on an interlayer film covering those elements, and an interlayer flattening film 21 is provided so as to cover the base wiring. Buried capacitor electrodes 34 and 34 and a buried contact electrode 35 are buried in the interlayer flattening film, and upper wirings 36, 36 and 37 are connected to the upper portions thereof. The buried capacitor electrodes 34 are buried so as not to penetrate the interlayer flattening film 21, while the buried contact electrode 35 is connected to the underlying wiring 31 through the interlayer flattening film 21. Embedded capacitor electrode 3
In the drawing, there is a pair of electrodes formed by combining the upper layer wiring 4 and the upper layer wiring 36 to form a capacitive element.

As in the first embodiment, the capacitive element of this embodiment has a pair of electrodes formed in the vertical direction, and has capacitance on the side of the embedded capacitor electrode and the upper wiring.
Therefore, the area occupied by the capacitor can be reduced while securing the necessary electric capacity. Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. The process up to FIG. 3A is the same as the process up to FIG. 1A of the first embodiment. However, the underlying wiring 3
2 may be omitted, and only the capacitor hole pattern 1 is patterned in the resist R2.

Next, as shown in FIG. 3B, a hole PH for a capacitor is opened by anisotropic etching. At this time, if the underlying wiring 32 is present, the etching is terminated before it is exposed. If there is no underlying wiring 32, the etching is stopped to the extent that the interlayer flattening film 21 does not penetrate.

Next, as shown in FIG. 3C, the resist R2 is removed, a resist R3 in which only the contact hole pattern 2 is patterned is formed, and a contact hole CH is opened by anisotropic etching. To expose. Next, as shown in FIG.
3 is removed, a buried wiring layer is formed by CVD of a conductor such as tungsten, and then the buried wiring layer is etched back to form buried capacitor electrodes 34 and 34 and a buried contact electrode 35.

Next, as shown in FIG. 4E, upper wirings 36, 36 and 37 connected to the buried capacitor electrodes 34 and 34 and the buried contact electrode 35, respectively, are formed by sputtering a conductor such as aluminum. As a result, a pair of capacitor electrodes including the buried capacitor electrode 34 and the upper layer wiring 36 can be formed, and a capacitive element having a capacitance on these side surfaces is completed.

In this embodiment, a pair of electrodes is formed.
Multiple electrodes can be formed as needed. This capacitor electrode can form a capacitor in a desired region irrespective of the presence or absence of a lower underlying wiring, and can be formed easily by using only a single-layer wiring.

Third Embodiment FIG. 6E is a sectional view showing a third embodiment of the capacitor according to the semiconductor device of the present invention. Base wirings 31 and 32 are provided on a substrate on which a field effect transistor and other elements are formed, or on an interlayer film covering those elements, and an interlayer flattening film 21 is provided so as to cover the base wiring.
The embedded capacitor electrodes 34a and 34 are provided in the interlayer planarization film.
b and 34c and a buried contact electrode 35 are buried, and upper layers 36 and 37 are respectively connected to the upper portions thereof. Embedded capacitor electrodes 34a, 34b,
34 c is buried so as not to penetrate the interlayer planarization film 21, that is, so as not to be connected to the underlying electrode 32, while the buried contact electrode 35 is connected to the underlying wiring 31 through the interlayer planarization film 21. . An electrode formed by combining the buried capacitor electrodes 34a, 34b, 34c and the upper layer wiring 36 and the underlying wiring 32 form a pair of electrodes to form a capacitance element.

In this capacitive element, an upper electrode formed by projecting a buried capacitor electrode on the lower surface of an upper wiring and a flat lower electrode are formed so as to face each other up and down. With Since the surface area is increased by the unevenness formed on the lower surface of the upper electrode, the occupied area of the capacitor can be reduced while securing the necessary electric capacity.

Next, a method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. FIG.
The process up to (a) is the same as the process up to FIG. 1A of the first embodiment. However, resist R2
Only the capacitor hole pattern 1 is patterned.

Next, as shown in FIG. 5B, a hole PH for a capacitor is opened by anisotropic etching. At this time, the etching is completed before the underlying wiring 32 is exposed. Next, as shown in FIG. 5C, the resist R2 is removed, a resist R3 in which only the contact hole pattern 2 is patterned is formed, a contact hole CH is opened by anisotropic etching, and the underlying wiring 31 is exposed. .

Next, as shown in FIG. 6D, the resist R3 is removed, a conductor such as tungsten is CVD-formed to form a buried wiring layer, and the buried wiring layer is etched back to form a buried capacitor electrode. 34a, 34b, 3
4c and the buried contact electrode 35 are formed.

Next, as shown in FIG. 6E, upper wirings 36 connected to the buried capacitor electrodes 34a, 34b, 34c and the buried contact electrodes 35, respectively.
37 is formed by sputtering a conductor such as aluminum. As a result, a capacitor electrode composed of three buried capacitor electrodes 34a, 34b, 34c and an upper layer wiring 36 is formed, and this electrode and the underlying wiring 32 under the electrode form a pair of electrodes, and a capacitive element having capacitance on the side surfaces thereof Is completed.

In this embodiment, three embedded capacitor electrodes are formed, but a large number can be formed if necessary. Further, the embedded capacitor electrode is formed in a hole opened in a groove shape, but may be formed in another form such as increasing the surface area to increase the electric capacity. In the method for manufacturing a semiconductor device according to the present embodiment, the shape of the upper layer electrode is not changed from other wiring shapes, and the step is not changed, so that the compatibility with the subsequent process is good.

Fourth Embodiment FIGS. 7 to 9 are views showing a fourth embodiment of a method of manufacturing a capacitor according to the present invention. FIG. 7 is a cross-sectional view illustrating a structure of a capacitor according to the semiconductor device of the present invention.
It has a structure in which four parallel plate type electrodes are vertically arranged, and a lower electrode a made of a conductor such as aluminum,
b, c, d and upper electrodes A, B, C, D are arranged in the insulating film. The lower electrodes a and c and the upper electrodes B and D conduct to function as one electrode, and the lower electrodes b and d and the upper electrodes A and C are also the same. A total of eight electrodes constitute a pair of electrodes. Thus, a capacitive element is formed. The eight electrodes can have capacitances on the side surfaces of the electrodes adjacent vertically and horizontally, respectively, and eventually become capacitance elements equivalent to the circuit diagram shown in FIG.

As shown in FIG. 7, each lower electrode has a width I and a height M, the upper electrode has a width I and a height K, and the distance between the lower electrodes and the distance between the upper electrodes are J. If the distance between the lower electrode and the upper electrode is L, and the dielectric constant is uniform in the lower electrode region and the upper electrode region,
The electric capacity C of the system is represented by C = Z ((K + M) / J + I / L) (1) Here, Z is a proportional constant including the dielectric constant of the system. On the other hand, when the capacitance element is formed in the same occupied area by the conventional parallel plate type electrode, the electric capacitance C ′ of the system is represented by C ′ = Z (J / L + I / L) (2) Therefore, when (K + M) / J> J / L (3), the capacitance element of the present embodiment can effectively increase the capacitance in a smaller area than the conventional parallel plate capacitance element. This condition corresponds to the interlayer planarization film 2 shown in FIG.
When the dielectric constant of the protective insulating film 22 is not equal to 1 and the dielectric constant of the protective insulating film 22 is E times larger, for example, (E * K + M) / J> J / L (4)

The method of manufacturing the capacitive element of this embodiment is substantially the same as the method of manufacturing the capacitive element of the first to third embodiments. Interlayer planarization film 2 after lower electrode formation a, b, c, d
1 is deposited, a conductive film is deposited on the upper surface thereof, and is formed by etching like upper electrodes A, B, C and D. afterwards,
A protective insulating film 22 such as silicon oxide is formed by CVD so as to protect the upper electrode. The upper electrode may be formed so as to open and bury an electrode hole in the interlayer planarization film 21. In FIG. 7, four electrodes are formed on each of the upper and lower electrodes. However, the number of electrodes is not particularly limited as long as there are a plurality of upper and lower electrodes.

As described above, the capacitance element of this embodiment is
A capacitance element having a larger capacity than that of the conventional parallel plate type can be manufactured by the same simple process as that of the conventional parallel plate type capacitance element. FIG. 9 shows the structure of an example of the capacitor of this embodiment. In this figure, the illustration of the insulating layer covering the entire capacitive element is omitted. Lower electrode a,
c and the upper electrodes B and D are electrically connected by the connection portion 38 to function as one electrode, and the lower electrodes b and d
And the upper electrodes A and C are the same. The boundaries between the individual electrodes and the connections are not shown. A material having conductivity can be used for the connection portion, and the same material as the electrode or a different material may be used.

The present invention is not limited to the above embodiment. For example, a conductive material such as aluminum, tungsten, or polysilicon can be used for the base electrode 32, the embedded capacitor electrode 34, and the upper wiring 36. Various other changes can be made without departing from the spirit of the present invention.

[0032]

According to the semiconductor device having the capacitance element of the present invention, a problem such as a reduction in processing speed does not occur.
Furthermore, the area occupied by the capacitor can be reduced while securing the necessary capacitance.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a method for manufacturing a capacitor according to a semiconductor device of the present invention. FIG. 1A shows a process up to a resist forming process for forming a capacitor hole and a contact hole. ) Shows the steps up to the step of opening the capacitor holes and contact holes, and (c) shows the steps up to the step of depositing the conductor.

FIG. 2D is a cross-sectional view showing a step that follows the step shown in FIG. 1, and shows up to the step of removing a conductor other than the buried electrode portion by etching, and FIG. 2E is a semiconductor device of the present invention; FIG. 2 is a sectional view showing a capacitive element according to the first embodiment, and FIG.
The process up to the process of forming the upper layer wiring following the process (d) is shown.

3A and 3B are cross-sectional views illustrating a manufacturing process of a method for manufacturing a capacitor according to the semiconductor device of the present invention. FIG. 3A illustrates a process up to a resist forming process for forming a capacitor hole.
(B) shows up to the step of opening a capacitor hole, and (c) shows up to the step of opening a contact hole.

FIG. 4D is a cross-sectional view showing a step subsequent to that of FIG. 3, and shows a step of removing the conductor other than the buried electrode portion by depositing and etching the conductor, and FIG.
FIG. 4 is a cross-sectional view showing a capacitor according to the semiconductor device of the present invention, and shows a process following the process shown in FIG.

FIG. 5 is a cross-sectional view showing a manufacturing process of a method of manufacturing a capacitive element according to a semiconductor device of the present invention. FIG. 5A shows a process up to a resist forming process for forming a capacitor hole.
(B) shows up to the step of opening a capacitor hole, and (c) shows up to the step of opening a contact hole.

FIG. 6D is a cross-sectional view showing a step subsequent to that of FIG. 5, and shows a step of removing the conductor other than the buried electrode portion by depositing and etching the conductor, and FIG.
FIG. 6 is a cross-sectional view showing a capacitor according to the semiconductor device of the present invention, and also shows a process following the process shown in FIG.

FIG. 7 is a cross-sectional view illustrating a structure of a capacitor according to a semiconductor device of the present invention.

FIG. 8 is a circuit diagram equivalent to the semiconductor device shown in FIG. 7;

FIG. 9 is a perspective view showing the structure of one embodiment of a capacitor according to the semiconductor device of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Capacitor hole pattern, 2 ... Contact hole pattern, 21 ... Interlayer flattening film, 22 ... Protective insulating film,
31, 32: Underlying wiring, 33: Embedded wiring layer, 34 ...
Embedded capacitor electrode, 35 embedded contact electrode, 36, 37 upper wiring, 38 electrode connection portion, a,
b, c, d: lower electrode, A, B, C, D: upper electrode, P
H: hole for capacitor, CH: contact hole, R
1, R2, R3 ... resist

Claims (6)

[Claims] 1. A semiconductor device comprising: a capacitor element provided with electrode portions close to each other in an interlayer insulating film and forming a capacitor between at least the electrode portions. 2. The semiconductor device according to claim 1, further comprising a capacitor formed between said electrode portion and an adjacent wiring layer. 3. The semiconductor device according to claim 1, wherein said electrode portion penetrates through said interlayer insulating film and is connected to a wiring layer below said interlayer insulating film. 4. The semiconductor device according to claim 1, wherein said electrode portion has a buried electrode filling a recess dug in said interlayer insulating film. 5. The semiconductor according to claim 1, wherein two or more electrode portions adjacent to each other are arranged above and below the interlayer insulating film, and a capacitance is formed between the adjacent electrode portions and between the upper and lower electrode portions. apparatus. 6. A buried electrode formed in a concave portion dug from above the interlayer insulating film and a lower electrode existing below the interlayer insulating film, and between the buried electrode and the lower electrode. 2. The semiconductor device according to claim 1, wherein a capacitor is formed.