JPH1063575A - Cache memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cache memory capable of processing consecutive storing instructions into a pipeline by one clock cycle. SOLUTION: The cache memory is provided with a first memory 11 storing cache data 11a, a second memory 12 storing tag data 12b and a valid bit 12a showing whether cache data is valid or not in one entry, a third memory 13 housing a dirty bit 13a showing whether or not cache data in the first memory is updated, address decoders 15 and 16 individually provided in each of the second and third memories, and a cache controller 17 simultaneously executing the writing of the dirty bit to the third memory and the reading of a tag in the second memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory, and more particularly, to providing a cache memory which enables continuous store instructions to be pipelined in one clock cycle.

[0002]

2. Description of the Related Art Heretofore, this type of write-back type cache memory has been used for the purpose of pipeline processing instructions at clock cycle periods. Less than,
A conventional write-back cache memory will be described with reference to the drawings.

FIG. 5 is a block diagram showing a first conventional example of a general write-back type cache memory. In FIG. 5, reference numeral 78 denotes an address bus, and 79 denotes a data bus. The first memory 71 stores cache data 71a, and the second memory 72 stores dirty bits 72a, valid bits 72b, and tags 72c, respectively.

The valid bit 72b is provided in the first memory 71
Is a flag memory for storing information indicating that the data stored in the data is valid data.

The dirty bit 72a is a flag memory for storing information indicating whether or not the cache data has been updated and does not match the external memory. here,
When the cache data is updated, the dirty bit 72a holds active high (HIGH).

The cache controller 84 includes a dirty bit signal 82, a valid bit signal 83, a tag signal 8
4 to and from the second memory 72, and outputs a cache hit signal 81 indicating whether or not a cache hit has occurred. Here, it is assumed that when a cache hit occurs, the cache hit signal 81 is set to active high (HIGH).

The operation of the first conventional example shown in FIG. 5 will be described. First, a case where the data at the address A0 is read from the first memory 71 will be described. According to the address A0 on the address bus 78, the tag 72c, the valid bit 72b, and the dirty bit 72a of the entry A0 are transmitted from the second memory 72 to the tag signal 84, the valid bit signal 8
3. The data is read out to the cache controller 84 via the dirty bit signal 82. Cache controller 8
4 compares the tag 72c with the address A0 and generates a cache hit signal 81.

If a cache miss has occurred, a cache replacement process is performed. In the case of a cache hit, if the dirty bit 72a is HIGH, the cache data 71a has been updated, so the cache data is written back to the external memory and cache replacement is performed. If there is a cache hit and the dirty bit 72a is not HIGH, the first memory 71
From the cache data.

Next, an operation in the case where two store instructions for writing data to the cache memory successively cause a cache hit will be described.

Here, consecutive store instructions are referred to as store instruction A and store instruction B. FIG. 6 is a diagram showing a pipeline operation of successive store instructions in the cache memory shown in FIG. Here, TAG (R) is tag 7
2C, D (R) reads the dirty bit 72a, HIT generates the cache hit signal 81, D
data (W) is the write of the cache data 71a;
(W) indicates writing to the dirty bit 72a.

In the stage (1), the tag 72c and the dirty bit 72a relating to the store instruction A are read. In the stage (2), the tag 72 read in the stage (1)
The cache hit signal 81 is generated by comparing c with the address.

In stage (3), store data is stored in the first
Write to the memory 71 and set the dirty bit 72a to HIG
Write H. Here, the tag 72c and the dirty bit 7
Since 2a is stored in the same second memory 72, the tag 72c relating to the store instruction B cannot be read during writing to the dirty bit 72a relating to the store instruction A. Therefore, the reading of the tag 72c related to the store instruction B must be waited until the stage (5). As a result, three clocks are required to execute two consecutive store instructions.

A cache memory of a second conventional example which solves the above problem is disclosed in Japanese Patent Laid-Open No. Hei 5-314007. This second conventional example discloses a technique in which successive store instructions are pipelined at a clock cycle period by providing two dirty bit cells in one line.

FIG. 7 is a circuit diagram showing a dirty bit of the write-back type cache memory of the second conventional example. This cache memory is a direct-mapped cache memory, and its clock is a two-phase clock.

In the figure, 90 is a precharge circuit for precharging a bit line, and 105 is a second charge of a two-phase clock.
A phase clock (ph2), 106 is a first phase clock (ph1) of a two-phase clock, and 107 is a clock (xph2) obtained by inverting the second phase clock (ph2) 105, 1
04 is a cache hit signal, and 102 is write data for a dirty bit. Further, reference numeral 91 denotes a storage circuit for holding a dirty bit indicating update of data connected to the word line WL0 and bit line B corresponding to the 0th cache line of the cache memory and its inverted bit XB, and 110 and 111 denote tag memories. A cell 96 is a first memory cell of the storage circuit 91, and a reference numeral 92 is a second memory cell of the storage circuit 91.

The operation of the cache memory of the second embodiment configured as shown in FIG. 7 will be described. When the clock (xph2) 107 is LOW, the bit lines B and XB are precharged to HIGH. Phase 2 clock (ph
2) The row address given to the cache when 105 is HIGH is decoded, and the second phase clock (ph
2) When 105 is LOW, only one of the plurality of word lines is valid, and a dirty bit entry of one cache line is selected.

Here, it is assumed that word line WL0 is selected. When information from the dirty bit is read, the information of the dirty bit held in the first memory cell 96 is read out to the bit lines B and XB and taken out. on the other hand,
There are two types of writing information to dirty bits.

First, when a cache miss occurs in a store operation to a cache, when data transferred from an external memory is replaced with a cache line, information is written to a dirty bit simultaneously with update of store data. . This operation is performed by applying the write data 102 to the bit lines B and XB, and
Write to.

The second is to set a dirty bit when a cache hit occurs for a store operation to the cache. First phase clock (phl) 106 is H
When HIGH, the HIGH of the selected word line WL0
Is transmitted through the transistor 93, and the second memory cell 92 holds HIGH. HIGH of the cache write hit signal 104 and the second phase clock (ph
2) High of 105 is input to AND gate 101 and H
Generate IGH. The HIGH held in the second memory cell 92 and the output HIGH of the AND gate 101 are input to the NAND gate 98 to obtain LOW. This NAND Gate 1
The output LOW of 01 is input to the NAND gate 97, the output is set to HIGH, and this information is held via the inverter 108. Therefore, the dirty bit information of the first memory cell 96 is set to "1" indicating data update.

FIG. 8 is an explanatory diagram of a pipeline operation of a store instruction in the cache memory of the second conventional example. A case where two store instructions for writing data to the cache memory successively cause a cache hit will be described. Here, a write hit operation is shown as store instruction A and store instruction B.

TAG (R) reads the tag, D (R)
Indicates reading of a dirty bit, DATA (W) indicates writing of store data, and D (W) indicates writing of a dirty bit.

In the stage (1), the tag and the dirty bit relating to the store instruction A are read. The tag is compared with the address given to the cache to obtain a write hit signal. In stage (2), the bit line is precharged and the dirty bit is written at the same time before the store data is written to the data portion of the cache. In stage (3), store data is written and a tag and a dirty bit related to a store instruction B, which is the next access, are read by a write enable signal obtained from a write hit signal.

In the stage (4), the bit line is precharged and the dirty bit is written at the same time before the store data is written in the data portion of the cache. The subsequent operation of the store instruction B is the same as the operation of the store instruction A in the stages (3) and (4).

[0024]

The above-mentioned conventional cache memory has the following problems.

First, in the configuration of the first prior art, when a continuous store instruction is operated in a pipeline manner, a store instruction can be performed only in two clock cycles with a stop cycle of one cycle. There is a problem that it decreases. The reason is that reading of the tag and writing of the dirty bit cannot be performed at the same time.

Second, the second conventional technique has a problem that it is difficult to increase the speed, that is, to increase the clock frequency. The reason is that, in order to transfer the value held in the second dirty bit memory cell to the first dirty bit memory cell during the precharge period, the precharge period can be shortened, that is, one clock cycle can be shortened. This is because it is difficult to do so.

Third, the configuration of the cache memory shown in the second prior art also has a problem that the circuit area becomes large because two dirty bit memory cells are required.

A first object of the present invention is to solve the above-mentioned conventional problems and to provide a cache memory which enables continuous store instructions to be pipelined in one clock cycle.

A second object of the present invention is to provide a cache memory capable of easily realizing high speed by shortening a clock cycle.

A third object of the present invention is to provide a cache memory that does not require an additional memory for saving write data when writing a dirty bit and reading a tag simultaneously.

[0031]

According to the present invention, there is provided a cache memory comprising: a first memory for storing cache data; a tag data in one entry; and a valid bit indicating whether the cache data is valid or not. , A third memory for storing a dirty bit indicating whether or not cache data of the first memory is updated, and a second memory and a third memory, respectively. , And control means for simultaneously writing a dirty bit to the third memory and reading a tag from the second memory.

According to a second aspect of the present invention, there is provided a cache memory comprising:
When a first store instruction and a second store instruction for writing data to the first memory cause a cache hit, the control unit reads the tag data relating to the first store instruction, and writes the read tag data and the write data. A first stage in which an address is compared to generate a cache hit signal and read the dirty bit, a second stage in which only a precharge process is performed,
A third stage in which writing of the dirty bit to the third memory and writing of the tag data relating to the second store instruction from the second memory at the same time as writing the dirty bit to the third memory; A fourth stage for performing only the charging process, a fifth stage for performing the writing of data to the first memory and the dirty bit to the third memory, and a sixth stage for performing only the precharging process. And a pipeline operation of one clock cycle composed of the stages described above.

According to a third aspect of the present invention, there is provided a cache memory comprising:
A first memory for storing, for each entry, cache data and a dirty bit indicating whether or not the cache data has been updated; and a second memory for storing tag data and a valid bit indicating whether the cache data is valid in one entry. 2, an address decoder separately provided in each of the first memory and the second memory, and writing of a dirty bit to the first memory and the second memory.
It is characterized by comprising control means for simultaneously reading tags from the memory.

According to a fourth aspect of the present invention, there is provided a cache memory comprising:
When a first store instruction and a second store instruction for writing data to the first memory cause a cache hit, the control unit reads the tag data relating to the first store instruction, and writes the read tag data and the write data. A first stage for comparing addresses to generate a cache hit signal and read the dirty bit, a second stage for performing only precharge processing, and writing data and the dirty bit to the first memory At the same time, a third stage for reading out the tag data relating to the second store instruction from the second memory, a fourth stage for performing only the precharge processing,
A fifth stage for writing the data and the dirty bit to the memory, and a sixth stage for performing only the precharge processing.
And a pipeline operation of one clock cycle composed of the stages described above.

[0035]

Embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a cache memory according to the present invention.

In FIG. 1, the cache memory according to the present embodiment includes a first memory 11, a second memory 12,
It comprises a memory 13, address decoders 14 to 16, and a cache controller 17. Here, reference numeral 18 denotes an address bus, and 19 denotes a data bus.

The first memory 11 stores cache data 11a.
Is stored. The second memory 12 stores a valid bit 12a and a tag 12b, and the third memory 13 stores a dirty bit 13a. Here, when the cache data 11a of the first memory 11 is updated, it is assumed that the dirty bit 13a holds active high (HIGH).

The second memory 12 and the third memory 13 have individual address decoders 15 and 16, respectively.
It is configured such that reading of b and writing to the dirty bit 13a can be performed simultaneously.

The cache controller 17 reads and writes the dirty bit signal 22 to and from the third memory 13, reads and writes the valid bit signal 23 and the tag signal 24 to and from the second memory 12, The hit signal 21 is output. Here, when a cache hit occurs, the cache hit signal 21 is set to active high (HIGH).

The operation of the cache memory according to the embodiment of the present invention shown in FIG. 1 will be described. When an instruction read A0 for reading cache data is executed, the cache data 11a is transferred from the first memory 11 to the second memory 1
2, the tag 12b and the valid bit 12a are simultaneously read from the third memory 13, and the dirty bit 13a is read from the third memory 13.

The cache controller 17 compares the read tag 12b with the address A0,
The cancel hit signal 21 is set to HIGH.

When a cache miss has occurred, if the dirty bit 13a is HIGH, the cache data 11a has been updated, so the cache data 11a is written back to the external memory, and then the cache replacement is started. If the dirty bit 13a is LOW, the cache replacement is started as it is.

If there is a cache hit, the cache data 11a in the first memory 11 is output to the outside.

When the instruction store A0 for writing the cache data 11a is executed, the tag 1
2b and the valid bit 12a are read. The cache controller 17 compares the read tag 12b with the address A0 to determine whether the cache hit signal 2
1 is generated.

If a cache miss has occurred, the dirty bit 13a is read from the third memory 13. If the dirty bit 13a is HIGH, the cache data 11a has been updated because the cache data 11a has been updated. , And start the cache replacement. If the dirty bit 13a is LOW, the cache replacement is performed as it is, the store data is written to the replaced entry of the first memory 11, and the third
HIGH is written to the dirty bit 13a of the memory 13.

If there is a cache hit, the store data is written to the replaced entry of the first memory 11 and at the same time, the dirty bit 13 of the third memory 13 is written.
Write HIGH to a.

Next, the operation when two consecutive store instructions for writing data to the cache memory cause a cache hit will be described. Here, two consecutive store instructions are referred to as a store instruction A and a store instruction B.

FIG. 3 is an explanatory diagram of a pipeline operation of a store instruction in the cache memory of the present invention. In FIG. 3, TAG (R) indicates reading of tag 12b and D
(R) is the reading of the dirty bit 13a, Data
(W) indicates writing to the cache data 11a, and D
(W) shows HIGH writing to the dirty bit 13a.

In the stage (1), the tag 12b relating to the store instruction A is read from the second memory 12, the read tag 12b is compared with the address, and the cache hit signal 21 is generated and the dirty bit 13a of the third memory 13 is read. Do.

In the stage (2), the bit lines are precharged. In stage (3), the store data is written to the cache data 11a, and the dirty bit 13a
Is written HIGH. Also, the dirty bit 13a
And the tag 12b relating to the store instruction B is read at the same time as the writing of the instruction.

In the stage (4), the bit lines are precharged. Store instruction B after stage (5)
Are the same as those in the stages (3) and (4) of the store instruction A.

As described above, the dirty bit 13a and the tag 12b are stored in the different second memory 12 and third memory 13, respectively, and the individual address decoders 15, 1
6 and writing of dirty bit 13a and tag 12
Since reading of b can be performed at the same time, continuous store instructions can be pipelined in one clock cycle.

Further, as described above, since no other operation is performed during the precharge period, the precharge period can be easily shortened, so that the operation frequency can be easily improved.

A first embodiment of the cache memory according to the present invention will be described with reference to FIG. In FIG. 2, a cache memory according to the present embodiment includes a first memory 31, a second memory 32, a third memory 33, and address decoders 34 to 3.
6, a cache controller 37, and a read / write controller 45. Here, 38 is an address bus, and 39 is a data bus.

The first memory 31 stores 4-word cache data 31a in one line. When reading the cache data 31a, the read / write controller 45 reads a line including the cache data 31a from the first memory 31 via the 128-bit bus 46,
By using two bits of the address bus 38, the cache data 31a is read from the four words of the read line.
And sends it out to the data bus 39.

When writing the cache data 31a,
The read / write controller 45 writes the data of the data bus 39 to the word of the first memory 31. The second memory 32 includes a valid bit 32a and a 20-bit tag 32.
b. The third memory 33 is dirty bit 3
3a is stored.

Here, when the cache data is updated, HIGH is held in the dirty bit 33a.

The second memory 32 and the third memory 33 have individual address decoders 35 and 36, respectively.
It is configured such that reading of b and writing to the dirty bit 33a can be performed simultaneously.

The cache controller 37 reads and writes the dirty bit signal 42 from the third memory 3.
3 and read and write the valid bit signal 43 and the 20-bit tag signal 44 in the second memory 3.
2 and outputs a cache hit signal 41. When a cache hit occurs, the cache controller 37 sets the cache hit signal 41 to HIGH.

The operation of the first embodiment shown in FIG. 2 will be described. When the instruction read A0 for reading the cache data 31a is executed, the cache data 31a is read from the first memory 31, the tag 32b and the valid bit 32a are read from the second memory 32, and the dirty bit 33a is read from the third memory 33 at the same time. It is.

The cache controller 378 compares the read tag 32b with the address A0, and generates the cache hit signal 41. If a cache miss has occurred, if the dirty bit 33a is HIGH, the cache data has been updated, so an entry including the cache data 31a is written back to the external memory, and then cache replacement is started. Dirty bit 33a is L
If it is OW, the cache replacement is started as it is. If there is a cache hit, the cache data 31a is output to the outside.

Next, a case will be described in which two store instructions (store instruction A and store instruction B) for writing data to the cache memory are consecutive and a cache hit occurs. In this case, the pipeline operation of the store instruction in the cache memory is performed in the same manner as in FIG. That is,
In the stage (1), the store instruction A from the second memory 32
Read out the tag 32b for the tag 32b
Then, the cache hit signal 41 is generated and the dirty bit 33 a is read from the third memory 33. In the stage (2), the bit lines are precharged. In stage (3), the store data is written to the cache data 31a of the first memory 31, and HIGH is written to the dirty bit 33a of the third memory 33.
The tag 3 relating to the store instruction B is stored in the second memory 32.
Read 2b. In the stage (4), the bit lines are precharged. Store instruction A after stage (5)
The operation by the store instruction B is performed in the same manner as in the stages (3) and (4).

The configuration of the cache memory according to the second embodiment of the present invention will be described with reference to FIG. In this embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

In the second embodiment, the first memory 5
Dirty bit 53a and cache data 51a are stored for each entry. by this,
An address decoder for cache data and an address decoder for dirty bits are combined into one address decoder 54.
Can be shared by

The first memory 51 and the second memory 32 have address decoders 54 and 15 respectively. Thus, reading of the tag 32b and writing of the dirty bit 53a can be performed simultaneously.

The cache data 51a of the second embodiment
The operation in the case of reading and writing the data and the operation in the case where two store instructions for writing data to the cache memory successively hit the cache are the same as those in the first embodiment.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to the contents of the above embodiments.

[0068]

As described above, according to the cache memory of the present invention, the following effects can be obtained.

First, a dirty bit and a tag are stored in different memories, and a separate address decoder is provided.
Since the writing of the dirty bit and the reading of the tag are performed at the same time, it is possible to pipeline the successive store instructions in one clock cycle, thereby improving the processing efficiency. That is, the store operation can be performed in one clock cycle without a stop cycle when a continuous store instruction is pipelined, and the performance of the cache memory can be improved.

Secondly, by performing no processing other than precharge during the precharge period of the bit line, the precharge time can be easily reduced by sizing the precharge circuit, and the speed can be increased, that is, the clock cycle can be shortened. Can be easily performed.

Third, since the dirty bit and the tag are stored in different memories and the individual address decoder is provided, the dirty bit and the tag are used to save the write data when writing the dirty bit and reading the tag at the same time. There is no need to add additional memory.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a cache memory according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a cache memory according to the first embodiment of the present invention.

FIG. 3 is a timing chart for explaining a pipeline operation in a case where two store instructions for writing data to the cache memory successively hit the cache memory according to the present invention;

FIG. 4 is a block diagram showing a configuration of a cache memory according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a cache memory according to a first conventional example.

FIG. 6 is a timing chart illustrating a pipeline operation in the cache memory of the first conventional example.

FIG. 7 is a block diagram showing a configuration of a cache memory according to a second conventional example.

FIG. 8 is a timing chart illustrating a pipeline operation in the cache memory of the second conventional example.

[Explanation of symbols]

 11, 31, 51 First memory 11a, 31a, 51a Cache data 12, 32 Second memory 12a, 32a Valid bit 12b, 32b Tag 13, 33 Third memory 13a, 33a, 53a Dirty bit 14, 15, 16 Address decoder 17, 37 Cache controller 34, 35, 36 Address decoder 45 Read / write controller 54, 55 Address decoder

Claims (4)

[Claims] A first memory for storing cache data; a second memory for storing tag data and valid bits indicating whether or not the cache data is valid in one entry; and a cache of the first memory. A third memory for storing a dirty bit indicating whether data has been updated, an address decoder individually provided in the second memory and the third memory, and a dirty memory for the third memory. A cache memory comprising control means for simultaneously writing a bit and reading a tag from the second memory. 2. When a first store instruction and a second store instruction for writing data to the first memory cause a cache hit, the control unit reads the tag data relating to the first store instruction,
A first stage for generating a cache hit signal and reading the dirty bit by comparing the read tag data with a write address, a second stage for performing only a precharge process, and transferring data to the first memory. A third stage of reading the tag data relating to the second store instruction from the second memory at the same time as writing the dirty bit and writing the dirty bit to the third memory; From a fourth stage for writing data to the first memory and writing a dirty bit to the third memory, and a sixth stage for performing only precharge processing. Become one
2. The cache memory according to claim 1, wherein a pipeline operation of a clock cycle is performed. 3. A first memory for storing, for each entry, cache data and a dirty bit indicating whether the cache data has been updated, and validity indicating whether or not the tag data and the cache data are valid in one entry. A second memory for storing bits; an address decoder separately provided in each of the first memory and the second memory; writing of a dirty bit to the first memory; and a tag of the second memory. A cache memory comprising control means for simultaneously performing reading. 4. When a cache hit occurs between a first store instruction and a second store instruction for writing data to the first memory, the control unit reads the tag data relating to the first store instruction,
A first stage for comparing the read tag data with a write address to generate a cache hit signal and read the dirty bit, a second stage for performing only a precharge process, and a data to the first memory. And the third bit for simultaneously reading the tag data relating to the second store instruction from the second memory while writing the dirty bit.
, A fourth stage for performing only precharge processing, a fifth stage for writing data and the dirty bit to the first memory, and a sixth stage for performing only precharge processing. 1
2. The cache memory according to claim 1, wherein a pipeline operation of a clock cycle is performed.