JPH1063564A - Hierarchical storage managing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a processing speed by simplifying processing at the time of writing to a memory. SOLUTION: A storage read and write means 40 sends a request for reading and writing information to a storage managing means 41. When the writing request is with respect to the area of a present level, the means 41 writes information in a storing means 45 as it is. In addition the means 41 sets an area with respect to a former level to be a writing prohibited area. When the writing request is with respect to the area set to by the writing prohibited area, an area storing and judging means 42 informs a changed history preparing means 43 that the area should be restored at the time of being restored. The means 43 prepares the history of variables to be changed in the area according to information from the means 42 and stores a changed history to a changed history storing means 44. After then the means 41 releases writing prohibition to write information the writing of which is requested in the means 45.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a page description language (PDL) for interpreting a page description language and generating output image data.
The present invention relates to a script language) processing system and relates to a hierarchical storage management device that performs memory management.

[0002]

2. Description of the Related Art As one of page description languages (PDL) for outputting to a raster output device such as a printer or a display, Po has been developed by Adobe in the United States.
There is stScript ™. The PostScri
In pt, apart from the conventional page description using a series of commands, in addition to advanced graphics operation instructions, control structures and abundant data types as programming languages, definition of procedures, operations, memory management mechanisms, etc. It has functions comparable to high-level languages, and is widely used as a de facto standard language because of its high descriptiveness and high functionality.

In recent years, the performance of printers has been improved. For black and white, the output speed is 135 ppm (page / min) at 600 dpi, and 400 dpi, 40 dpi for color.
With the emergence of high-speed printers with high image quality such as ppm, there is a large difference in throughput between raster image processing that interprets PDL and develops image data and printers that output image data. However, the PostScript described above
Is based on the use of the interpreter method and its high functionality, compared to the case where the same document is represented by another PDL.
The disadvantage is that the raster image processing takes a lot of time.

One of the relatively large loads in language processing in PostScript is a memory management mechanism. Hereinafter, a conventional memory management mechanism will be described. In the conventional memory management mechanism, an area called a virtual memory is defined as one of the storage areas. The virtual memory is a storage area that is leveled and managed in a hierarchical manner, and has a function of restoring to an arbitrary low-level memory state with a level in order to effectively use the limited storage area. By using this function, it is possible to invalidate a change of data in the virtual memory, for example, a rewrite of a variable, which is performed during the processing.

As described above, as a method for restoring the current storage area state to an arbitrary level of storage state,
Conventionally, a change history for a storage area required for restoration is created sequentially, and in response to a restoration request, the history is traced in reverse.
The parts changed sequentially are restored. That is, the conventional hierarchical storage management device has, for example, the configuration shown in FIG. 21. Before writing, the storage read unit 1 sequentially accesses the storage unit 6 from the lowest level, reads variables, and then , Area storage determination means 2
It is determined whether or not the area is to be restored at the time of restoration, in other words, whether or not the level is exceeded. Then, if it is necessary to restore, a history of changed variables is created by the change history creating means 3, and the change history is stored in the change history storage means 4. The storage writing unit 5 writes data based on the determination result by the area storage determination unit 2 and the change history created by the change history creation unit 3.

[0006]

However, in the conventional hierarchical storage management device, writing to a memory belongs to the most basic operation in a language processing system, and although it is an operation that frequently occurs during language processing. It is necessary to always judge at the time of writing, and consider that most of the writing performed at the time of job execution is writing that does not require history creation, that is, writing to an unsaved area. Then, there is a problem that the processing leads to an increase in cost and generates a lot of overhead.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a hierarchical storage management device capable of simplifying processing at the time of writing to a memory and improving the processing speed.

[0008]

In order to solve the above-mentioned problems, according to the present invention, newly written information and information before being rewritten due to storage of the newly written information are time-series. Storage means for storing information in different hierarchical levels, a prohibited area setting means for setting a write protected area based on a hierarchical level of information stored in the storage means, and an area set by the prohibited area setting means. On the other hand, when a write request is issued, a storage unit for storing information already written in the area in a predetermined area of the storage unit, and after the information already written is stored by the storage unit, Storage control means for controlling to store requested information in the storage means.

According to the present invention, each time the hierarchical level changes, the previous area is set as the write-inhibited area by the prohibited area setting means, and when a write request is issued to the area, the storing means is set. As a result, the information in the area is stored in a restorable manner, so that the processing at the time of writing to the memory can be simplified, and the processing speed can be improved.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

A. Configuration of Embodiment A-1. Document Processing System First, a document processing system using the hierarchical storage management device according to the present embodiment will be described. Here, FIG.
FIG. 2 is a block diagram illustrating a configuration example of the document processing system. In the figure, a host computer 9 converts a created document composed of a figure, a bitmap image, a character, and the like into a page description language (PDL) at the time of printout, and then converts the document into an Ethernet, a SCSI (Small Computer Sys- tem).
The image data is transmitted to the image data output control device 10 via a communication line such as a serial interface or a serial interface. The image data output control device 10 includes an input interface 11, a language interpretation / image processing unit (raster image processing: RIP).
12, a frame buffer 13 and an output interface 14. The input interface 11 inputs data from the host computer 9, temporarily stores the input data in an input buffer in the interface, and supplies the data to the language interpretation / image processing unit 12.
The language interpretation / image processing unit 12 interprets the PDL, generates raster image data (bitmap data), and supplies the raster image data to the frame buffer 13. The frame buffer 13 stores raster image data for one page that has been developed. The output interface 14 is connected to the frame buffer 13.
Output device (image output terminal: printer) 15 for raster image data developed in
Output to

A-2. Configuration of Language Interpretation / Image Processing Unit Next, the configuration of the above-described language interpretation / image processing unit 12 will be described. FIG. 3 is a block diagram illustrating a configuration of the language interpretation / image processing unit. The phrase decomposition unit 16 constructs a language from the PDL input from the input interface 11, and extracts a token composed of a series of characters. The phrase analysis unit 17 interprets the meaning of the character string of the extracted token and converts the data as an object into
Converts the data into a unified internal data structure along with types, attributes, and values. For example, the input stream “128” is converted into a character string “123” representing a token, and finally an object of integer type with a literal attribute and a value of 128 is created.

The execution processing / control unit 18 executes the above-mentioned object by calling a series of predetermined processing according to its type and attribute. For example, execution of an object having a literal attribute calls the stack unit 19 and stores the object on the operand stack. Further, the operator execution unit 20 executes an operator indicated by the name on an object of a name type having an executable attribute. Operators provide functions as ordinary languages such as logical operation, arithmetic operation, character string operation, control, and stack operation, and PDL-specific functions such as coordinate operation, character drawing, image drawing, and graphics drawing. There is something to offer. The operator usually takes out the data that is the argument of the operation as an argument from the operand stack, and if there is a return value, returns it to the stack unit 19. For example, "ad
The operator "d" retrieves two numerical values to be operated on from the operand stack, and after the operation, returns the result to the operand stack.

Next, the imaging unit 21 performs character drawing,
An operator who instructs a frame buffer such as an image drawing and a graphics drawing to perform drawing is executed. In the imaging unit 21, from the coordinate point information of the figure, bitmap, or character to be drawn,
Calculate the address on the frame buffer for drawing the bit string. Here, in the case of drawing a character, the font outline management unit 22 extracts the character code and the outline coordinate point information of the character corresponding to the font information. Next, the marking unit 23 performs writing to the frame buffer according to the information from the imaging unit 21 described above. In the course of these processes, the memory management unit 24 manages the necessary virtual memory area, and performs processing such as acquisition, writing, reading, and restoring the state of the virtual memory area.

A-3. Configuration of Image Data Output Device Next, the configuration of the above-described image data output device 10 will be described. Here, FIG. 4 is a block diagram showing a configuration of the image data output device. The address bus and control bus 25, the data bus 26, and the interrupt control signal 27 are signal lines for exchanging data between a CPU 35 described later and each interface described later. The interrupt control signal 27 is a signal for notifying the CPU 35 of various events generated from each interface or device. The input / output interface 28 is an interface for inputting the PDL generated by the client computer. In the present embodiment, the input / output interface 28 is a LAN (Local Area Network) such as an Ethernet or a serial line.
rk) Assumes interface in environment.

The ROM 29 stores a program. The address translation device 30 includes a memory management unit 3
1 and an address conversion table 32. The memory management unit 31 uses the information of the address conversion table 32 to transfer a virtual address supplied from the CPU 35 via the address bus 25 to a DRAM (Dynamic Random).
Access Memory) 33 is converted into a physical address for accessing, and DRAM 33 is accessed. The details of the address conversion table 32 will be described later.

The DRAM 33 is a main storage device for storing data necessary for the operation of a frame buffer and a program. The DMA interface 34 converts the raster image data developed in the virtual space (actually the DRAM) into C
The data is directly transferred to the printer, which is an output device, by the DMA method without using the PU 35. The CPU 35 controls the above-described units, and in particular, executes the program of the ROM 29 to realize the function of the language interpretation / image processing unit 12 described above.

A-4. Functional Configuration of Memory Management Unit Next, the function of the above-described memory management unit will be described.
Here, FIG. 1 is a block diagram showing a functional configuration of a memory management unit (hierarchical storage management device) according to the embodiment of the present invention. In the figure, a storage read / write unit 40 sends a data read / write request to a storage management unit 41. The storage management unit 41 corresponds to the memory management unit 16 described above, and is set to be accessible (rewritable) or access prohibited (not rewriteable) in terms of hardware for each hierarchical level of the storage unit 45. Set to. The area storage determination unit 42 is configured to store information (access prohibited) from the storage management unit.
Is used as a trigger to determine whether or not the area is to be restored when the data is restored, in other words, whether or not the area exceeds the level. Then, the change history creating unit 43 creates a history of the changed variable according to the result of the determination by the area determining unit 42, if necessary, and stores the change history in the change history storage unit 44. That is, in the present embodiment, it is not necessary for the storage read / write unit 40 to read the memory that is the storage unit 45 based on the determination result by the area storage determination unit 42.

A-4. Next, FIG. 5 is a conceptual diagram showing a functional configuration (operation) of the address translation device according to the above embodiment. The virtual memory (substantially, the DRAM 33) is a storage area that is assigned a level and managed hierarchically, and has a function of restoring a given low-level memory state in addition to writing and reading. The memory management unit acquires, writes, and acquires the memory area in response to a request from a module in an upper layer.
It has a function of reading, saving the state, and restoring. The save state operation indicates to save the current memory state and returns the corresponding ID as a result. The state restoration operation is for restoring a previously saved state. At this time, the I-state given at the time of saving as an argument is used.
Restore any memory state based on D.

In the figure, a virtual address VA is supplied from the CPU 35 described above, and includes a PTE number (upper 17 bits) 51 indicating a PTE (page table entry) of the address conversion table 27 and a lower address of the physical address PA. Offset directly indicating 15 bits (lower 15 bits)
Bit) 52. The virtual address VA is converted by the memory management unit 31 into a physical address PA for accessing the DRAM 33. That is, the virtual address VA is divided into upper 17 bits 51 and lower 15 bits 52, and the upper 17 bits 51 are used for addressing the address conversion table 27. The address conversion table 27 is composed of a RAM readable and writable by the CPU 35, and has a PTE number (0
0000-1fff), its attributes 53 and 15
It holds a physical page number 54 of bits. Therefore, the PTE number of the virtual address VA (upper 17 bits)
51 retrieves one PTE corresponding to the virtual address.

One PTE is, as shown in FIG. 6, specifically, a valid flag (1 bit) 56 indicating whether the PTE is valid, a write attribute (16 bits) 57,
And the physical page number (15 bits) 54 described above. The physical address PA is the physical page number 5
4 and an offset 52 of the virtual address VA. As shown in FIG. 7, the physical page number 54 is obtained by dividing the DRAM 33 having a continuous storage area into fixed length area units.
Blocks are indicated by numbers. In this embodiment, as described above, one block is 32 Kbytes,
An area for 12 blocks is prepared. The validity flag 56 indicates whether or not the PTE holds a correct physical page number. If the PTE is "1", it indicates that the PTE is correctly associated. As shown in FIG. 8, the write attribute 57 is a set of flags 62 indicating a write attribute corresponding to each divided area 61 obtained by dividing one physical page 60 of 32 Kbytes in units of 2 Kbytes.

FIG. 9 is a block diagram of a circuit for converting the logical address VA into the physical address PA in the memory management unit 31. In the figure, a PTE map 70 has an address conversion table 2
7. One PTE (32 bits) corresponding to the PTE number 51 (15th to 31st bits), which is the upper 17 bits of the logical address VA, is extracted. next,
The decoder 71 outputs 4 bits (14 bits from the 11th bit) of the offset (lower 16 bits) of the logical address VA.
) And decodes each bit into each AND circuit 72
To one of the input terminals. The other input terminal of each AND circuit 72 is supplied with each bit of the write attribute 57 of the PTE. Each AND circuit 57 calculates the logical product of the bit from the decoder and the bit of the write attribute 57 and supplies the logical product to the NOR circuit 73. NOR circuit 7
3 takes the logical sum of the outputs of the respective AND circuits 72, inverts the result, and supplies the result to one input terminal of the NAND circuit 74.

The other input terminal of the NAND circuit 74 has C
Write enable signal WE ^* supplied from PU 35
Is supplied to the NAND circuit 74.
The logical product of the inverted signal of the output of the circuit 73 and the inverted signal of the write enable signal WE ^* is obtained, and the OR circuit 75
To one of the input terminals. The other input terminal of the OR circuit 75 is supplied with the valid flag 56 of the PTE. The OR circuit 75 calculates the logical sum of the output of the NAND circuit 74 and the inverted signal of the valid flag 56. ,
The result is inverted and output as a trap enable signal TE ^* . The offset (lower 15 bits) between the physical page number 54 of the PTE and the logical address VA is
It is output as a physical address PA of 30 bits in total.
That is, if the CPU 35 (the storage / read / write means 40 in FIG. 1) accesses an area to which a physical page is not assigned or writes to a write-inhibited area, the trap enable TE ^* signal is asserted. , An interrupt to the CPU 35 is generated.

B. Next, an operation of the hierarchical storage management device according to the present embodiment will be described. B-1. Initialization Processing First, initialization processing performed prior to the operation of the memory management unit will be described. Here, FIG. 10 is a flowchart for explaining the initialization processing. First, step Sa
In step 1, the valid flag 56 of each PTE in the PTE map 70 (address conversion table) is initialized to “0”. Next, in step Sa2, the current level CL indicating the current storage level is set to "0", and the pointer indicating the head of the area to be allocated is initialized to "0".

B-2. Process for Securing Memory Area Next, a process for allocating memory for one unit will be described. Here, FIG. 11 is a flowchart for explaining the reserved area. First, step Sb1
In step Sb2, after storing the pointer indicating the head of the area to be allocated in the address, the pointer is incremented by "1" in step Sb2, and the address set in step Sb1 is set as the return value in step Sb3.

B-3. Write Processing Next, write processing to the memory will be described. Here, FIG. 12 is a conceptual diagram showing a data configuration when data is written to the memory. FIG. 13 is a conceptual diagram showing one state of the memory, and FIG. 14 is a flowchart for explaining the writing process. As shown in FIG. 12, when data is written to a memory, a current level CL indicating a current level is added, and the data is sequentially written from a lower address. FIG. 13 is a conceptual diagram showing one state of the memory. In the figure, reference numeral 80 denotes data written at the current memory level “1”;
Is data generated when the level is “0”.

In the writing process, first, in step Sc1, a virtual address is designated to write the current level CL at a predetermined address.
Then, write the specified data. At this time, the virtual address is converted into a physical address PA by the memory management unit 16. Therefore, when the physical memory is not allocated to the virtual space, the trap enable TE ^* signal shown in FIG. 9 is asserted before the write processing is executed, and as a result, an interrupt occurs to the CPU 35. I do. In the interrupt processing, memory allocation is performed. After that, the above-described writing process is executed. The details of the interrupt processing will be described later.

B-4. Read Process Next, a read process from the memory will be described. Here, FIG. 15 is a flowchart for explaining the reading process. In the process of reading from the memory, in step Sd1, data at the specified address is simply read.

B-5. Next, a save process for saving the state of the memory area will be described with reference to FIG. Here, FIG. 16 is a flowchart for explaining the saving process, and FIG. 17 is a conceptual diagram for explaining an operation of writing-protecting an area to be saved in the saving process. In the preservation process,
In step Se1, the current level CL is set as a return value. Next, in step Se2, the current level CL is incremented by "1". This allows
The new level is one level higher than before.

Then, in step Se3, for every 2K bytes, which is the minimum memory unit in which writing can be prohibited in the PTE, the area from the head to the pointer indicating the current area to be allocated (see reference symbol a in FIG. 17). By setting the write attribute 57 of the PTE to “1”,
Write-protected. By this operation, the writing to the area where the state is saved is prohibited.
Therefore, when an access is made to the write-protected area, the trap enable TE ^* signal shown in FIG. 9 is asserted as described above, and as a result, C
An interrupt occurs to the PU 35. In the interrupt processing, memory allocation is performed.

B-6. Interrupt Processing Next, the above-described interrupt processing will be described. Here, FIG. 18 is a flowchart for explaining the interrupt processing. As described above, the interrupt process is executed when no physical memory is allocated to the virtual space in the write process, or when an attempt is made to access a write-protected area in the save process. Is done.

When an interrupt occurs, first, in step S
At f1, the cause of the interrupt is checked by determining whether the valid flag 56 of the PTE is “0”. Then, in the case of an interrupt caused by the valid flag 56 of the PTE being “0”, it is determined that the write is to an area where the physical memory is not allocated to the virtual space, and the process proceeds to step Sf2. A physical page is allocated to the virtual space to be processed, and the process ends.

On the other hand, if the valid flag 56 is not "0", it is determined that the write is for a write-protected area, and the flow advances to step Sf3. In step Sf3, it is determined whether or not the area needs to be saved before the data is rewritten by determining whether the current level CL indicating the current level and the level L indicating the level added to the area are the same. Check by determining if there is. If the current level CL and the level L are the same, the current process is a write to an unsaved area that is currently being processed. On the other hand, if the current level CL is not the same as the level L, the data is written in a saved area. Therefore, by the following steps, the previously written data is written before the data is written. evacuate.

FIGS. 19A and 19B are conceptual diagrams for explaining the structure in the evacuation memory. As shown in FIG. 19B, the evacuation memory includes a pointer 85 indicating the next change content, and an address 8 of the data to be changed.
6 and leaf 8 on which data 87 before rewriting are recorded
As shown in FIG. 19 (a), 8 is unidirectionally listed for each level indicated by 0 to 15.

Therefore, in the interrupt processing, step Sf
In step 4, a list corresponding to the level L of the accessed area is selected, and the change (leaf) is added to the top of the list. Next, in step Sf5, the level L of the area to be changed is set to the current level CL. As a result, it is possible to prevent the evacuation memory from increasing even when the same address is written a plurality of times.

B-7. Restore Process Next, a description will be given of a restore process for restoring the state of the area saved by the save process described above. Here, FIG.
It is a flow chart for explaining return processing. In the return processing, the rewritten information is restored to the state before rewriting based on the change history information shown in FIG. 19 created by the above-described interrupt processing. First, in step Sg1, the current level CL-1 is set to a variable i. That is, the level immediately before the current level is set in the variable i. Next, in step Sg2, it is determined whether or not the variable i has reached the specified level L. If not, the process proceeds to step Sg3, and according to the information in the list corresponding to the level L indicated by the variable i, Restore memory contents. Then, in step Sg4, the variable i is set to “1”.
, And returns to step Sg2. Thereafter, the memory is sequentially restored in accordance with the information in the list corresponding to the level L indicated by the variable i while decrementing the variable i until the variable i reaches the designated level L.

When the variable i reaches the specified level L, the process proceeds to step Sg5, where the current level CL is updated to the level L, and in step Sg6, the pointer P is returned to the state where the level L is stored. Next, step Sg7
To set the write attribute 57 of the PTE up to that area to "0".
And the write protection is released.

[0038]

As described above, according to the present invention, the newly written information and the information before being rewritten due to the storage of the newly written information are stored in the storage means in a time-series manner. In the process of storing the information in different hierarchical levels, the prohibited area setting means sets a write-inhibited area based on the hierarchical level of the information stored in the storage means. Is the area set by the prohibited area setting means,
After the information already written in the area is stored in a predetermined area of the storage means by the storage means, the information requested to be written is stored in the storage means by the storage control means. Each time, it is not necessary to determine whether or not the area will be restored later. This has the advantage that the processing at the time of writing to the memory can be simplified and the processing speed can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a functional configuration of a memory management unit (hierarchical storage management device) according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a document processing system.

FIG. 3 is a block diagram illustrating a configuration of a language interpretation / image processing unit.

FIG. 4 is a block diagram illustrating a configuration of an image data output device.

FIG. 5 is a conceptual diagram showing a functional configuration (operation) of the address translator.

FIG. 6 is a conceptual diagram showing a more detailed configuration of an address conversion table.

FIG. 7 is a conceptual diagram showing a configuration of a block of a DRAM.

FIG. 8 is a conceptual diagram for explaining a write attribute.

FIG. 9 is a block diagram of a circuit that converts a logical address VA into a physical address PA in the memory management unit.

FIG. 10 is a flowchart illustrating an initialization process.

FIG. 11 is a flowchart illustrating a reserved area.

FIG. 12 is a conceptual diagram showing a data configuration when data is written to a memory.

FIG. 13 is a conceptual diagram showing one state of a memory.

FIG. 14 is a flowchart illustrating a writing process.

FIG. 15 is a flowchart illustrating a reading process.

FIG. 16 is a flowchart illustrating a storage process.

FIG. 17 is a conceptual diagram for explaining an operation of writing-protecting an area to be saved in a saving process.

FIG. 18 is a flowchart illustrating an interrupt process.

FIG. 19 is a conceptual diagram for explaining a structure in an evacuation memory.

FIG. 20 is a flowchart illustrating a return process.

FIG. 21 shows a conventional memory management unit (hierarchical storage management device).
FIG. 2 is a block diagram showing a functional configuration of the first embodiment.

[Explanation of symbols]

31 memory management unit (forbidden area setting means, storage control means, address conversion means) 32 address conversion table (address conversion means) 33 DRAM (storage means) 35 CPU (storage means) 41 storage management means (forbidden area setting means, storage) Control means) 43 change history creation means (storage means) 44 change history storage means (storage means) 45 storage means

Claims (4)

[Claims] 1. A storage unit for storing newly written information and information before being rewritten in accordance with storage of the newly written information in a time-series hierarchical level, and storing the information in the storage unit. A prohibited area setting means for setting a write prohibited area based on the hierarchical level of the set information, and when a write request is issued to the area set by the prohibited area setting means, information already written in the area is deleted. Storage means for storing in a predetermined area of the storage means, and storage control for controlling to store the information requested to be written in the storage means after information already written by the storage means is stored. And a means for managing hierarchical storage. 2. The hierarchical storage management device according to claim 1, further comprising address conversion means for converting a logical address for storing information requested to be written into a physical address of said storage means. 3. The hierarchical storage control device according to claim 2, wherein said address conversion means assigns said physical address to said logical address according to a use condition of said storage means. 4. The address conversion means assigns a write attribute indicating whether the area is a writable area or an unwritable area to each of a plurality of areas dividing the storage means. 3. The hierarchical storage management device according to claim 2, wherein the occurrence of a write request to the area set by the prohibited area setting means is detected based on the request, and the storage request is notified to the storage means.