JPH1063540A - Signal inputiting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal input circuit saving power consumption and reducing noise. SOLUTION: When a reading signal is inputted, a holding device 5 reads and holds data, a comparator 6 compares inputted data and the output of the holding device 5, and CPU 3 outputs the reading signal and reads data when the comparing result by the comparator 6 is not coincident. CPU 3 suspends processing when the comparing result by the comparator 6 is coincident, but executes the reading of data or the arithmetic processing of the data when the comparing result by the comparator 6 is not coincident. Otherwise, the comparing result by the comparator 6 is supplied for the interruption input terminal of CPU 3, which executes previously set processing when the comparing result by the comparator 6 is coincident but executes the reading of data or the arithmetic processing of the data when the comparing result by the comparator 6 is not coincident.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal input circuit for executing processing by inputting a signal when the signal changes.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing an example of the configuration of a signal change monitoring circuit according to the prior art. And the signal change monitoring, each input signal i _0, i ₁ ... i _n of 2 values,
It is to monitor whether the state has changed from “H” (high level) to “L” (low level) or from “L” to “H”.

In the signal change monitoring circuit shown in FIG.
(Central Processing Unit) 13 periodically generates a pulsed read signal R at intervals of several milliseconds to several tens of milliseconds.

On the other hand, a three-state bus buffer 12
, Only when the read signal R is input, the input signal i _0, i ₁ ... i _n is the input terminal side to be supplied to the input state from the high resistance inputted input signal i _0, i ₁ ... i _n to C
Pass to PU13.

The CPU 13 receives the input signal
i₀, I₁... i_nAnd the previous reading signal R was output
Corresponding input signal (input signal i_0-1, I
_1-1... i _n-1) And each input signal i₀, I₁... i_n
It monitors whether or not has changed.

[0006]

According to i.e. the circuit shown in FIG. 3 A be Solved by the Invention] By reading the input signal i _0, i ₁ ... i _n regularly because it monitors the change, the CPU13 input signal It is operating regardless of the change of.

For this reason, there is no change in the input signal and the CPU 13 must continue to operate even if there is no item to be processed, which hinders the reduction in power consumption. Even if the CPU 13 is suspended when there is no item to be processed, it is necessary to restart the CPU 13 at intervals of several milliseconds to several tens of milliseconds in order to read an input signal as described above. was there.

Further, in such a signal change monitoring circuit, noise in an audible frequency band having a period of several milliseconds to several tens of milliseconds, which is an operation interval of the CPU 13 (several tens of Hz to several hundreds of H).
z) occurs.

Therefore, when this circuit is applied to a device that outputs amplified sound through a speaker or the like, noise components may be mixed into the amplifier, and noise may be output together with the required sound. For this reason, it has been necessary to take measures such as separating the amplifier and the signal change monitoring circuit, and surrounding each circuit with a shield case. The present invention has been made under such a background, and has as its object to provide a signal input circuit capable of reducing power consumption and noise.

[0010]

According to the first aspect of the present invention, there is provided a data processing means for outputting a read signal when reading data,
A data holding unit that reads and holds the data when the read signal is input, and a data comparison unit that compares the input data with an output of the data holding unit, wherein the data processing unit includes: The data is read when the comparison result by the data comparing means does not match. Further, in the invention according to claim 2, in the signal input circuit according to claim 1, the data processing unit suspends the processing when the comparison result by the data comparison unit matches. When the comparison result by the data comparison means does not match, the data is read or the data is processed. According to a third aspect of the present invention, in the signal input circuit according to the first aspect, the comparison result by the data comparing means is supplied to an interrupt input terminal of the data processing means, and the data processing means When the result of comparison by the data comparing means is identical, a predetermined process is executed, and when the result of comparison by the data comparing means is inconsistent, the data is read or the arithmetic processing of the data is executed. It is characterized by doing.

According to the present invention, the data holding means reads and holds the data when the read signal is input, the data comparison means compares the input data with the output of the data holding means, and the data processing means When the result of comparison by the data comparing means does not match, a read signal is output and data is read. The data processing means suspends the processing when the result of comparison by the data comparing means is coincident, and executes data reading or arithmetic processing of the data when the result of comparison by the data comparing means is inconsistent. Alternatively, the comparison result by the data comparison unit is supplied to an interrupt input terminal of the data processing unit, and the data processing unit executes a preset process when the comparison result by the data comparison unit matches,
If the result of comparison by the data comparing means does not match, data reading or arithmetic processing of the data is executed.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below.
FIG. 1 is a block diagram showing a configuration of a signal input circuit according to one embodiment of the present invention. The input circuit shown in FIG.
In this configuration, data of n + 1 bits (bit 0 to bit n) is input.

In FIG. 1, reference numeral 2 denotes a three-state bus buffer. The 3-state buffer 2 is the input data i ₀ through i _n input an input buffer to pass to CPU3, by the read signal R from the CPU3 is input, the data input terminal a high resistance state From the input state.

The CPU 3 has a mismatch signal D which will be described later.
Is entered. The CPU 3 determines that the mismatch signal D is "L".
Is a pause state (including a case where the CPU 3 waits in a low power consumption state and performing other processing), and shifts to an operation state when the mismatch signal becomes “H”.

The data output from the three-state bus buffer is supplied to the CPU 3 and the holder 5. The retainer 5 is
When the read signal R is input, the output data of the three-state bus buffer is read and output. When the read signal R is not input, the read data is held and output.

[0016] 6 is a comparator, and the data holding unit 5 and the input data i ₀ through i _n outputs, and outputs a mismatch signal D must match by comparing them. This mismatch signal D is input to an interrupt input terminal or the like of the CPU 3.

The operation of this embodiment will be described below. FIG. 2 is a timing chart showing a signal level and the like in each section of the present embodiment. In FIG. 2, the input data i _n, are shown with respect to the output bits of the cage 5 corresponding thereto (data i _n).

At time t ₀ in FIG. 2, input data i _n
And the level of the output of the retainer 5 coincide with each other.
In this case, since the non-coincidence signal D output from the comparator 6 is "L", the CPU 3 remains in the sleep state.

[0019] Next, the input data i _n at time t ₁ is changed to the "H" from "L". That is, the input data i _n
Is different from the level of the output of the retainer 5, and the mismatch signal D output from the comparator 6 is "H".
Becomes

When the mismatch signal D becomes "H",
The CPU 3 enters an operation state and outputs a read signal R. Thereby, the three-state bus buffer 2 enters the input state, and the input data is read by the CPU 3.

At the same time, the output of the retainer 5 is rewritten with the contents of the newly read input data. Therefore, the non-coincidence signal D output from the comparator 6 becomes "L" again. After the CPU 3 enters the operating state and ends the predetermined processing (for example, several tens of milliseconds during this period), the CPU 3 returns to the sleep state again.

[0022] Furthermore, the input data i _n at time t ₂ is changed to the "L" to "H". That is, the input data i _n
Is different from the level of the output of the retainer 5, and the mismatch signal D output from the comparator 6 is "H".
Becomes

When the mismatch signal D becomes "H",
As described above, the CPU 3 is activated, and the read signal R
And the three-state bus buffer 2 enters the input state, and the input data is read by the CPU 3.

At the same time, the output of the holder 5 is rewritten to the content of the newly read input data,
Output again becomes "L". After this,
The CPU 3 returns to the sleep state again.

As described above, in this embodiment, the CPU 3 is in the operating state from the time when the level of the input data in is changed to the time when the predetermined processing by the CPU 3 is completed, and otherwise the CPU 3 is in the idle state. Therefore, power consumption of the signal input circuit can be reduced. Further, since the CPU 3 does not need to periodically shift from the sleep state to the operation state, no noise component particularly in the audible frequency band is generated.

In the above embodiment, the input data i _n
Has been described as an example, however, the operation is the same when any of the input data i _{0 to in n} changes, so the description thereof will be omitted.

Further, in the above-described embodiment, the CPU 3 returns to the sleep state after the predetermined processing is completed after the operation state, but as shown in FIG. 2, the CPU 3 is set in advance after the operation state. After a predetermined time t _a (for example, several tens of milliseconds) elapses, the configuration may return to the sleep state.

[0028]

As described above, according to the present invention, the data holding means reads and holds data when a read signal is input, and the data comparison means compares the input data with the output of the data holding means. And the data processing means outputs a read signal and reads data when the comparison result by the data comparison means does not match. The data processing means suspends the processing when the result of comparison by the data comparing means is coincident, and executes data reading or arithmetic processing of the data when the result of comparison by the data comparing means is inconsistent. Alternatively, the comparison result by the data comparison means is supplied to an interrupt input terminal of the data processing means, and the data processing means executes a preset process when the comparison results by the data comparison means match, If the result of the comparison does not match, data reading or arithmetic processing of the data is performed, so that an effect that a signal input circuit that can reduce power consumption and noise can be realized is obtained.

That is, according to the present invention, there is no need to constantly or periodically monitor the input signal by the central processing unit, and the system can be completely put into the halt state. This is because the provision of the circuit for monitoring a change in the input signal allows the central processing unit to keep the sleep state when the input signal is not changed, thereby reducing power consumption. become.

In order to eliminate noise, it is not necessary to separate circuits and take measures such as a shield case. This is because the central processing unit does not operate periodically, and no periodic noise is generated from the central processing unit. Also,
This is also because the central processing unit completes the processing in several tens of milliseconds when the input is changed and the central processing unit is again in the sleep state, so that noise in the human audible range is not generated.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a signal input circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing a signal level and the like in each section of the embodiment.

FIG. 3 is a block diagram illustrating an example of a configuration of a signal change monitoring circuit according to a conventional technique.

[Explanation of symbols]

 3 CPU (data processing means) 5 Holder (data holding means) 6 Comparator (data comparing means)

Claims (3)

[Claims] 1. A data processing means (3) for outputting a read signal at the time of reading data; a data holding means (5) for reading and holding the data when the read signal is input; Signal comparing means for comparing the data with the output of the data holding means, wherein the data processing means reads the data when the comparison result by the data comparing means does not match. Input circuit. 2. The data processing means suspends processing when the comparison result by the data comparison means matches, and reads or reads the data when the comparison result by the data comparison means does not match. 2. The signal input circuit according to claim 1, wherein the signal input circuit executes data arithmetic processing. 3. A comparison result by the data comparison means is supplied to an interrupt input terminal of the data processing means, and the data processing means performs a preset process when the comparison results by the data comparison means match. 2. The signal input circuit according to claim 1, wherein when the comparison result by the data comparing means does not match, the data is read or the data is processed.