JPH1063485A - Digital multiplier adder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lay out as one block with an adder which performs last row adding processing in a digital multiplier, to reduce useless space where no cell exists, to provide a layout of high density and to entirely output each bit of a multiplied result output signal in the same direction. SOLUTION: A digital multiplier is provided with partial product generation addition array 21 and a last row adder 22. The adder 22 is divided between even bit cell array 22A which consists of plural adder cells to generate even bits in a multiplied result output signal Z and odd bit cell array 22B which consists of plural adder cells to generate odd bits in the signal Z and is parallelly arranged along a bit direction in the array 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adder for a digital multiplier for performing a final stage addition process in a digital multiplier.

[0002]

2. Description of the Related Art Basically, processing in a digital multiplier (hereinafter simply referred to as a multiplier) is a processing of generating a partial product and adding the generated partial products to obtain a final multiplication result. And processing. In the process of adding the partial products to obtain the final multiplication result, the sum (su
m) and a carry of a partial product until carry (carry) is obtained, and a sum and carry of each bit obtained by the partial product addition are multiplied by addition. A final stage addition process for obtaining a result is performed.

FIG. 13 shows a configuration of a multiplier for performing a partial product addition process and a final stage addition process as a process for obtaining a final multiplication result by adding partial products as described above, and an arrangement of each block. An example is shown. Here, for simplicity, it is assumed that both the multiplicand input signal X and the multiplier input signal Y have a bit width of n bits (n is a natural number). In the figure,
x _i (i = 0,..., n−1), y _j (j = 0,.
1) represents each bit of the multiplicand input signal and the multiplier input signal, respectively. The multiplier shown in FIG. 13 receives a multiplicand input signal X and a multiplier input signal Y and performs a partial product generation process and a partial product addition process, and a partial product generation and addition array 101. Final stage adder 102 which receives the output signal of 101 and performs final stage addition processing
And

In the multiplier shown in FIG. 13, a multiplicand input signal X and a multiplier input signal Y are input to a partial product generation and addition array 101 from directions orthogonal to each other. A product is generated, and addition processing of the partial product is performed until each bit becomes a sum and a carry of two numbers, and the addition processing of the two numbers is performed by the final-stage adder 102, and the final multiplication is performed. The result output signal is obtained.

When both the multiplicand input signal X and the multiplier input signal Y have n bits, the bit width of the multiplication result output signal is of course 2n bits, and the sum to be input to the final-stage adder 102 is obtained. And the carry bit width are also 2n bits. Therefore, a 2n-bit adder is required as the last-stage adder 102. However, the bit width of the partial product generation and addition array is generally equal to the bit width n of the multiplicand input signal X. Therefore, the final stage adder 10
2 is a final stage adder 102L for lower n bits,
It is common to divide the circuit into two parts, that is, a final stage adder 102H for the upper n bits, and arrange them in an L-shape as shown in FIG. In this case, the multiplication result output signal Z _Hi = [z _2n−1 ,...
z _n ] is output from the final stage adder 102L.
Bit multiplication result output signal Z _Lo = [z _n−1 ,..., Z ₀ ]
Is output. In the figure, S _Hi (= [s _2n-1 ,..., S
_n ]) represents the sum signal for the upper bits, and C _Hi (=
[C _2n-1 ,..., C _n-1 ] represents a carry signal for the upper bits, and S _Lo (= [s _n-1 ,..., S ₀ ]) is a sum signal for the lower bits. And C _Lo (= [c _n−2 ,..., C
₀ ]) represents a carry signal for the lower bits.
In the drawing, broken-line arrows shown on the partial product generation addition array 101 and the final stage adders 102H and 102L indicate the bit directions. The reason why such an L-shaped arrangement is adopted is that the sum and the carry are determined in order from the one closest to the LSB (least significant bit), so that it is close to the input position of the multiplicand input signal X or the multiplier input signal Y. In the place, the last stage adder 10
This is because it is better to arrange a portion closer to LSB 2 in terms of calculation speed and the like.

[0006]

However, as shown in FIG. 13, the last-stage adder 102 is divided into two, and the bit directions of the upper and lower n bits are different between the upper n bits and the lower n bits. Considering the cell arrangement of the entire multiplier, the partial product generation addition array 101 and the final stage adder 102
There is a problem that various measures are required in terms of the connection method (particularly, the wiring method of the power supply line, etc.). In addition, since there is a blank portion where cells are not arranged, it is not efficient in terms of area. Further, the multiplication result output signal is Z
_Dividing into _Hi and Z _Lo and outputting them in different directions is disadvantageous in terms of an interface with an external block in the case of a multiplier for embedded use or the like.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and an object of the present invention is to provide an adder for performing a final-stage addition process in a digital multiplier, which can be laid out as one block and has a cell existence. A high-density layout can be realized by reducing unnecessary waste margins,
An object of the present invention is to provide a digital multiplier adder capable of outputting all bits of a multiplication result output signal in the same direction.

[0008]

SUMMARY OF THE INVENTION An adder for a digital multiplier according to the present invention includes a plurality of cells arranged in a predetermined number in a bit direction to constitute one stage and provided in a plurality of stages, and generates a partial product. And a final stage adder that performs an addition process on the output signal of the partial product generation and addition array and outputs a multiplication result output signal. An adder for a digital multiplier used as an adder, comprising a plurality of adder cells for a larger number of bits than the number of cells in the bit direction in the partial product generation and addition array, and the plurality of adder cells are Arranged along the bit direction in the partial product generation and addition array so as to be arranged in parallel in at least a part of the bit direction in the partial product generation and addition array. Those which are.

In this adder for a digital multiplier, a plurality of adder cells corresponding to a larger number of bits than the number of cells in the bit direction in the partial product generation / addition array are provided at least partially in the bit direction in the partial product generation / addition array. Since they are arranged along the bit direction in the partial product generation and addition array so as to be arranged in parallel in the region, the adder for the digital multiplier can be laid out as one block, and the multiplication result output signal All bits can be output in the same direction.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

First, a digital multiplier including a digital multiplier adder according to a first embodiment of the present invention will be described with reference to FIG. This digital multiplier performs multiplication using the Booth algorithm. The digital multiplier receives a multiplier input signal Y and outputs a selection signal 12 to a Booth decoder 11.
And a Booth decoder 1 for the multiplicand input signal X.
A Booth selector 13 that multiplies a coefficient according to the selection signal 12 from 1 to output a partial product 14, and a partial product that performs an addition process of the partial product 14 until each bit becomes a sum and a carry of two. An addition processing unit 15 and a final-stage addition processing unit 16 for adding the sum and carry of each bit output from the partial product addition processing unit 15 and outputting a multiplication result output signal Z are provided.

In this digital multiplier, a Booth decoder 11 supplies a selection signal 12 for selecting a coefficient by which a multiplicand input signal X is to be multiplied to a Booth selector 13 based on necessary bits of the multiplier input signal Y. . The Booth selector 13 multiplies the multiplicand input signal X by a coefficient selected according to the selection signal 12, and outputs a partial product 14. Thereafter, the addition process of the partial product 14 is performed by the partial product addition processing unit 15 until each of the bits becomes a sum of two and a carry, and further, the final stage addition processing unit 1
6, the sum and carry are added to each bit output from the partial product addition processing unit 15, and a multiplication result output signal Z is finally obtained.

FIG. 1 is an explanatory diagram showing a configuration of a digital multiplier including a digital multiplier adder according to the present embodiment and an arrangement of each block. Here, for simplicity, it is assumed that both the multiplicand input signal X and the multiplier input signal Y have a bit width of n bits (n is a natural number). In the figure, x
_i (i = 0,..., n−1), y _j (j = 0,.
1) represents each bit of the multiplicand input signal and the multiplier input signal, respectively. The digital multiplier receives a multiplicand input signal X and a multiplier input signal Y and performs a partial product generation process and a partial product addition process, and an output of the partial product generation and addition array 21. The multiplication result output signal Z
= [Z _2n-1 ,..., Z ₀ ].

The partial product generation and addition array 21 is arranged in n bits in the bit direction to form one stage and has a plurality of cells provided in a plurality of stages. Note that, in the figure, broken arrows indicate the bit directions. The partial product generation and addition array 21 corresponds to the Booth decoder 1 shown in FIG.
1, Booth selector 13 and partial product addition processing unit 1
Corresponding to 5.

The last-stage adder 22 corresponds to the adder for the digital multiplier according to the first embodiment of the present invention, and has 2n bits, which is more than the number n of cells in the bit direction in the partial product generation and addition array 21. A plurality of adder cells are provided. In the present embodiment, the final-stage adder 22 is replaced with an even-bit cell array 22 composed of a plurality of adder cells for generating even-numbered bits of the multiplication result output signal Z.
A and an odd bit cell array 22B composed of a plurality of adder cells for generating odd bits of the multiplication result output signal Z, and these are arranged in parallel along the bit direction in the partial product generation and addition array 21. Have been placed.
Even bit cell array 22A, odd bit cell array 2
The bit width of each 2B is n bits, which is equal to the bit width n in the partial product generation and addition array 21. Each adder cell in the even bit cell array 22A and the odd bit cell array 22B is arranged at a position corresponding to each cell in the bit direction in the partial product generation and addition array 21. Therefore, two adder cells are arranged in parallel at positions corresponding to each cell in the bit direction in the partial product generation addition array 21.

In the digital multiplier shown in FIG. 1, a multiplicand input signal X and a multiplier input signal Y are input to a partial product generation and addition array 21 from directions orthogonal to each other. A partial product is generated, and addition processing of the partial product is performed for each bit until the sum S and the carry C become two numbers, and the two numbers are input to the final-stage adder 22. In the final stage adder 22, the even bit of the multiplication result output signal Z is generated by the even bit cell array 22A, and the odd bit cell array 22
B generates an odd number bit of the multiplication result output signal Z.

Here, a specific example of the last-stage adder 22 will be described. First, with reference to FIG. 3, an example of the configuration of the conventional last-stage adder 102 in FIG. 13 will be described for comparison with the last-stage adder 22 in the present embodiment. The last-stage adder 102 shown in FIG. 3 is an example using a ripple carry adder. This final stage adder 102
Is a half adder (shown as HA in the figure) 102 ₀ that generates the least significant bit z ₀ of the multiplication result output signal Z, and the other bits z _{1 to} z _{2n−1 of the} multiplication result output signal Z. (In the figure, referred to as FA) 102 ₁ to 10 2
2 _2n-1 . The half adder 102 ₀ receives the sum signal S ₀ from the partial product generation and addition array and the carry signal C ₋₁ (=
0) and outputs z ₀ and a carry signal C _out . The full adder 102 _i (i = 1,..., 2n−1)
The sum signal S _i and the carry signal C _i-1 from the partial product generation and addition array and the carry signal C _out from the adder 102 _i-1 are added, and z _i and the carry signal C _out are respectively processed. _out
Is output. In the final-stage adder 102, cells of the adders 102 _{0 to} 102 _2n−1 are arranged in one column.
As a result, it has a width of 2n cells. for that reason,
Conventionally, as shown in FIG.
Are divided into two parts, a final-stage adder 102L for lower n bits and a final-stage adder 102H for upper n bits, and are arranged in an L-shape.

FIG. 4 shows an arrangement of cells in an example of the last-stage adder 22 in the present embodiment.
The last-stage adder 22 in this example is functionally the same as that shown in FIG.
A half adder 22 ₀ corresponding to _0, the full adder 22 _1-22 corresponding to full adder 102 ₁ ~102 _2n-1 in FIG. 3
_2n-1 . However, in the final-stage adder 22, a plurality of adders 22 ₀ , 22 ₂ ,... For generating even-numbered bits of the multiplication result output signal Z are used by the cells of the adders 22 _{0 to} 22 _2n-1 . , 22 _2n-2 and a plurality of adders 22 ₁ , 22 ₃ ,..., 22 _2n-1 for generating odd bits of the multiplication result output signal Z. And these are arranged in parallel. Incidentally, the adders 22 ₀ , 22 ₂ ,.
A plurality of cells for _{2n-2 form} an even-bit cell array 22A, and adders 22 ₁ , 22 ₃ ,.
A plurality of cells for _{2n-1 form} an odd bit cell array 22B. The bit width of the even bit cell array 22A and the odd bit cell array 22B is n bits equal to the bit width in the partial product generation and addition array 21. Each cell in the even bit cell array 22A and the odd bit cell array 22B is Are arranged at positions corresponding to the respective cells in the bit direction.

As described above, according to the last-stage adder 22 in the present embodiment, the even-numbered bit cell array 2
Since each bit width of the 2A, odd-numbered bit cell array 22B is equal to the bit width of the partial product generation and addition array 21, it is not necessary to arrange them in an L-shape as shown in FIG. At the same time, it is possible to connect to the partial product generation and addition array 21 only on one side. Therefore, the connection between the partial product generation and addition array 21 and the final-stage adder 22 is facilitated, the useless blank space in which no cells are present is reduced, and a high-density layout can be realized. It is efficient. Further, according to the last-stage adder 22 in the present embodiment,
Since all the bits of the multiplication result output signal Z can be output in the same direction, it can be said that the multiplication result output signal Z is suitable as an embedded digital multiplier in terms of interface with an external block.

Further, according to the last stage adder 22 in the present embodiment, since the bit directions of the partial product generation and addition array 21 and the last stage adder 22 match, the cell arrangement is fixed and only the wiring is automatically performed. When using the layout CAD to be performed, the layout can be easily performed.

FIG. 5 shows a second embodiment of the present invention.
Structure of digital multiplier including adder for digital multiplier
FIG. 4 is an explanatory diagram showing the configuration and arrangement of each block. This implementation
Is that the last-stage adder performs multiple final-stage additions.
FIG. 5 shows an example in which the stage is divided into stages.
An example in which the number of tiers is 2 is shown. In this example,
Instead of the final stage adder 22 in one embodiment,
A final stage adder 32 is provided. This final stage adder 32
Is the first state of the final stage addition process for even-numbered bits.
1st stage even-numbered cell array 32A₁And an odd number
Performs the first stage of the final stage addition process for bits
First-stage odd-numbered cell array 32B₁And even bits
The second stage that performs the second stage of the final stage addition process
Several bit cell array 32A_TwoAnd about the odd bits
Second-stage odd-numbered bits for performing the second stage of the final-stage addition process
Cell array 32B_TwoAnd the cell array 32
A ₁, 32B₁, 32A_Two, 32B_TwoAre in this order
It is arranged in parallel so as to be adjacent to the product sum generation array 21.
Have been. The multiplication result output signal Z is
Luray 32A_TwoAnd second-stage odd-numbered bit cell array 32B
_TwoIs obtained.

As described above, when the last-stage addition process in the last-stage adder is divided into a plurality of stages, each stage is divided into an even-bit cell array and an odd-bit cell array, and these are alternately arranged. By doing so, the same effect as in the first embodiment can be obtained.

Here, a specific example of the adder used as the last-stage adder in the present embodiment will be described.
First, an example of a conventional configuration of an adder used as a last-stage adder in which the last-stage addition process is divided into a plurality of stages will be described with reference to FIG. 6 for comparison with the present embodiment. . The adder shown in FIG. 6 has a 16-bit binary look-ahead ca.
(ry) an example of an adder. This adder has six stages, and as a first stage, a 16-bit augend input signal A _0.
ＡA ₁₅ and a 16-bit addend input signal B _{0 to} B _15, and an inverted signal P _i ^* of the propagation signal P _i (i = 0,..., 15) for each bit and a carry generation signal G inverted signal of the _i G _i ^*
Is provided.

As the second stage, the adder shown in FIG. 6 corresponds to fifteen first type cells (shown by a circle in the figure) corresponding to the first to fifteenth bits and the zeroth bit. One cell of the third type (indicated by ▽ in the figure) is provided. The first type cell receives the output signal of the corresponding bit of the signal generation unit 41 and the output signal of the bit one bit before it, respectively, and the third type cell receives the output signal of the corresponding bit of the signal generation unit 41. An output signal is input.

The adder shown in FIG. 6 includes, as a third stage, fourteen second type cells (indicated by □ in the figure) corresponding to the second to fifteenth bits and the zeroth and first bits. And two third-type cells corresponding to. The second type cell receives the output signal of the corresponding bit in the second stage and the output signal of the bit two bits before the second stage, and the third type cell outputs the output signal of the corresponding bit in the second stage. Is to be entered.

The adder shown in FIG. 6 has, as a fourth stage, twelve first type cells corresponding to the fourth to fifteenth bits and four third type cells corresponding to the zeroth to third bits. Cell. The first type cell receives the output signal of the corresponding bit in the third stage and the output signal of the bit 4 bits before the third stage, respectively, and the third type cell outputs the output signal of the corresponding bit in the third stage. Is to be entered.

The adder shown in FIG. 6 has, as a fifth stage, eight second type cells corresponding to the eighth to fifteenth bits and eight third type cells corresponding to the zeroth to seventh bits. Cell. The second type cell receives the output signal of the corresponding bit at the fourth stage and the output signal of the bit eight bits before the fourth stage, and the third type cell outputs the output signal of the corresponding bit at the fourth stage. Is to be entered.

The adder shown in FIG. 6 has, as a sixth stage, an addend input signal, an addend input signal of the corresponding bit, and a bit preceding the corresponding bit of the fifth stage for each bit. , And a sum signal generator 46 for generating sum signals S ₀ -S ₁₅ . Here, the sum signal generation unit 46
, The H level (“1”) is input instead of the output signal of the bit immediately before the corresponding bit in the fifth stage. The output signal of the MSB (most significant bit) at the fifth stage becomes an inverted signal C _out ^* of the carry-out signal C _out of the present adder, and the carry-out signal C _out is obtained through the inverter.

FIG. 7 shows one of the signal generators 41 in FIG.
FIG. 3 is a block diagram showing a configuration of a cell for bits. The cell includes a signal A _i, (negation of logical sum) NOR to generate the B _i and input signal P _i ^* gate 51, signals A _i, B _i
NAND to generate and input signals G _i ^* a is composed of a (logical negation of the product) gate 52.

FIG. 8 is a block diagram showing the structure of the first type cell in FIG. This cell receives the signals P _i ^* , P
A NOR gate 53 that inputs _j ^* (j = 0,..., 15) and outputs a signal P _i ′, an OR (logical sum) gate 54 that inputs signals P _i ^* and G _j ^* , and this OR gate An output signal of the signal 54 and a signal G _i ^* are input, and a NAND gate 55 for outputting a signal G _i ′ is provided.

FIG. 9 is a block diagram showing the structure of the second type cell in FIG. This cell receives the signals _Pi , _Pj
, And outputs a signal P _i ' ^*
When, composed of an AND (logical product) gate 57 for inputting a signal P _i, G _j, and inputs the output signal and the signal G _i of the AND gate 57, a NOR gate 58 which outputs a signal G _i ^'* Have been.

FIG. 10 is a block diagram showing the configuration of the third type cell in FIG. This cell receives a signal P _i and outputs a signal P _i ′ ^* by a NOT (negation) gate 5.
9 receives the signal G _i, and outputs a signal G _i ^'* NO
And a T gate 60.

FIG. 11 shows the sum signal generator 46 shown in FIG.
FIG. 3 is a block diagram showing a configuration of a 1-bit cell. This cell has an EX-NOR (exclusive OR) gate 61 for inputting the signals A _i and B _i, and an output signal of the EX-NOR gate 61 and a signal G _i-1 ^* for inputting a signal. S
An EX-OR (exclusive OR) gate 62 that outputs _i . Note that an H level (“1”) is input to the cell of the 0th bit in the sum signal generation unit 46 as the signal G _i−1 ^* .

FIG. 12 shows an arrangement of cells in an example of the adder used as the last-stage adder in the present embodiment. This adder is functionally the same as that shown in FIG. 6, except that each stage is divided into even-numbered bits and odd-numbered bits and arranged in parallel. That is, the first stage is the signal generation unit 4 for even-numbered bits.
1A and a signal generation unit 41B for odd bits,
These are arranged in parallel. The sixth stage includes an even-bit sum signal generator 46A and an odd-bit sum signal generator 4A.
6B, which are arranged in parallel. 2
Similarly, the stages from the fifth stage to the fifth stage are divided into cells for even-numbered bits and cells for odd-numbered bits, which are arranged in parallel. In FIG. 12, for convenience, cells for even-numbered bits and cells for odd-numbered bits in each stage are shown shifted from each other, but in actuality, all of the cells in the bit direction in the partial product generation and addition array 21 are shown. The cells are arranged in parallel at positions corresponding to the cells.

Other configurations, operations, and effects of this embodiment are the same as those of the first embodiment.

Note that the present invention is not limited to the above embodiments. For example, in each of the above embodiments, the case where the bit widths of the multiplicand input signal and the multiplier input signal are equal has been described. The present invention can also be applied to the case where the bit widths of the input signal and the multiplier input signal are different. Also in this case, according to the bit width in the partial product generation and addition array (generally, the bit width of the multiplicand input signal),
The cells of the last-stage adder may be divided into a plurality of cells and arranged in parallel. The bit width of the partial product generation and addition array is N bits, and the total bit width of the last-stage adder is M bits.
When (> N) bits, M / N may not be an integer in some cases. In this case, the cells of the final-stage adder are divided into a plurality of groups so that the margins are reduced as much as possible. May be arranged in parallel. Also, 1 <
When (M / N) <2, the cells of the last-stage adder may be arranged in parallel in only a part of the partial product generation and addition array in the bit direction.

[0037]

As described above, according to the adder for a digital multiplier of the present invention, a plurality of adder cells for a larger number of bits than the number of cells in the bit direction in the partial product generation and addition array are partially replaced. The adder for the digital multiplier is laid out as one block because it is arranged along the bit direction in the partial product generation and addition array so as to be arranged in parallel in at least a part of the product generation and addition array in the bit direction. Becomes possible,
It is possible to realize a high-density layout by reducing useless blank spaces in which no cells exist, and to output all bits of the multiplication result output signal in the same direction.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a configuration of a digital multiplier including an adder according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a digital multiplier including an adder according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram showing an arrangement of cells in an example of a conventional adder for comparison with the adder according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram showing an example of a cell arrangement in the adder according to the first embodiment of the present invention.

FIG. 5 is an explanatory diagram showing a configuration of a digital multiplier including an adder according to a second embodiment of the present invention.

FIG. 6 is an explanatory diagram showing an arrangement of cells in an example of a conventional adder for comparison with the adder according to the second embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a 1-bit cell of a signal generation unit in FIG. 6;

FIG. 8 is a block diagram showing a configuration of a first type cell in FIG. 6;

FIG. 9 is a block diagram showing a configuration of a second type cell in FIG. 6;

FIG. 10 is a block diagram showing a configuration of a third type cell in FIG. 6;

11 is a block diagram showing a configuration of a 1-bit cell of a sum signal generation unit in FIG. 6;

FIG. 12 is an explanatory diagram showing an example of a cell arrangement in an adder according to a second embodiment of the present invention.

FIG. 13 is an explanatory diagram showing a configuration of a conventional digital multiplier.

[Explanation of symbols]

21: partial product generation and addition array, 22: last stage adder, 2
2A: Even bit cell array, 22B: Odd bit cell array

Claims (2)

[Claims] 1. A partial product generation / addition array having a predetermined number of cells arranged in a predetermined number in a bit direction and having a plurality of cells provided in a plurality of stages and performing partial product generation and addition processing. An adder for a digital multiplier used as the last-stage adder in a digital multiplier including a final-stage adder that performs an addition process on an output signal of a product generation and addition array and outputs a multiplication result output signal. A plurality of adder cells for the number of bits greater than the number of cells in the bit direction in the partial product generation and addition array, wherein the plurality of adder cells are at least one in the bit direction in the partial product generation and addition array. Characterized by being arranged along the bit direction in the partial product generation and addition array so as to be arranged in parallel in the region of Le multiplier dexterity adder. 2. The digital circuit according to claim 1, wherein a plurality of said adder cells are arranged in parallel at positions corresponding to respective cells in the bit direction in said partial product generation and addition array. Adder for multiplier.