JPH1063355A - Low saturated power source circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power source circuit using a bipolar transistor suppressing a reactive current when a power source voltage is low, by negatively feedback-controlling the voltage of the emitter collector of an output PNP transistor by first or second deviation amplifiers so as to maintain to be not less than a reference potential difference. SOLUTION: When a power source voltage is boosted, the base current of the output PNP transistor 6 is suppressed through a driving NPN transistor 5 by the negative feedback output of the first deviation amplifier 4 to maintain an output voltage to be a set voltage. In addition, as a potential difference between the power source voltage and the output voltage is not less than the reference potential difference in this range, the second deviation amplifier 9 controls an NPN transistor 31 to be in a disconnected state and the transistor 5 is controlled exclusively by the amplifier 4. Thereby, voltage between an emitter and a collector is negatively feedback-controlled by the amplifier 9 or 4 without regard to the value of the power source voltage and maintained to be not less than the reference potential difference.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low-saturation power supply circuit used for regulating a power supply voltage of a device.
In particular, it relates to a low-saturation power supply circuit using a bipolar transistor in an output stage.

[0002]

2. Description of the Related Art In a battery-driven device such as a mobile phone, it is desired to suppress unnecessary power consumption as much as possible even in a low-saturation power supply circuit used for regulating a power supply voltage. FIG. 3 is a circuit diagram showing an example of this type of conventional low-saturation power supply circuit using a bipolar transistor in an output stage.

In this conventional low-saturation power supply circuit, an output PNP transistor 6 whose emitter is connected to a power supply terminal 1 and whose collector is grounded via a voltage dividing resistor 7 having resistance values R1 and R2 for obtaining a feedback voltage is provided. And an error amplifier 4 to which the feedback voltage is input to a negative input terminal and the reference voltage Vref generated by the reference voltage generating circuit 3 is input to a positive input terminal.
By controlling the base current of the output PNP transistor 6 via the transistor 5, the voltage of the constant voltage source output from the output terminal 2 connected to the collector of the output PNP transistor 6 is stabilized.

In this conventional example, when the power supply voltage Vcc supplied to the power supply terminal 1 is equal to or lower than the regulation start voltage Va, an emitter is connected to the output terminal 2 in order to suppress a reactive current flowing through the base of the output PNP transistor 6. And a base connected to the base of the output PNP transistor 6, a collector connected to the collector of the PNP transistor 30, a collector connected to the base of the driving NPN transistor 5, and an emitter grounded. And an NPN transistor 31.

FIGS. 4 and 5 show a power supply voltage V of the prior art.
FIG. 4 is a graph showing a relationship between cc, output voltage Vo, and reactive current Iq. The operation of the conventional example will be described below with reference to these graphs.

As shown in FIG. 4, the value of the output voltage Vo is expressed by the following equation when the power supply voltage Vcc is equal to or lower than the regulation start voltage Va and when the power supply voltage Vcc is equal to or higher than the regulation start voltage Va. Vcc <Va: Vo = Vcc−Vx (1) Vcc> Va: Vo = Vref · (1 + R1 / R2) (2) where Vx is the base-emitter voltage Vbe6 of the output PNP transistor 6. And the base-emitter voltage Vbe30 of the PNP transistor 30 and Vx = Vbe6
−Vbe30. Further, the regulation start voltage is Va = Vref · (1 + R1 / R2) + Vx.

That is, when the feedback voltage input to the negative input terminal of the error amplifier 4 is lower than the reference voltage Vref input to the positive input terminal, the error amplifier 4 drives the drive NPN.
The base current of the output PNP transistor 6 is increased via the transistor 5, and when the feedback voltage is higher than the reference voltage Vref, the base current of the output PNP transistor 6 is decreased. Therefore, when the power supply voltage Vcc is sufficiently high, the collector current of the output PNP transistor 6 is controlled so that the feedback voltage Vo · R2 / (R1 + R2) becomes equal to the reference voltage Vref, and the output voltage Vo becomes the set voltage. Vref. (1 + R1 / R2) is maintained.

However, if the power supply voltage Vcc is lower than the regulation start voltage Va, assuming that there is no PNP transistor 30 and NPN transistor 31, the feedback voltage is lower than the reference voltage Vref. Although the base current of the PNP transistor 6 is increased, since the collector voltage and therefore the feedback voltage cannot follow this, the error amplifier 4 and the driving NPN
Transistor 5 has an open gain and the base current remains increased.

The PNP transistor 30 and the NPN transistor 31 are provided for suppressing a reactive current flowing through the base.
Enters the saturation region, the base-emitter voltage of the PNP transistor 30 is biased in the forward direction,
Negative feedback is applied by lowering the base potential of the driving NPN transistor 5 via the transistor 31 and the output PN
The base current of P transistor 6 is reduced. In this conventional example, the reactive current flowing through the base of the output PNP transistor 6 when the power supply potential Vcc is lower than the regulation start voltage Va is thus suppressed.

[0010]

However, this P
The negative feedback by the NP transistor 30 becomes effective only when the output PNP transistor 6 is in the saturation region as described above. Therefore, in the prior art of FIG. 3, the output PNP transistor 6 which is another element of the reactive current is used.
There is a problem that it is not possible to suppress a reactive current flowing through a parasitic transistor formed when the transistor is in a saturated state.

The parasitic transistor is the lateral PN shown in FIG.
As illustrated in the schematic diagram of the structure of the P transistor, in a normal operation region, the p region serving as a collector has a higher potential than the + n region serving as a base, so that the transistor operates as an emitter and is formed using a base p layer as a collector. Then, a parasitic current flowing toward the base is generated from the collector of the output PNP transistor 6 connected to the power supply terminal 1.

As shown in the example of FIG. 5, in the prior art, even when the reactive current flowing through the base is suppressed when the power supply Vcc is equal to or lower than Va, the parasitic transistor formed in the output bipolar transistor 6 considerably reduces the reactive current. Of reactive current has occurred. For example, in a battery-driven device such as a mobile phone, this reactive current causes a rush current when the power is turned on / off, which not only causes a reduction in the use time due to the consumption of the battery, but also reduces the battery when the voltage decreases. There is a problem that the device may be shut down due to rapid exhaustion of the device.

The present invention has been made in order to solve such a problem, and an object of the present invention is to provide a low-saturation power supply circuit using a bipolar transistor which suppresses a reactive current when a power supply voltage drops as much as possible.

[0014]

In order to solve the above problems, a low saturation power supply circuit according to an embodiment of the present invention has an emitter connected to a power supply, a collector connected to an output terminal, and obtaining a feedback voltage. Transistor, a first reference voltage generating circuit for generating a first reference voltage, a feedback voltage obtained from a division point of the voltage dividing resistor, and the first reference voltage. When the feedback voltage is on the power supply potential side with respect to the first reference voltage, the base current of the bipolar transistor is reduced, and the feedback voltage is lower than the first reference voltage on the ground potential side. , The negative current is applied to the bipolar transistor by increasing the base current of the bipolar transistor, and the constant voltage output from the output terminal is A first negative feedback circuit for controlling the voltage of the power supply to a constant value, connected to the power supply, and generating a second reference voltage to output a ground-side potential by the second reference voltage from the potential of the power supply. A second reference voltage generation circuit,
And comparing the collector potential of the bipolar transistor with the output potential of the second reference voltage generating circuit, and when the collector potential is closer to the power supply than the output potential of the second reference voltage generating circuit, When the base potential of the bipolar transistor is reduced by bringing the base potential of the bipolar transistor closer to the power supply potential with an output having a lower impedance than that of the negative feedback circuit, and the collector potential is on the ground side with respect to the output potential of the second reference voltage generating circuit. , The impedance becomes high, and the base potential is left to control of the first negative feedback circuit.
A second negative feedback circuit for controlling a potential difference between the emitters to be equal to or higher than the second reference voltage.

Further, the second reference voltage is higher than a collector saturation voltage of the bipolar transistor and a difference between respective set values of a voltage of the power supply and a voltage of a constant voltage source output from the output terminal. It is characterized by being smaller.

Still further, the first negative feedback circuit includes: a first error amplifier having the first reference voltage input to a positive input terminal and the feedback voltage input to a negative input terminal;
A collector is connected to the base of the bipolar transistor and a first error amplifier controlled by an output of the first error amplifier.
The second negative feedback circuit, wherein the collector potential of the bipolar transistor is input to a positive input terminal, and the output potential of the second reference voltage generation circuit is input to a negative input terminal. A second error amplifier connected to the base of the first common-emitter transistor and a second common-emitter transistor controlled by an output of the second error amplifier. I do.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a basic configuration of an embodiment of a low-saturation power supply circuit according to the present invention. FIG. 2 shows a specific example of the circuit. In FIGS. 1, 2 and 3, the same reference numerals indicate the same or corresponding parts.

As shown in FIG. 1, the low-saturation power supply circuit of the present embodiment has a resistance value R such that an emitter is connected to a power supply terminal 1 and a collector obtains a feedback voltage, similarly to the prior art of FIG.
1, an output PNP transistor 6 grounded via a voltage dividing resistor 7 having R2, and a feedback voltage input to a negative input terminal and a first reference voltage generating circuit 3 connected to a positive input terminal.
Is provided with a first error amplifier 4 to which the reference voltage Vref generated is input. By controlling the base current of the output PNP transistor 6 via the driving NPN transistor 5 by the output of the first error amplifier 4, The voltage of the constant voltage source supplied from the output terminal 2 connected to the collector of the PNP transistor 6 is stabilized.

In this embodiment, in place of the PNP transistor 30 provided for applying negative feedback when the output PNP transistor 6 is in the saturation region in the preceding example of FIG. 3, the reference potential difference from the power supply voltage Vcc is obtained. A second reference voltage generating circuit 8 for generating a voltage lower by Vy, an output voltage Vo being input to a positive input terminal, and a Vcc− obtained by the second reference voltage generating circuit 8 to a negative input terminal.
A second error amplifier 9 to which the voltage of Vy is input is provided. By the output of the second error amplifier 9, the collector is connected to the base of the driving NPN transistor 5 and the emitter is grounded in the same manner as in the previous example of FIG. Through the NPN transistor 31, the feedback is applied to the base of the driving NPN transistor 5 with an output impedance lower than that of the first error amplifier 4, that is, with a higher driving capability.

Here, the value of the reference potential difference Vy is such that the set value of the output voltage is Vs = Vref. (1 + R1 / R2) and the minimum value of the power supply voltage Vcc in the normal operation range is Vcc (m
in), the collector saturation voltage of the output PNP transistor 6, that is, the collector-base voltage of the output PNP transistor 6 is forward biased within the range of Vy <Vcc (min) -Vs, and the parasitic transistor is It is set higher than the formed collector-emitter voltage.

The second error amplifier 9 is connected to the power supply voltage V
If the difference between cc and the output voltage Vo is equal to or greater than the reference potential difference Vy, the base potential of the NPN transistor 31 is lowered,
This is set to a cutoff state, that is, a high impedance, and when the reference potential difference is equal to or smaller than Vy, the driving NPN transistor 5 is controlled via the NPN transistor 31 with an output impedance sufficiently lower than that of the first error amplifier 4 to reduce the base potential. By lowering, the output PNP transistor 6
Decrease the base current.

Hereinafter, the operation of this embodiment will be described. Power supply voltage Vcc is low and output voltage Vo is equal to set voltage Vs
, The first error amplifier 4 operates to increase the base current of the output PNP transistor 6 and increase the output voltage Vo, as in the preceding example of FIG. However, when the output voltage Vo reaches Vcc-Vy, the NPN transistor 31 becomes active and suppresses the base potential of the driving NPN transistor 5, so that the base current of the output PNP transistor 6 does not increase any more. Therefore, when the power supply voltage is in the range of Vcc <Vs + Vy, the output voltage Vo is controlled so as to always follow Vcc with a potential difference equal to the reference potential difference Vy, thereby preventing both the saturation of the output PNP transistor 6 and the occurrence of the parasitic transistor, and invalidating Generation of current is suppressed.

When the power supply voltage rises and reaches Vcc = Vs + Vy, the output voltage Vo reaches the set voltage Vs. When the power supply voltage Vcc further rises, the negative feedback output of the first error amplifier 4 becomes the same as in the preceding example of FIG. As a result, the base current of the output PNP transistor 6 is suppressed via the driving NPN transistor 5, and the output voltage Vo is maintained at the set voltage Vs. In this range, the potential difference between the power supply voltage Vcc and the output voltage Vo is equal to or greater than the reference potential difference Vy. Therefore, the NPN transistor 31 is controlled to be in the cut-off state by the second error amplifier 9, and the driving NPN transistor 5 exclusively uses the first error. Controlled by the amplifier 4.

As described above, according to the low saturation power supply circuit of the present embodiment, the potential difference between the power supply voltage Vcc and the output voltage Vo, that is, the potential difference between the emitter and collector of the output PNP transistor 6 irrespective of the value of the power supply voltage Vcc. Since the voltage is negatively feedback-controlled by the second error amplifier 9 or the first error amplifier 4 and is maintained at least equal to or higher than the reference potential difference Vy, the voltage is invalidated by the base current of the output PNP transistor 6 as illustrated in FIG. An increase in current and an increase in reactive current due to a parasitic transistor can both be suppressed.

In this embodiment, the power supply voltage Vcc is higher than the ground potential, the output bipolar transistor 6 is a PNP transistor, and the driving bipolar transistors 5 and 31 for driving the base are NPN.
Although the embodiment of the present invention has been described as a transistor, when the power supply voltage VCC is lower than the ground potential, an NPN transistor is used as the output bipolar transistor 6 and PNP transistors are used as the driving bipolar transistors 5 and 31. As in the present embodiment, both the reactive current due to the base current and the reactive current due to the parasitic transistor can be suppressed.

[0026]

As described above, according to the low-saturation power supply circuit of the present invention, the reactive current can be suppressed as much as possible regardless of the power supply voltage, the use time is long, and the battery voltage is low. It is possible to provide a low-cost battery-operated device that does not suddenly shut out even when it falls.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific circuit example of the embodiment of FIG. 1;

FIG. 3 is a circuit diagram showing a circuit example of a conventional low-saturation power supply circuit.

4 is a diagram showing a power supply voltage Vcc and an output voltage Vo of the conventional example of FIG.
It is a graph which shows the relationship of.

5 shows a power supply voltage Vcc and a reactive current Iq of the conventional example of FIG.
It is a graph which shows the relationship of.

6 is a graph showing a relationship between a power supply voltage Vcc and a reactive current Iq according to the embodiment of the present invention in FIG. 1;

FIG. 7 is a structural diagram illustrating a parasitic transistor formed in a lateral PNP transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Power supply terminal 2 Output terminal 3 Reference voltage generation circuit 4, 9 Error amplifier 5 Driving NPN transistor 6 Output PNP transistor 7, 84 Dividing resistance 8 Reference potential difference generation circuit 30, 41, 42, 81, 93, 94 PNP transistor 31, 43 , 44, 82, 83, 91, 92, 95, 9
6 NPN transistors 33, 51 Capacitors 45, 61, 85 Constant current generation circuit

Claims (3)

[Claims] 1. A bipolar transistor having an emitter connected to a power supply, a collector connected to an output terminal, and grounded via a voltage dividing resistor for obtaining a feedback voltage, a first transistor for generating a first reference voltage A reference voltage generation circuit, which compares a feedback voltage obtained from a division point of the voltage dividing resistor with the first reference voltage, and when the feedback voltage is closer to a power supply potential than the first reference voltage, Applying a negative feedback to the bipolar transistor by decreasing the base current of the bipolar transistor and increasing the base current of the bipolar transistor when the feedback voltage is on the ground potential side compared to the first reference voltage; A first negative feedback circuit for controlling a voltage of a constant voltage source output from the output terminal to a constant value, connected to the power supply to generate a second reference voltage; A second reference voltage generating circuit that outputs a potential on the ground side by the second reference voltage from the potential of the power supply, and a collector potential of the bipolar transistor and the second reference voltage.
And when the collector potential is closer to the power supply than the output potential of the second reference voltage generating circuit, the output of the first negative feedback circuit has a lower impedance than the first negative feedback circuit. When the base potential of the transistor approaches the power supply potential to reduce the base current and the collector potential is on the ground side from the output potential of the second reference voltage generating circuit, the impedance becomes high and the base potential is reduced to the first potential. A low-saturation power supply circuit including a second negative feedback circuit that controls a potential difference between the collector and the emitter of the bipolar transistor to be equal to or higher than the second reference voltage by leaving control to a negative feedback circuit. 2. The method according to claim 1, wherein the second reference voltage is higher than a collector saturation voltage of the bipolar transistor and a difference between respective set values of a voltage of the power supply and a voltage of a constant voltage source output from the output terminal. The low-saturation power supply circuit according to claim 1, wherein the power supply is smaller than the first power supply. 3. The first negative feedback circuit includes: a first error amplifier having the first reference voltage input to a positive input terminal and the feedback voltage input to a negative input terminal; and a collector. A first common-emitter transistor connected to the base of the bipolar transistor and controlled by an output of the first error amplifier, wherein the second negative feedback circuit has an input in which the collector potential of the bipolar transistor is positive. A second error amplifier whose input is input to a terminal and an output potential of the second reference voltage generating circuit is input to a negative input terminal; and a collector connected to the base of the first common-emitter transistor. 2. The low saturation power supply circuit according to claim 1, further comprising a second common emitter transistor controlled by an output of said error amplifier.