JPH1055631A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase reliability of a buffer memory and a peripheral circuit by processing the error correction of data outputted from the buffer memory by the installation of an EDAC and retrying the recording or output processing operation of the data against external devices and recording/reproducing system according to need, based on the processing result. SOLUTION: The EDACs 24a and 24b are respectively arranged corresponidng to each buffer memory 21A and 21B, thereby a check bit of error correcting code is added to data D1 inputted from the buffer 7 at the recording operation. Further at the recording operation, the data D1 outputted from each buffer memory 21A and 21B are processed for error detection by the check bit, and the error correction is processed when the bit error of one bit is detected, and when the bit error of two or more bits are detected, the data D1 are outputted as they are, and simultaneously, the result of the error correction is informed to a timing control circuit 25. Also at the reproduction, the error detection and the correction processing are executed on inputted data D2 for reproduction by almost the same manner as the recording operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus, and more particularly to a data processing apparatus, for example, which is applied to a large-capacity storage device such as a tape streamer, performs error correction processing on output data of a buffer memory, and makes it necessary based on the error correction processing result. The reliability of the buffer memory and the peripheral circuits is improved by retrying the processing such as data output to the external device and the recording / reproducing system accordingly.

[0002]

2. Description of the Related Art Conventionally, this type of data processing apparatus is designed to input / output data to / from a host computer via a large-capacity buffer memory, thereby providing a recording / reproducing system and a recording / reproducing system. Desired data is recorded and reproduced with an asynchronous external device.

FIG. 21 is a block diagram showing a data processing device. The data processing apparatus 1 sequentially forms recording tracks diagonally on the magnetic tape M, inputs data D1 from an external device such as a host computer, and records the data D1 on the recording tracks. That is, the data processing device 1
The interface (I / F) 2 is controlled by an interface (I / F) control circuit 3 to input and output control commands and data D1 and D2 for recording and reproduction with a host computer.

Therefore, the interface control circuit 3
A control command output from the host computer via the interface 2 is monitored, the control command is notified to the system control circuit 4 if necessary, and a control signal SC1 is output to the buffer memory 5 to subsequently input data D1.
1 is stored in the buffer memory 5. At this time, the interface control circuit 3 adds data necessary for the logical format to the data D1 input from the host computer via the interface 2. At the time of reproduction, the interface control circuit 3 outputs the control signal SC1 and transmits the data stored in the buffer memory 5 to the host computer, contrary to the time of recording. Communication with this host computer is performed by SCSI (Small Co
mputer System Interface), and the data D1 and D2 are input / output in 32-bit parallel.

The buffer memory 5 stores the data D1, D
2 is temporarily held and output at a predetermined timing. FIG.
Is a block diagram showing the buffer memory 5 together with peripheral circuits. The buffer memory 5 is composed of two systems of buffer memories 5A and 5B. By alternately switching the operations of the two systems of buffer memories 5A and 5B, the data writing and reading processes are executed simultaneously and in parallel. Input / output data D1 and D2 at high speed.

At the time of recording, the memory control circuit 6 issues addresses ADA and ADB in accordance with the control signal SC1 to control the address of the buffer memory 5, and thereby stores the data D1 input from the interface 2 via the buffer 7 into the buffer memory. 5 is stored. In response to a control signal SC2 output from the system control circuit 4, the address of the buffer memory 5 is controlled in the same manner, so that the data D1 stored in the buffer memory 5 can be stored at a predetermined timing suitable for recording on the magnetic tape M. Output in block units. Further, the memory control circuit 6 performs the reproduction,
Conversely, by controlling the address in response to the control signal SC2, the data D2 reproduced from the magnetic tape M in predetermined block units is stored in the buffer memory 5, and in response to the control signal SC1. The stored data D2 is output at a timing synchronized with the host computer.

The buffer 7 forms a buffer between the interface 2 and the buffer memory 5, and the buffer 9
A buffer between the buffer memory 5 and the tape controller 11 is configured. The tape controller 11 is composed of a signal processing circuit 10 (FIG. 21) and the like,
And data D1 and D2 are transmitted and received between them.

The signal processing circuit 10 performs data processing on data D1 sequentially input during recording,
Is encoded by an encoding method suitable for the recording of the data and output.
On the contrary, during reproduction, the signal processing circuit 10
After decoding the reproduced data obtained from the circuit 12, the data is processed, whereby the data D2 is reproduced and output to the buffer memory 5.

[0009] The RF circuit 12 is used for recording the signal processing circuit 1.
The rotary head 13 is driven by the output data of 0, whereby the recording tracks are sequentially formed on the magnetic tape M diagonally to record the data D1. Conversely, during playback, R
The F circuit 12 generates and outputs reproduction data from a reproduction signal obtained from the rotary head.

The servo circuit 14 is controlled by the system control circuit 4 to control the operation of the magnetic tape traveling system, so that the data processing device 1 finds the magnetic tape and reads data input from the host computer. D1
And record it. That is, the system control circuit 4
When a write command is input from the host computer, the servo circuit 14 is controlled to rewind the magnetic tape M by a predetermined amount, and then starts running of the magnetic tape M. Record. When a playback command is input from the host computer, the system control circuit 4 rewinds the magnetic tape to a corresponding position, starts running the magnetic tape M, and thereby records the magnetic tape M on the magnetic tape according to a request from the host computer. The reproduced data D2 is reproduced.

As described above, in this type of magnetic recording medium, bit errors cannot be avoided due to dropout or the like. Therefore, in this type of data processing device 1, in recording, data processing in the signal processing circuit 10 is performed. ,
A strong error correction code is added, cross-interleave processing is performed, and the same data is recorded on a magnetic tape in an overlappingly dispersed manner. As a result, in this type of data processing apparatus 1, bit errors in the magnetic recording / reproducing system are maintained at an extremely low value that can be almost ignored, thereby ensuring extremely high reliability. I have.

[0012]

In such a data processing apparatus 1, the recording and reproduction of data on and from a magnetic tape are sufficiently considered with respect to data errors, but the data is not recorded in a buffer memory. The fact is that there is no particular response to errors.

However, in recent years, as the speed of the apparatus has been increased, the capacity of the buffer memory has been increased, and it has been found that errors in the buffer memory cannot be ignored. Specifically, when the data processing device described above with reference to FIG. 21 is operated by using a buffer memory 5 having a memory size of 32 [M bytes], once every several years, even though the data processing device is operating properly. It was found that bit errors due to cosmic rays occurred.

The present invention has been made in consideration of the above points, and it is possible to effectively avoid this kind of bit error and improve the reliability of the buffer memory and peripheral circuits as compared with the related art. It is intended to propose a processing device.

[0015]

According to the present invention, an error correction code is added to data input from an external device or data recording means and stored in a buffer memory. When an error occurs in the data output from the buffer memory based on the error correction processing result, the corresponding data is read from the buffer memory and recorded on the data recording medium via the error correction means, or output to an external device. I do.

If an error occurs in the data output from the buffer memory, the corresponding data is read from the buffer memory and recorded on a data recording medium via an error correction means or output to an external device. By the process of merely accessing the memory, it is possible to confirm a bit error that has occurred accidentally without retransmitting data from an external device or the like.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 2 is a block diagram showing a data processing device according to the embodiment of the present invention. The data processing device 20 monitors input / output data of the buffer memory 21, and retrys the recording / reproducing process as needed based on the monitoring result. In the configuration shown in FIG. 2, the same components as those of the conventional configuration described above with reference to FIG. 21 are denoted by the corresponding reference numerals, and redundant description will be omitted.

FIG. 3 is a block diagram showing a peripheral configuration of the buffer memory 21. Here, the buffer memory 21
Is composed of two systems of buffer memories 21A and 21B, and these two systems of buffer memories 21A and 21B
By alternately switching the operation of B, data write and read processes are executed simultaneously and in parallel, and data D1 and D2 are input / output at high speed. At the time of writing and reading data, the buffer memories 21A and 21B
The data D1 is output to the signal processing circuit 10 in units of 1 ID (117,768 bytes = 29,440 words), and the data D2 input from the signal processing circuit 10 is stored.

EDAC (Error Detection And Correcti
on) 24A and 24B are buffer memories 2 respectively.
At the time of recording, a check bit consisting of a code for error correction is added to data D1 input from the buffer 7 at the time of recording. Here, as shown in FIG. 4, EDACs 24A and 24B have one word (32 bits).
7 bits of check bits are added to the data D1.

Further, at the time of recording, the EDACs 24A and 24B perform an error detection process on the data D1 output from each of the buffer memories 21A and 21B by using a check bit, and perform an error correction process when an error can be corrected. Ie ED
When a 1-bit error is detected for 39-bit data, the ACs 24A and 24B invert the logical level of the corresponding bit and perform error correction. On the other hand, if a bit error of 2 bits or more is detected,
Due to the difficulty of error correction, the data D1 is output as it is.

Further, the EDACs 24A and 24B notify the timing control circuit 25 of the result of the error correction processing by the error flag F1. Here, when the error flag F1 has a value of 1, it indicates that no error has occurred, and when the error flag F1 has a value of 2, it indicates that the error correction processing has been successfully performed.
If the value of the error flag F1 is 2, it is notified that the error could not be corrected.

Further, when outputting the data D1 processed in this manner, the EDACs 24A and 24B add a 4-bit parity code to the 32-bit data D1 and output the data. It is designed to detect bit errors.

On the other hand, at the time of reproduction, the EDACs 24A and 24B receive reproduction data D2 to which a 4-bit parity code is added, as shown in FIG. 6, and perform error detection processing using this parity code. Further, the EDACs 24A and 24B notify the timing control circuit 25 of the error detection result using the error flag F2. This allows EDAC
24A and 24B are transmitted from the signal processing circuit 10 to EDAC2.
With respect to the paths leading to 4A and 24B, an error occurring in this path is detected and notified.

Further, at the time of reproduction, the EDACs 24A and 24B remove the parity code from the data D2 input in this way, and add the same 7-bit check bits as in the recording to add them to the buffer memories 21A and 21B. Store. Further, as shown in FIG. 7, when outputting the data D2 stored in this manner, the EDACs 24A and 24B perform error correction processing using check bits, and notify the error correction processing result to the timing control circuit 25 using an error flag F1. I do. This allows EDAC 24A and 2
4B are buffer memories 21A and 21B during recording and reproduction.
In addition to monitoring the bit errors of the data D1 and D2 at the time of input / output to / from the device, the monitoring result is notified, and when the error can be corrected, the error is corrected.

The tape controller 27 is composed of the signal processing circuit 10 (FIG. 2) and the like, and processes and outputs data D1 inputted from the buffer memories 24A and 24B during recording. At this time, the tape controller 27
Detects a bit error of the data D1 by the parity code added to the data D1, and outputs the detection result to the error information EE.
It outputs to the system control circuit 22 as 1. Thereby, in the data processing device 20, the buffer memories 24A and 2A
4B to the signal processing circuit 10, the data D1
Is detected, and a detection result is output. Also, the tape controller 27
At the time of reproduction, a 4-bit parity code is added to the data D2 output from the signal processing circuit 10 and output, so that a bit error can be detected based on the parity code.

Further, at the time of recording / reproduction, the tape controller 27 detects the last data of the data D1 and D2 input in units of 1 ID, thereby detecting a framing error. Here, the framing error is an error in which the block structure of data in units of 1 ID is disturbed for some reason. In this embodiment, at the time of recording, the interface control circuit 3 uses “0F0” in hexadecimal notation.
The data of “F0F0F” is added to the end of each block, and if the data at the end is different from this, the tape controller 27 determines that it is a framing error and outputs error information EE1.

The memory control circuit 26 controls the addresses of the buffer memories 21A and 21B according to the control signal SC1 output from the interface control circuit 3 and the control signal SC2 input to the timing control circuit 25, Thereby, at the time of recording / reproduction, the memory spaces of the buffer memories 21A and 21B are sequentially designated, and the data D1 and D2 are
B, and read the stored data D1 and D2.

The timing control circuit 25 is a control circuit for controlling the buffer memories 21A and 21B and peripheral circuits, and controls the system control circuit 2 according to the error flag F1.
2 and the error information EE3 in the interface control circuit 3.
Notify. At this time, the timing control circuit 25 monitors the addresses ADA and ADB issued by the memory control circuit 26, and notifies the system control circuit 22 of the addresses of the buffer memories 21A and 21B corresponding to the data in which the error has occurred. . Further, the timing control circuit 25 controls the switching of the operation of the buffer memories 21A and 21B as described later under the control of the system control circuit 22 in response to the error information EE1 and EE3.

Thus, in this embodiment, at the time of recording, the interface 2 is connected through the route shown in FIG.
And outputs the input data D1 to the signal processing circuit 10,
At this time, after outputting data from the EDACs 24A and 24B to the buffer memories 21A and 21B, a bit error occurring between the time when the data is input from the buffer memories 21A and 21B to the EDACs 24A and 24B,
In ACs 24A and 24B, bit errors are monitored by check bits, and error correction is performed as much as possible. In addition, the tape controller 2 is
For the period up to 7, a bit error is monitored by the tape controller 27 using the parity code. Further, a framing error is monitored by the tape controller 27 between the interface 2 and the tape controller 27.

On the other hand, as shown in FIG. 9, during reproduction, the tape controller 27 sends the EDAC 24A.
And 24B, EDAC 24A and 2
In 4B, the bit error is monitored by the parity code. Further, after outputting data from the EDACs 24A and 24B to the buffer memories 21A and 21B, the EDACs 24A and 24B are output from the buffer memories 21A and 21B.
About the bit error that occurred until input to
In the EDACs 24A and 24B, bit errors are monitored by check bits and error correction is performed as much as possible.
Further, a framing error is monitored by the tape controller 27 from the magnetic recording / reproducing system to the tape controller 27.

The system control circuit 22 (FIG. 2) controls the entire operation of the data processing apparatus 20 in response to a control command input from an external device, thereby transferring the data D1 input from the external device to a magnetic tape. M, and reproduces the data D2 recorded on the magnetic tape M and outputs it to an external device. At this time, the system control circuit 22 outputs the error information EE output from the timing control circuit 25 or the like.
The overall operation is switched and controlled as necessary in accordance with 1 to EE2, so that bit errors caused by the buffer memories 21A and 21B and peripheral circuits are repaired as much as possible. When a bit error occurs, a record is left in the history memory 23 composed of a non-volatile memory, and a warning is issued to the user as necessary based on the record.

That is, when a write control command is input from an external device, the system control circuit 22 switches the entire operation to a recording operation mode, and is input via the interface 2 at a timing synchronized with the operation of the external device. The data D1 is sequentially stored in the buffer memories 21A and 21B. In this state, as shown in FIG. 1, the system control circuit 22 proceeds from step SP1 to step SP2, sets the start address of the buffer memories 21A and 21B, and then proceeds to step SP3, where one ID is stored in the buffer memories 21A and 21B. Is read from the buffer memories 21A and 21B and transferred to the signal processing circuit 10.

At this time, in the subsequent step SP4, the system control circuit 22 determines whether or not an error has occurred based on the error information EE1 and EE2. If a negative result is obtained here, the process proceeds to step SP5. Here, the system control circuit 22 determines the presence or absence of the subsequent data D1, and if the subsequent data D1 is stored in the buffer memories 21A and 21B, the process proceeds to step SP2, and the same processing is repeated for the next 1 ID data D1. . On the other hand, if the subsequent data D1 is not stored in the buffer memories 21A and 21B, the process proceeds from step SP5 to step S5.
The process moves to P6, and this processing procedure ends. Thus, the system control circuit 22 records the data D1 on the magnetic tape M in units of 1 ID while monitoring the error.

In this series of processing, when an error occurs, the system control circuit 22 records one ID of data, and then proceeds to step SP7 to determine the type of error. The error that occurred here is EDAC 24A and 24
In the case of a 1-bit error detected by B, the system control circuit 22 proceeds to step SP8, executes a 1-bit error process described later, and returns to step SP5. On the other hand, if the error that has occurred is a framing error detected by the tape controller 27, step SP9
Then, a framing error process described later is executed, and the process returns to step SP5.

If the generated error is a two-bit error detected by the EDACs 24A and 24B, the system control circuit 22 proceeds to step SP10, executes a two-bit error process described later, and returns to step SP5. If the error that has occurred is a parity error detected by the tape controller 27, the system control circuit 22 proceeds to step SP11, executes a parity error process described later, and returns to step SP5. Further, in the 1-bit error processing or the like, if the system control circuit 22 determines that the device has failed, the system control circuit 22 proceeds to step SP5
Without returning to the above, the recording process is stopped, and recording of erroneous data is prevented.

Here, the one-bit error means a bit error that has been successfully corrected among the bit errors detected by the check bit, and the two-bit error is a bit error similarly detected by the check bit. Of these, means a bit error that is difficult to correct. Further, the parity error means an error detected by the EDAC 24A, 24B or the tape controller 27 by the parity code added to the data D1, D2. As a result, the system control circuit 22 executes a processing procedure corresponding to the type of error that has occurred, thereby improving the reliability of the buffer memories 21A and 21B and peripheral circuits within a practically sufficient range.

FIG. 10 is a flowchart showing a one-bit error processing routine. System control circuit 22
In this 1-bit error process, step SP2
0 to step SP21, the timing control circuit 2
Based on the error information EE1 notified from 5, the corresponding data D1 is read again from the area corresponding to the data in which the error has occurred. Subsequently, the system control circuit 22
In step SP22, it is determined whether a one-bit error has occurred again for the read data D1. If the data can be read correctly, the system control circuit 22 proceeds from step SP22 to step SP2.
Move to 3 and set the error mode.

Data errors occurring in this type of data processing apparatus can be roughly classified into hard errors and soft errors. Here, the hard error generally means permanent data destruction caused by a failure of a circuit or a device (such as an IC). A hard error in a memory is a state in which a unit (memory cell) for storing a certain bit (0 or 1) of data has failed, and the bit assigned to the corresponding memory cell is always held at 0 or 1. When an abnormality occurs in a specific one bit, an abnormality may occur in the entire specific address space.

On the other hand, the data is accidentally destroyed,
A case where a bit error cannot be reproduced is called a soft error.
Soft errors in memory include those in which data changes after reading data from memory cells in a memory IC,
There are cases where the data in the memory cell itself changes.The former is caused by a soft error in the peripheral circuits of the memory, and the latter is difficult to read the correct data no matter how many times the same address is subsequently read. become. However, a soft error in the memory does not mean that the memory itself (hardware) has been destroyed. Therefore, if correct data is written again, correct data can be read.

Thus, in this embodiment, an error mode is defined as shown in FIG. 11 corresponding to the cause of the error. That is, the buffer memories 21A and 21A
In the peripheral circuits other than B, if it is considered that the logical value of the data has changed due to noise or the like, the error mode is set to E.
Let it be 1. When it is determined that a failure occurs in a peripheral circuit other than the buffer memories 21A and 21B, the error mode is set to E2, and it is considered that the logic value of the data has changed for some reason when the data is output from the buffer memories 21A and 21B. In this case, the error mode is set to E3.

If the data in the buffer memories 21A and 21B is changed, the error mode is set to E.
4, when it is considered that the buffer memories 21A and 21B have failed and the buffer memories 21A and 21B are about to fail, the error modes are set to E5 and E6, respectively.

As a result, the system control circuit 22 determines the error detection result based on the error information EE1 detected first,
The cause of the one-bit error is self-diagnosed based on the error detection result detected by rereading the data based on the error information EE1, and the entire operation is switched based on the self-diagnosis result. That is, when a negative result is obtained in step SP22, the system control circuit 22
Initial one-bit errors are stored in buffer memories 21A and 21B.
In the peripheral circuits other than the above, when the logical value of data changes due to noise or the like, or when buffer memories 21A and 21B
At the time of output from, it is considered that the logical value of the data has changed for some reason, and the error mode is set to the corresponding E1 and E3.

The system control circuit 22 records the time at which the bit error occurred, the type of error, the error mode, and the corresponding addresses ADA and ADB of the buffer memories 21A and 21B in the history memory 23 in the subsequent step SP24. Thereafter, the process moves to step SP25 and returns to the main routine. That is, in this case, in the data D1 in which the bit error has occurred, the error has been correctly corrected by the check bit and recorded on the magnetic tape M, and the bit error is considered to have occurred accidentally. System control circuit 2
2 terminates this one-bit error processing so as not to interfere with the recording of the subsequent data D1 stored in the buffer memories 21A and 21B or input via the interface 2.

On the other hand, if a one-bit error is detected again in the read operation, the system control circuit 22 proceeds from step SP22 to step SP26. Here, the system control circuit 22 performs
The correct data D1 subjected to the error correction processing by the EDACs 24A and 24B is stored in the same address space and then read again. Subsequently, the system control circuit 22 proceeds to step SP
The process proceeds to 27 to determine whether a one-bit error has occurred again in the read data.

If no 1-bit error occurs,
When data is stored in the buffer memories 21A and 21B, the data D1 itself changes for some reason such as noise. In this case, since the data D1 is considered to be an accidental bit error, the system control circuit 22 proceeds to step SP28, and Set the mode to the corresponding E4. Further, the system control circuit 22 proceeds to step SP24,
The error occurrence time, the error mode, and the like are recorded in the history memory 23, and the routine goes to Step SP25. In this case, the system control circuit 22 also checks that the data D1 in which the bit error has occurred is correctly corrected by the check bit and recorded on the magnetic tape M. Returning to the main routine so as not to interfere with the recording of the subsequent data D1 stored in the buffer memories 21A and 21B or input via the interface 2 because it is considered to have occurred.

On the other hand, if a one-bit error occurs again, the system control circuit 22 proceeds from step SP27 to step SP29. In this case, since this one-bit error is considered to be a failure in the corresponding address space of the buffer memories 21A and 21B, the system control circuit 22 sets the error mode to the corresponding error mode E5.
After that, the process moves to step SP24. In this case, the system control circuit 22 also corrects the error in the data D1 in which the bit error has occurred and corrects the error with the check bit and records the data on the magnetic tape M. And correct data can be recorded on the magnetic tape M, so that the recording of the subsequent data D1 stored in the buffer memories 21A and 21B or input via the interface 2 is not hindered. Return to Lucin.

FIG. 12 is a flow chart showing the processing routine of the 2-bit error processing. In the two-bit error process, the system control circuit 22 proceeds from step SP30 to step SP31. In this case, the erroneous data D2 is recorded on the magnetic tape M, so that the magnetic tape M is rewound and caught. ,
The running of the magnetic tape M is started, and the data D1 is recorded again in the corresponding area of the magnetic tape M. At this time, the system control circuit 22 reads the corresponding 1ID data D1 from the buffer memories 21A and 21B and records it on the magnetic tape.

When the recording of the data D1 is retried in this manner, the system control circuit 22 proceeds to step SP32
Then, it is determined again whether a 2-bit error has occurred. Thereby, the system control circuit 22 self-diagnoses the cause of the 2-bit error based on the error detection result based on the error information detected first and the retry error detection result based on the error information, and based on the self-diagnosis result. To switch the whole operation.

That is, when the data D1 has been correctly read in step SP31, the system control circuit 22 proceeds from step SP32 to step SP33. In this case, the system control circuit 22 sets the error mode to E1 and E3 in step SP33 because it is considered that a two-bit error has occurred accidentally due to the influence of noise or the like. Further, in this case, since the correct data is recorded on the magnetic tape M by the retry of the data recording, the process proceeds to step SP34, and the error occurrence time and the like are recorded in the history memory 23. Further, the system control circuit 22 proceeds to step SP35 and returns to the main routine.

Thus, the system control circuit 22 ends this processing procedure without interrupting the processing of the external device by the retransmission request.

On the other hand, if a two-bit error is detected again in the data recording retry, the system control circuit 22
Moves from step SP32 to step SP36. Here, the system control circuit 22 issues a data retransmission request to the external device, rewinds the magnetic tape M and starts running, and thereby the data D retransmitted from the external device is transmitted.
1, the data recording is retried in the corresponding area of the magnetic tape M.

Subsequently, the system control circuit 22 proceeds to step SP37, and judges again whether or not a 2-bit error has occurred in the reproduced data. Thereby, the system control circuit 22 self-diagnoses the cause of the 2-bit error based on the error information detected first and the error detection result detected in the retry of steps SP31 and SP36 executed based on the error information, The whole operation is switched based on the self-diagnosis result.

That is, if no 2-bit error occurs here, the system control circuit 22
At the time of storing the data in A and 21B, the data D1 itself is changed due to noise or the like, and it is considered that this is an accidental bit error. Therefore, the flow shifts to step SP38 to set the error mode to the corresponding E4. Further, the system control circuit 22 proceeds to step SP34, records the error occurrence time, the error mode, and the like in the history memory 23, and then proceeds to step SP35 to return to the main routine.

Thus, in this embodiment, the number of check bits is set so as to correspond to the most frequently occurring 1-bit error, and a retransmission request is not issued to an external device for the 1-bit error. Also, correct data is recorded by internal processing, and for a bit error of 2 bits or more, a retransmission request is issued to an external device as necessary to record the correct data. That is, in the case of a 1-bit error, if the data processing device 20 operates properly, as described above, it occurs only once in a few years, and in the case of a 2-bit error, it is much more complicated than this 1-bit error. Occurrence probability is reduced.
As a result, in the data processing device 20, an increase in the capacity of the buffer memories 21A and 21B due to the addition of check bits is effectively avoided, and sufficient reliability for practical use is ensured.

On the other hand, if a two-bit error occurs again, the system control circuit 22 proceeds from step SP37 to step SP39. Here, the system control circuit 2
2 judges whether a 2-bit error has occurred at the same address, and if a positive result is obtained, it is considered that the corresponding address space of the buffer memories 21A and 21B has failed in this case, and the process proceeds to step SP39. The error mode is set to the corresponding error mode E5.

Further, in this case, if another memory space is used, correct data can be recorded on the magnetic tape M. However, if the same memory space is used, the magnetic tape M
Since it is difficult to record the correct data in step SP41, the process proceeds to step SP41, and the entire operation is stopped and controlled with priority given to reliability. At this time, the system control circuit 22 issues an error message to an external device serving as a host computer via the interface control circuit 3 to notify the user that data could not be correctly recorded and that the operation should be stopped due to a system abnormality. Further, the system control circuit 22 leaves a record in the history memory 23, and proceeds to step SP4.
Then, the processing procedure is terminated without returning to the main routine.

On the other hand, if a two-bit error occurs at a different address, the system control circuit 22 proceeds from step SP39 to step SP43. In this case, since it is considered that the buffer memories 21A and 21B are about to fail, the system control circuit 22 sets the error mode to the corresponding error mode E6. Further, in this case, even if the data is retransmitted and the data recording is retried, it is considered that the data cannot be correctly recorded. Therefore, the process proceeds to step SP41 to stop and control the entire operation and notify the user of a warning. Also in this case, similarly, the record is left in the history memory 23, and the process proceeds to step SP42 to end the processing procedure without returning to the main routine. Note that data D is sent from the host computer.
If there is no retransmission of 1, after issuing a message to that effect, the system control circuit 22 proceeds from step SP36 to step SP42 and stops the entire operation.

FIG. 13 is a flowchart showing the processing routine of the parity error processing. In this parity error process, the system control circuit 22 executes step S
The process proceeds from step P45 to step SP46. In this case, the erroneous data D1 is recorded on the magnetic tape M, so that the magnetic tape M is rewound and cueed, and then the magnetic tape M starts running. Data D1 is recorded again in the corresponding area. At this time, the system control circuit 22
Is the corresponding 1I from the buffer memories 21A and 21B.
The data D1 of D is read and recorded on the magnetic tape.

When the recording of the data D1 is retried in this manner, the system control circuit 22 proceeds to step SP47.
Then, it is determined again whether a parity error has occurred. Accordingly, the system control circuit 22 self-diagnoses the cause of the parity error based on the error detection result detected first and the error detection result of the retry, and switches the entire operation based on the self-diagnosis result.

That is, if the system control circuit 22 has successfully read the data in step SP46, the process proceeds from step SP47 to step SP48. Here, in this case, it is considered that a parity error has occurred accidentally due to noise or the like, and the system control circuit 22 sets the error mode to E1 in step SP48. Further, in this case, since the correct data has been recorded on the magnetic tape M by the retry of the data recording, the process proceeds to step SP49. Here, the system control circuit 22 records the error occurrence time and the like in the history memory 23, moves to step SP50, and returns to the main routine.

As a result, the system control circuit 22 terminates this processing procedure without issuing a retransmission request to the external device and interfering with the processing of the external device.

On the other hand, if a parity error is detected again in the retry of data recording, the system control circuit 2
In step 2, the process moves from step SP47 to step SP51.
Here, the system control circuit 22 includes EDACs 24A and 24A.
When the abnormality from B to the tape controller 27 is reproduced, the error mode is set to E2. Further, in this case, since it is difficult to record correct data even in the case where rewriting is repeated, the system control circuit 22 proceeds to step SP52 and controls stop of the entire operation. At this time, the system control circuit 22 notifies the user via the interface control circuit 3. Further, the system control circuit 22 leaves the record in the history memory 23, and proceeds to step SP53 to end the processing procedure without returning to the main routine.

FIG. 14 is a flowchart showing a processing routine of the framing error processing. In the framing error process, the system control circuit 22 proceeds from step SP55 to step SP56, in which the erroneous data D1 is recorded on the magnetic tape M. The running of the magnetic tape M is started, and the data D1 is recorded again in the corresponding area of the magnetic tape M. At this time, the system control circuit 22 reads the corresponding 1ID data D1 from the buffer memories 21A and 21B and records it on the magnetic tape.

Subsequently, the system control circuit 22 proceeds to step SP57, and determines again whether or not a framing error has occurred. Thereby, the system control circuit 22 self-diagnoses the cause of the framing error based on the error detection result detected first and the error detection result detected in the retry, and performs the entire operation based on the self-diagnosis result. Switch.

That is, if the system control circuit 22 has successfully read the data in step SP56, the process proceeds from step SP57 to step SP58. In this case, since it is considered that a framing error has occurred accidentally due to noise or the like, the system control circuit 22 sets the error mode to E1 in step SP58. Further, in this case, since the correct data has been recorded on the magnetic tape M by the retry of the data recording, the process proceeds to step SP59, and the error occurrence time and the like are recorded in the history memory, and then proceeds to step SP60 to return to the main routine.

On the other hand, if the framing error is detected again in the data recording retry, the system control circuit 22 proceeds from step SP57 to step SP61. Here, the system control circuit 22 issues a data retransmission request to the external device, rewinds the magnetic tape M and starts running, and thereby uses the data D1 retransmitted from the external device to execute the data retransmission. Retry data recording in the corresponding area.

Subsequently, the system control circuit 22 proceeds to step SP62, and determines whether or not a framing error has occurred again for the retransmitted data. Thus, the system control circuit 22 self-diagnoses the cause of the framing error based on the error information detected first and the error detection results detected in steps SP56 and SP61, and performs the entire operation based on the self-diagnosis result. Switch.

That is, when no framing error occurs, the system control circuit 22
At the time of storing the data in A and 21B, it is considered that the data D1 has changed due to noise or the like, and it is considered to be an accidental error. Therefore, the flow shifts to step SP63 to set the error mode to the corresponding E4. Further, the system control circuit 22 proceeds to step SP59, records the error occurrence time, the error mode, and the like in the history memory 23, and proceeds to step SP60.
And return to the main routine.

On the other hand, if a framing error occurs again, the system control circuit 22 proceeds to step SP6.
The process proceeds to step SP64 from step 2. Here, the system control circuit 22 sets the error mode to E2 when the same abnormality is reproduced. Then, the system control circuit 2
The process proceeds to step SP65 to stop and control the entire operation and notify the user via the interface control circuit 3. After the record is left in the history memory 23, the process proceeds to step SP66, and the processing procedure ends without returning to the main routine.

By these processes, the system control circuit 22
Records the data D1 input from the external device on the magnetic tape M with extremely high reliability. It should be noted that the system control circuit 22 is configured to perform a 1-bit error process, a 2-bit error process, a parity error process, and a framing error process when different errors are separately detected.
Priority is given to error processing corresponding to these separately detected errors according to the type of error that has occurred, and error processing corresponding to errors detected separately is performed concurrently with the error processing being executed. It has been made to be.

FIG. 15 is a flowchart showing a main processing routine of the system control circuit 22 during data reproduction. When a read control command is input from an external device, the system control circuit 22 switches the entire operation to a reproduction operation mode, and sequentially outputs data D2 output from the signal processing circuit 10 at a timing synchronized with reproduction of the magnetic tape M. Is stored in the buffer memories 21A and 21B. In this state, when the consent of data transmission is obtained from the external device, the system control circuit 22 proceeds from step SP71 to step SP72, and stores the buffer memories 21A and 2A.
After setting the start address of 1B, step SP73
And sends the data D2 for one ID from the buffer memories 21A and 21B to the external device.

At this time, in the following step SP74, the system control circuit 22 determines whether or not an error has occurred based on the error information EE1 and EE2. If a negative result is obtained here, the process proceeds to step SP75. Here, the system control circuit 22 determines the presence or absence of the following data D2,
If the subsequent data D2 is held in the buffer memories 21A and 21B, the process moves to step SP72, and the next 1I
The same processing is repeated for the data D2 for D. On the other hand, the following data D2 is stored in the buffer memories 21A and 2A.
If it is not held in 1B, the process moves from step SP75 to step SP76, and this processing procedure ends. Thereby, the system control circuit 22 outputs the data D2 to the external device in units of 1 ID while monitoring the error.

In this series of processing, when an error occurs, the system control circuit 22 sends the data D2 for one ID.
Is output, the process proceeds to step SP77, and the type of error is determined. If the error occurred here is a one-bit error detected by the EDACs 24A and 24B, the system control circuit 22 proceeds to step SP78, executes a one-bit error process described later, and returns to step SP75. On the other hand, if the error that has occurred is a framing error detected by the tape controller 27, the process proceeds to step SP79, executes a framing error process described later, and returns to step SP75.

If the generated error is a two-bit error detected by the EDACs 24A and 24B, the system control circuit 22 proceeds to step SP80, executes a two-bit error process described later, and returns to step SP75. Further occurring errors are EDAC 24A and 24B
In the case of a parity error detected by (1), the system control circuit 22 proceeds to step SP81, executes a parity error process described later, and returns to step SP75. If it is determined in the 1-bit error processing or the like that the device has failed, the system control circuit 22 proceeds to step SP.
Without returning to step 75, the reproduction process is stopped and output of erroneous data is prevented.

FIG. 16 is a flowchart showing a one-bit error processing routine during reproduction. In the one-bit error process, the system control circuit 22 proceeds from step SP85 to step SP86, and based on the error information EE3 notified from the timing control circuit 25, re-reads the data corresponding to the area corresponding to the data in which the error has occurred. Read D2. Subsequently, the system control circuit 22 proceeds to step SP87, and determines whether a one-bit error has occurred again for the read data D2. Here, if the data can be read correctly, the system control circuit 22 proceeds from step SP87 to step SP88, and sets the error mode to E1 and E2.

Thus, even during reproduction, the system control circuit 22 self-diagnoses the cause of the one-bit error based on two error detection results, and switches the entire operation based on the self-diagnosis result. That is, if a negative result is obtained in step SP87, the system control circuit 22
Means that the initial 1-bit error is stored in the buffer memories 21A, 2A,
In the peripheral circuits other than 1B, when the logical value of the data changes due to noise or the like, or when the buffer memories 21A,
At the time of output from 1B, it is considered that the logical value of the data has changed for some reason, and the error mode is set to the corresponding E1 and E3.

Thus, in the following step SP89, the system control circuit 22 records this bit error together with related information in the history memory 23, and then proceeds to step S89.
It moves to P90 and returns to the main routine. That is, in this case, in the data D1 in which the bit error has occurred,
The system control circuit 22 interferes with the output of the subsequent data D2 because the error correction processing is correctly performed by the check bit and the error is output to the external device, and the bit error is considered to have occurred accidentally. This one-bit error processing is terminated so as not to occur.

On the other hand, if a one-bit error is detected again in the read operation, the system control circuit 22 proceeds from step SP87 to step SP91. Here, the system control circuit 22 performs
The correct data D1 subjected to the error correction processing by the EDACs 24A and 24B is stored in the same address space and then read again. Subsequently, the system control circuit 22 proceeds to step SP
The process then proceeds to 92, where it is determined whether a one-bit error has occurred again for the read data.

If no 1-bit error occurs,
When data is stored in the buffer memories 21A and 21B, it is considered to be an accidental bit error in which the data D2 itself has changed due to noise or the like. The system control circuit 22 proceeds to step SP93, sets the error mode to E4, moves to step SP94, leaves the record in the history memory 23, and moves to step SP90.

On the other hand, if a 1-bit error occurs again, the system control circuit 22 proceeds from step SP92 to step SP94. In this case, since the one-bit error is considered to be a failure in the corresponding memory space of the buffer memories 21A and 21B, the system control circuit 22 sets the error mode to the corresponding error mode E5, and then proceeds to step SP89. . In this case, the system control circuit 22 also corrects the error in the data D1 in which the bit error has occurred and corrects the error with the check bit and outputs the data to the external device. By returning the correct data, the main routine is returned so as not to hinder the output of the subsequent data D2.

FIG. 17 is a flowchart showing the processing routine of the 2-bit error processing. In the two-bit error process, the system control circuit 22 proceeds from step SP100 to step SP101. In this case, the erroneous data D2 is output to the external device, so that the external device declares retransmission of the data D2.
Further, the system control circuit 22 includes a buffer memory 21A.
And the data D2 having the same ID is read out from the external memory and output from the buffer memories 21A and 21B.
Retry the data output from 1B.

Subsequently, the system control circuit 22 proceeds to step SP102, and determines again whether or not a two-bit error has occurred, whereby the system control circuit 22 determines the cause of the two-bit error based on successive error detection results. The self-diagnosis is performed, and the entire operation is switched based on the self-diagnosis result.

That is, when the data can be correctly output in step SP101, the system control circuit 22 proceeds from step SP102 to step SP103. In this case, the system control circuit 22 sets the error mode to E1 and E3 in step SP103 because it is considered that a two-bit error has occurred accidentally due to noise or the like. Further, in this case, since the correct data has been output to the external device by retrying the data output, the process proceeds to step SP104, and the history memory 2
After recording a record in No. 3, the process moves to step SP105 and returns to the main routine.

As a result, the system control circuit 22 operates the buffer memory 2 without driving the magnetic tape running system.
By retrying data output from 1A and 21B, 2
The bit error is repaired and the processing procedure ends.

On the other hand, if a 2-bit error is detected again in the data output retry, the system control circuit 22
Moves from step SP102 to step SP106. Here, the system control circuit 22 declares the data retransmission to the external device again, rewinds the magnetic tape M, and retries the data reproduction of the corresponding 1 ID.

Subsequently, the system control circuit 22 proceeds to step SP107, and
It is determined again whether a two-bit error has occurred. Where 2
If a bit error does not occur, it is considered that the data D2 itself is an accidental bit error that has changed due to noise or the like, so the flow proceeds to step SP108, and the error mode is set to the corresponding E4. Further, the system control circuit 22 proceeds to step SP104 to leave a record in the history memory 23, and then proceeds to step SP105 to return to the main routine.

On the other hand, if a two-bit error occurs again, the system control circuit 22 proceeds to step SP107.
The process moves to step SP109. Here, the system control circuit 22 determines whether or not a 2-bit error has occurred at the same address, and if a positive result is obtained, in this case, it is considered that the corresponding address space of the buffer memories 21A and 21B has failed. Moving to step SP110, the error mode is set to the corresponding error mode E5.

Subsequently, the system control circuit 22 proceeds to step SP111, and controls the entire operation to stop with priority given to reliability. At this time, the system control circuit 22 issues an error message to an external device, which is a host computer, via the interface control circuit 3 to notify the user that it is difficult to output data correctly and that the operation is stopped due to a system abnormality. Notice. Also, history memory 2
After recording in step 3, the process proceeds to step SP112, where the processing procedure is terminated without returning to the main routine.

On the other hand, if a two-bit error occurs at a different address, the system control circuit 22 proceeds from step SP109 to step SP113. In this case, since it is considered that the buffer memories 21A and 21B are about to fail, the system control circuit 22 sets the error mode to the corresponding error mode E6.
Further, in this case, since it is considered that the data cannot be correctly output, the process proceeds to step SP111 to stop and control the entire operation and notify the user of a warning. After the record is left in the history memory 23, step S
Moving to P112, the processing procedure ends without returning to the main routine. If permission of data retransmission is not obtained from the host computer, the system control circuit 22
After issuing a message to that effect, the process moves from step SP101 to step SP112 and stops the entire operation.

FIG. 18 is a flowchart showing a processing routine of the parity error processing at the time of reproduction. In this parity error processing, the system control circuit 22 proceeds from step SP115 to step SP116, and in this case declares data retransmission to the external device when the incorrect data D2 is output to the external device.
Further, the system control circuit 22 retries the data reproduction by rewinding the magnetic tape M and reproducing the same ID.

When the reproduction of the data D2 is retried in this way, the system control circuit 22 proceeds to step SP11
Then, it is determined whether or not a parity error has occurred again, whereby the cause of the parity error is self-diagnosed based on successive error detection results, and the entire operation is switched based on the self-diagnosis result. That is, if the system control circuit 22 has successfully output the data in step SP116, the process proceeds from step SP117 to step SP118. Here, in this case, since it is considered that a parity error has occurred accidentally due to noise or the like, the system control circuit 22 proceeds to step SP118.
, The error mode is set to E1. Further, in this case, since the correct data has been output to the external device by retry of the data reproduction, the process proceeds to step SP119, and after the record is left in the history memory 23, the process proceeds to step SP1.
Move to 20 and return to the main routine.

On the other hand, if a parity error is detected again in the retry of data reproduction, the system control circuit 2
In step 2, the process moves from step SP117 to step SP121. Here, the system control circuit 22 sets the error mode to E2 when the abnormality is reproduced from the tape controller 27 to the EDACs 24A and 24B. Further, in this case, since it is difficult to output correct data even in the case where rewriting is repeated, the system control circuit 22 proceeds to step SP122 and performs stop control of the entire operation. At this time, the system control circuit 22 notifies the user via the interface control circuit 3. After the record is left in the history memory 23, step S
Moving to P123, the processing procedure ends without returning to the main routine. Also in this case, if the permission of data retransmission is not obtained from the host computer, the system control circuit 22 issues a message to that effect, and then proceeds from step SP116 to step SP123 to stop the entire operation.

FIG. 19 is a flowchart showing a processing routine for framing error processing during reproduction. In this framing error process, the system control circuit 22 executes steps SP125 to SP1.
The process proceeds to step S26, where the erroneous data D2 is output to the external device, so that the external device is declared to retransmit data. Further, the system control circuit 22 retries the data reproduction by rewinding the magnetic tape M and reproducing the data D2 having the same ID.

Subsequently, the system control circuit 22 proceeds to step SP127, and determines again whether or not a framing error has occurred. Thereby, the system control circuit 22
At the time of reproduction, the cause of the framing error is also self-diagnosed, and the entire operation is switched based on the self-diagnosis result. That is, if the system control circuit 22 can correctly output the data D2 in step SP126, the system control circuit 22 proceeds from step SP127 to step SP127.
Move to 128. In this case, since it is considered that a framing error has occurred accidentally due to noise or the like, the system control circuit 22 determines in step SP128 that
Set the error mode to E1. Further, in this case, since the correct data has been output to the external device in the retry of the data reproduction, the process proceeds to step SP129, and after recording in the history memory, the process proceeds to step SP130 to return to the main routine.

On the other hand, if a framing error is detected again in the retry of data reproduction, the system control circuit 22 proceeds from step SP127 to step SP131.
Move on to Here, the system control circuit 22 sets the error mode to E2 when the same abnormality is reproduced. Subsequently, the system control circuit 22 proceeds to step SP13
Then, the whole operation is stopped and controlled, and the user is notified via the interface control circuit 3. Further, a record is left in the history memory 23, the process proceeds to step SP133, and the processing procedure ends without returning to the main routine. In this case also, if permission of data retransmission is not obtained from the host computer, the system control circuit 22 issues a message to that effect, and then proceeds from step SP126 to step SP133 to stop the entire operation.

The above processing allows the system control circuit 22
Reproduces the data D2 recorded on the magnetic tape M and outputs it to an external device with extremely high reliability. Note that, when different errors are separately detected in the 1-bit error processing, the 2-bit error processing, the parity error processing, and the framing error processing during reproduction, the system control circuit 22 performs these additional processing according to the content of the generated errors. The error processing corresponding to the detected error is executed with priority, and the error processing corresponding to the separately detected error is executed simultaneously and in parallel with the error processing being executed.

FIG. 20 is a flowchart showing a processing procedure of the system control circuit 22 for processing the error history stored in the history memory 23 in this way. The system control circuit 22 executes this processing procedure periodically (for example, once a minute). That is, the system control circuit 22 proceeds from step SP140 to step SP141, and searches the contents of the history memory 23.

Subsequently, the system control circuit 22 proceeds to step SP142, and determines whether or not the frequency of occurrence of an error exceeds a predetermined value. Here, for example, when an error occurs once or more a day, the system control circuit 22 determines that the occurrence frequency exceeds a specified value and a serious failure such as a failure is occurring, and proceeds to step SP143. .

Here, the system control circuit 22 issues a warning to an external device via the interface control circuit 3. At this time, the system control circuit 22
In accordance with the error mode and the error content stored in, an abnormal point is estimated, and this abnormal point is also notified. That is, for specific addresses of the buffer memories 21A and 21B,
When a one-bit error or a two-bit error frequently occurs, it can be estimated that the buffer memories 21A and 21B are abnormal. Further, when an error occurs at regularly skipped addresses, it is considered that the address control in the memory control circuit 6 is abnormal. Thereby, the system control circuit 22
Allows maintenance work to be performed quickly and properly.

When the warning is output in this manner, the system control circuit 22 proceeds from step SP143 to step S143.
The process moves to P144, and this processing procedure ends. If the frequency of occurrence of the error is equal to or less than the specified value, the system control circuit 22
Moves from step SP142 to step SP144, and ends this processing procedure.

In the above configuration, when a write control command is input from a host computer as an external device (FIG. 2), the entire operation of the data processing device 20 is controlled by the system control circuit 22 so that the After rewinding and cueing the tape, the run-in starts, whereby a recording track is formed following the previously formed recording track.

At this time, the data D1 inputted subsequent to the control command is a predetermined data "0F0F" required for the logical format in units of 1 ID in the interface 2.
After "0F0F" is added, it is input to the buffer memory 21. At this time, the data D1 is (FIG. 3)
At A and 24B, after an error correction check bit is added, the data is alternately recorded in the buffer memories 21A and 21B. Further, buffer memories 21A and 21B
Is read out at a timing corresponding to the travel of the magnetic tape M, and then error-corrected by the EDACs 24A and 24B using check bits. Further, as for the data D1, the result of the error correction processing is output to the timing control circuit 25 as an error flag F1, and is notified to the system control circuit 22 via the timing control circuit 25.

The data D1 that has been subjected to the error correction processing in this way is added to the EDACs 24A and 24B with a parity code for error detection, and is then output to the tape controller 27 via the buffer 9, and is output to the tape controller 27. Are subjected to data processing such as cross-interleave processing and encoding processing. Furthermore, this data D
1 is converted into a modulation signal suitable for recording on the magnetic tape M in the following RF circuit, and the rotary head 13 is driven by this modulation signal to be sequentially recorded on the magnetic tape M. At this time, the data D1 is subjected to an error detection process using a parity code and a framing error detection process in the tape controller 27, and the detection result is notified to the system control circuit 22 as error information EE1.

Thus, during recording, the data D1 is sequentially recorded on the magnetic tape M in a state where errors in input / output in the buffer memories 21A and 21B and errors from the EDACs 24A and 24B to the tape controller 27 are monitored. (FIG. 1).

When a 1-bit error is detected in this monitoring (FIG. 10), 1 bit is detected in data D1.
After the ID data D1 is recorded on the magnetic tape M, it is detected whether or not the corresponding data has been correctly read from the buffer memories 21A and 21B. In this case, if a 1-bit error occurs, the correct data is detected. The data is recorded in the corresponding areas of the buffer memories 21A and 21B, and it is detected whether or not the data was correctly read.

Thus, the cause of the abnormality is self-diagnosed by the repeated reading, and the error mode is set.
It is recorded in the history memory 23 together with the error occurrence time and the like.

On the other hand, if a two-bit error occurs (FIG. 12), the magnetic tape M is rewound and data recording is retried. In this retry, data D1 for one ID is initially stored in the buffer memories 21A and 21B.
Is read out and recorded again on the magnetic tape M. At this time, it is detected whether or not the data D1 has been correctly read out from the buffer memories 21A and 21B. At this time again
When a bit error occurs, a retransmission request is issued to the host computer to re-record the data D1 on the magnetic tape M. At this time, the data D1 is correctly stored in the buffer memory 21A.
And 21B are detected.

As a result, in the case of a 2-bit error, the cause of the abnormality is self-diagnosed by retrying the recording of the data, and if it is determined that it is difficult to record the data D1 correctly, the recording process is stopped. The self-diagnosis result is recorded in the history memory 23 together with the error occurrence time and the like as an error mode.

On the other hand, when a parity error occurs (FIG. 13), when a framing error occurs (FIG. 14), retry of data recording is executed in the same manner as in the case of a 2-bit error, and error information in each retry is obtained. The cause of the abnormality is self-diagnosed according to. At this time, if it is determined that it is difficult to correctly record the data D1, the recording process is stopped, and the self-diagnosis result is recorded in the history memory 23 together with the error occurrence time and the like as an error mode.

On the other hand, the data D2 recorded on the magnetic tape M (FIG. 2) is obtained by demodulating a reproduction signal obtained from the rotary head 13 in the RF circuit 12 to generate reproduction data. The data is processed and decoded in the processing circuit 10.

The data D 2 (FIG. 3) is added with a parity code after a framing error is detected by the tape controller 27,
Output to ACs 24A and 24B. This EDAC24
In A and 24B, the data D2 is stored in the buffer memories 21A and 21B after a bit error is detected by the parity code, after which a check bit is added instead of the parity code.

Further, the data D2 is read out at a timing corresponding to the host computer, and then read out from the EDAC.
At 24A and 24B, error correction processing is performed using check bits, and the result is output to the host computer via the buffer 7. At this time, the data D2 is EDAC2
The result of the error correction processing in 4A and 24B and the result of error detection by the parity code are output to the timing control circuit 25 as error flags F1 and F2, and are notified to the system control circuit 22 via the timing control circuit 25. The detection result of the framing error is notified to the system control circuit 22 as error information EE1.

Thus, the data D2 is sequentially reproduced from the magnetic tape M and output to the host computer in a state where errors in the buffer memories 21A and 21B and errors from the tape controller 27 to the EDACs 24A and 24B are monitored. (FIG. 15).

When a 1-bit error is detected in this monitoring (FIG. 16), 1 bit is detected in data D1.
After the data D1 of the ID is output to the host computer, it is detected whether or not the corresponding data has been correctly read from the buffer memories 21A and 21B. Is recorded in the corresponding areas of the buffer memories 21A and 21B, and it is detected whether or not the data has been correctly read.

Thus, the cause of the abnormality is self-diagnosed by these repeated readings, and the error mode is set.
It is recorded in the history memory 23 together with the error occurrence time and the like.

On the other hand, when a 2-bit error occurs (FIG. 17), the data output to the external device is retried. In this retry, the buffer memory 2
Data D2 for one ID is read from 1A and 21B and output to the host computer again. At this time, it is detected whether data D2 has been correctly read from buffer memories 21A and 21B. If a two-bit error occurs again at this time, the magnetic tape M is rewound and the data D2 is re-recorded in the buffer memories 21A and 21B.
At this time, it is detected whether the data D2 has been correctly read from the buffer memories 21A and 21B.

Thus, in the case of a 2-bit error, the cause of the abnormality is self-diagnosed by retrying these data outputs, and if it is determined that it is difficult to output the data D2 correctly, the reproduction process is stopped. The self-diagnosis result is recorded in the history memory 23 together with the error occurrence time and the like as an error mode.

On the other hand, when a parity error occurs (FIG. 18), retry of data output is executed as in the case of a two-bit error, and the cause of the abnormality is self-diagnosed according to the error information in each retry. When a framing error occurs (FIG. 19), the magnetic tape M is rewound to store the data D2 in the buffer memories 21A and 21A.
B. At this time, it is detected whether the data D2 has been correctly read from the buffer memories 21A and 21B. Further, the cause of the abnormality is self-diagnosed from the detection result. In these cases, if it is determined that it is difficult to output the data D2 correctly, the data output is stopped, and the self-diagnosis result is recorded as an error mode in the history memory 23 together with the error occurrence time and the like.

When recording and reproduction of data are repeated in this manner (FIG. 20), after a certain period of time, the contents of the history memory 23 are examined by the system control circuit 22, and the frequency of error occurrence exceeds the specified value. Warning, the user is warned, and the recording / reproducing process is stopped.

According to the above configuration, the buffer memory 21
By performing error correction processing on the output data of A and 21B and retrying data recording and data output processing based on the error correction processing results, the reliability of the buffer memories 21A and 21B and peripheral circuits can be improved. . At this time, in the case of a 1-bit error or the like, after reading data from the buffer memory repeatedly, if a similar error occurs, data is input from an external device or a magnetic tape, and data recording and data output are retried. By reducing the effect on peripheral devices and peripheral circuits,
These retry processes can be executed.

The cause of the abnormality is self-diagnosed based on the result of the retry in this manner, and the data recording and data output processes are stopped based on the self-diagnosis result. Reliability can be improved. Furthermore, by recording and maintaining the history of such errors together with the self-diagnosis results, maintenance work can be performed quickly and accurately, thereby improving reliability.

In the above-described embodiment, between the buffer memory and the host computer,
Although a case where no error is detected has been described, the present invention is not limited to this, and an error may be detected similarly to the tape controller. By doing so, the reliability can be further improved.

In the above-described embodiment, the case where an error is detected by a parity code or the like has been described. However, the present invention is not limited to this, and a CRC code is added in a predetermined block unit (for example, an ID unit). An error may be detected based on the CRC code.

Further, in the above-described embodiment, the case where the data of the host computer is recorded / reproduced on / from the recording medium composed of the magnetic tape has been described. The present invention can be widely applied to a case where data is recorded or reproduced on a recording medium.

[0126]

As described above, according to the present invention, the output data of the buffer memory is subjected to error correction processing, and based on the result of the error correction processing, data recording and reproduction are performed on external equipment and a recording / reproducing system as necessary. By retrying the data output processing and the like, the reliability of the buffer memory and peripheral circuits can be improved.

[Brief description of the drawings]

FIG. 1 shows a data processing apparatus according to an embodiment of the present invention.
6 is a flowchart for explaining an overall operation during data recording.

FIG. 2 is a block diagram illustrating an overall configuration of the data processing device of FIG. 1;

FIG. 3 is a block diagram illustrating a buffer memory and peripheral circuits of the data processing device of FIG. 1;

FIG. 4 is a block diagram for explaining data writing to the buffer memory of FIG. 3 at the time of data recording;

5 is a block diagram for explaining reading of data at the time of data recording to the buffer memory of FIG. 3;

6 is a block diagram for describing writing of data to the buffer memory of FIG. 3 during data reproduction.

FIG. 7 is a block diagram for explaining reading of data from the buffer memory of FIG. 3 during data reproduction;

FIG. 8 is a block diagram showing a data flow at the time of data recording in comparison with FIG. 3;

FIG. 9 is a block diagram showing a data flow at the time of data reproduction in comparison with FIG. 3;

FIG. 10 is a flowchart showing a one-bit error process of FIG. 1;

FIG. 11 is a chart showing an error mode.

FIG. 12 is a flowchart showing a 2-bit error process of FIG. 1;

FIG. 13 is a flowchart showing a parity error process of FIG. 1;

FIG. 14 is a flowchart showing a framing error process of FIG. 1;

FIG. 15 is a flowchart for explaining an overall operation at the time of data reproduction in comparison with FIG. 1;

FIG. 16 is a flowchart showing the one-bit error process of FIG.

FIG. 17 is a flowchart showing the 2-bit error processing of FIG.

18 is a flowchart showing a parity error process of FIG.

FIG. 19 is a flowchart showing a framing error process of FIG.

FIG. 20 is a flowchart for explaining a history memory;

FIG. 21 is a block diagram showing the overall configuration of a conventional data processing device.

FIG. 22 is a block diagram illustrating a buffer memory and peripheral circuits of the data processing device of FIG. 21;

[Explanation of symbols]

1, 20 data processing device, 2 magnetic tape, 5,
5A, 5B, 21, 21A, 21B buffer memory, 4, 22 system control circuit, 6, 26 memory control circuit, 23 history memory, 24A, 24B
EDAC

Claims (6)

[Claims] 1. A data processing device for recording data input from an external device on a data recording medium or reproducing data recorded on the data recording medium and outputting the data to the external device, wherein the external device or the data An error correction code adding unit that adds an error correction code to data obtained from a recording medium; a buffer memory that temporarily stores output data of the error correction code adding unit; and an error correction process for data stored in the buffer memory. An error correction unit that records on the data recording medium or outputs to the external device and outputs an error correction processing result; anda control unit that controls an entire operation based on the error correction processing result. Means for, when an error occurs in data output from the buffer memory based on the error correction processing result, Again reads the corresponding data from Amemori, through the error correction means, recorded on the data recording medium, or the data processing device and outputting to an external device. 2. The external device or the data recording medium based on a second error correction processing result obtained by the error correction unit when the corresponding data is read again from the buffer memory. 2. The data according to claim 1, wherein after storing more corresponding data in the buffer memory, the data is recorded on the data recording medium or output to the external device via the error correction unit. 3. Processing equipment. 3. The control means records the error correction processing result and / or a second error correction processing result obtained by the error correction means when the corresponding data is read again from the buffer memory. The data processing device according to claim 1, wherein: 4. The control means performs a self-diagnosis of a failure content according to the error correction processing result and the second error correction processing result, and switches an entire operation based on the diagnosis result. The data processing device according to claim 2. 5. The control unit calculates an error occurrence frequency of the data based on an error correction processing result left in the record, and issues a warning based on the occurrence frequency. 4. The data processing device according to 3. 6. The data processing apparatus according to claim 1, wherein said data recording medium is a magnetic tape.