JPH1051278A - Flip-flop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flip-flop circuit which is able to operate at a lower current consumption and a lower voltage. SOLUTION: In the flip-flop circuit provided with a data buffer composed of transistors(TRs) 17, 18, a latch hold circuit composed of TRs 11-14, and a pull-down circuit composed of TRs 15, 16, emitters of the TRs 15, 16 in common to emitters of the TRs 17, 18 or the data buffer circuit are connected to a low level power supply 52, via a constant current source 42. In the case that a clock signal 63 fed to bases of the TRs 15, 16 is at a high level, a current from the constant current source 42 is supplied to collectors of the TRs 15, 16 to make the TRs 17, 18 stable in the OFF state. Thus, the TRs 11, 12 become nonconductive and a forcing capability is lost, and a master circuit reaches a hold state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop circuit based on a differential circuit using bipolar transistors, and more particularly, to a flip-flop circuit operating at a low voltage of about 1 volt (V) and a lower current consumption. About.

[0002]

2. Description of the Related Art Conventionally, this type of flip-flop circuit has been described in the specification attached to a patent application filed on Mar. 28, 1996 (application number, Japanese Patent Application No. 08-074093). There is something. This circuit will be described with reference to FIG.

The illustrated flip-flop circuit comprises two identical sets of circuits, a master circuit, and a slave circuit, and each circuit comprises a data buffer circuit, a latch-hold circuit, and a pull-down circuit.

The data buffer circuit of the master circuit forms a differential circuit and shapes the waveform of a data signal. The data buffer circuit includes transistors 17, 18 and a constant current source 42. In the transistors 17 and 18, the bases receive the data signals 61 and 62, respectively, and the collectors each include the resistor 3
3 and 34, respectively, and the emitters are connected to each other via a constant current source 42.
2 connected.

[0005] The latch and hold circuit of the master circuit includes transistors 11 to 14 and receives a constant current from a constant current source 41.

In the transistors 11 and 12, the base of the transistor 11 is connected to the collector of the transistor 18, and the base of the transistor 12 is connected to the collector of the transistor 17, and inputs signals. In the transistors 11 and 12, the collectors are resistors 31 and 3 respectively.
2 are connected to a high-potential power supply 51 via each of them, and the emitters are mutually connected to a low-potential power supply 52 via a constant current source 41.

In the transistors 13 and 14, the collector and the emitter of the transistor 13 are connected to the collector and the emitter of the transistor 11, respectively, and the collector and the emitter of the transistor 14 are connected to the collector and the emitter of the transistor 12, respectively. Each of the collector and base of transistor 13 is connected to the base and collector of transistor 14 respectively.

Further, in the transistors 15 and 16, the bases of the transistors 15 and 16 are commonly used as the clock signal 63.
And the collectors of the transistors 15 and 16 are connected to the collectors of the transistors 17 and 18, respectively, and the emitters are connected to the low potential power supply 52 via the constant current sources 46 and 45, respectively.

Next, the operation of the flip-flop circuit in the master circuit will be described with reference to FIG.

When the clock signal 63 applied to the bases of the transistors 15 and 16 is at a high level (Hi), the transistors 15 and 16 are turned on, and a current flows through the collector. In this state, the transistors 17, 18
Irrespective of the state of the differential data signals 61, 62 applied to the base of the transistor 17, the potentials of the collectors of the transistors 17, 18 drop to a low level (Lo). Therefore, the transistors 11 and 12 are both turned off, and lose their forcing. That is, the master circuit is in a so-called flip-flop hold state.

On the other hand, when the clock signal 63 applied to the bases of the transistors 15 and 16 is at a low level (Lo), the transistors 15 and 16 are turned off and the current of the collector becomes zero. Therefore, transistors 17 and 1
The data signals 61 and 62 whose waveforms are shaped by the data buffer circuit constituted by 8 are applied to the bases of the transistors 11 and 12. That is, the master circuit enters a so-called flip-flop latch state.

The operation of the slave circuit is the same as that of the above-described master circuit. That is, transistors 21 to
28 correspond to the transistors 11 to 18, respectively, and the resistors 35 to 38 correspond to the resistors 31 to 34, respectively. The input signal is applied to transistors 27 and 28.
Of the transistors 11 and 12 from the collectors of the transistors 11 and 12, respectively.

The difference is that transistors 25 and 26
The clock signal 64 is input to the base, and the connection destinations of the respective emitters are the constant current sources 45 and 46 opposite to the master circuit. Since the clock signals 63 and 64 operate in the relationship of the normal phase clock / negative phase clock, the master circuit and the slave circuit alternately take the latch / hold state.

In the above-described flip-flop circuit, as shown in FIG. 3, six constant current sources are required. In order for the flip-flop circuit to operate at lower voltage and lower current consumption under lower conditions, the number of constant current sources may be reduced. A technique for this is described, for example, in US Pat. No. 4,977,335.

This circuit will be described with reference to FIG.

The flip-flop circuit shown in the figure comprises two identical sets of latch and hold circuits provided in the master circuit and the slave circuit, respectively, and one set of clock buffer circuits common to the master circuit and the slave circuit.

A clock buffer circuit common to the master circuit and the slave circuit forms a differential circuit and shapes a waveform of a clock signal. The circuit is composed of transistors 17, 18 and a constant current source 42. Transistor 17,
At 18, the bases receive the clock signals 63 and 64, the collectors are connected to the high potential power supply 51 via the resistors 88 and 89, respectively, and the emitters are mutually connected to the low potential power supply 52 via the constant current source 42. doing.

The latch and hold circuit of the master circuit is composed of transistors 11 to 14 and includes constant current sources 47 and 48.
To receive a constant current.

In the transistors 11 and 12, the bases of the transistors 11 and 12 are connected to the data signals 61 and 62, respectively.
And input the signal. In addition, transistors 11, 1
In 2, the collectors are connected to the high-potential power supply 51 via the resistors 81 and 82 and further to the high-potential power supply 51 via the common resistor 83, and the emitters are connected to the low-potential power supply 52 via the constant current source 47. I have.

In the transistors 13 and 14, the collector of the transistor 13 is connected to the collector of the transistor 11, the emitter is connected to the emitter of the transistor 14, the collector of the transistor 14 is connected to the collector of the transistor 12, and the emitter is Is transistor 1
1 emitter. The transistor 13
Each of the collector and the base of the transistor 14
Are connected to the base and collector, respectively.

In the transistors 15 and 16, the base of the transistor 15 is connected to the collector of the transistor 18, and the base of the transistor 16 is connected to the transistor 17
, And the emitters of the transistors 15 and 16 are connected to a low potential power supply 52 via constant current sources 47 and 48, respectively. The collectors of the transistors 15 and 16 are directly connected to the high potential power supply 51.

Next, the operation of the flip-flop circuit in the master circuit will be described with reference to FIG.

When the clock signal 63 applied to the base of the transistor 17 is at a high level (Hi), the transistor 17 is turned on and a current flows through the collector. In this state, the potential of the collector of the transistor 17 drops to a low level (Lo). Since the clock signal 64 applied to the base of the one transistor 18 is at the opposite low level (Lo), the transistor 18 is turned off,
No current flows to the collector, and the potential of the collector of the transistor 18 rises to a high level (Hi).

When the potential of the collector of the transistor 18 is at a high level (Hi),
High level (Hi), the transistor 15 is turned on, and a collector current corresponding to the current value of the constant current source 47 flows. Therefore, the collector currents of the transistors 11 and 12 become zero irrespective of the state of the data signals 61 and 62 applied to the base. As a result, the flip-flop circuits in the master circuit are transistors 13 and 14
As a result, a so-called hold state is established.

On the other hand, when the base of the transistor 15 is at a low level (Lo), the transistor 16 is turned on, and a collector current corresponding to the current value of the constant current source 48 flows. Therefore, the collector currents of the transistors 13 and 14 become zero irrespective of the state of the data signals 61 and 62 applied to the bases.

Therefore, the transistors 11 and 12 have a forcing force, and the flip-flop circuit of the master circuit enters a so-called latch state.

Here, the reason why the transistors 15 and 16 have a more forcible force than the transistors 11 to 14 is that the resistance 8
This is because the common resistor 83 is provided between the first and second high-potential power supplies 51 and 82, and the high level (Hi) of the latch hold circuit is lower than the high level (Hi) of the clock buffer circuit.

The operation of the slave circuit is the same as that of the above-described master circuit. That is, transistors 21 to
26 correspond to the transistors 11 to 16, respectively, and the resistors 84 to 86 correspond to the resistors 81 to 83, respectively. The input signals are transistors 21 and 22
, And the constant current sources 49 and 50 correspond to the constant current sources 47 and 48, respectively.

The difference is that each of the emitters of the transistors 25 and 26 has a constant current source 50 and 4 opposite to the master circuit.
9 are connected to each other.

As a result of this circuit configuration, there are five constant current sources as shown in FIG. 4, and one is reduced from the example of FIG.

[0031]

The problem of the above-mentioned conventional flip-flop circuit is that the current consumption is large.

The reason is that the number of constant current sources is five or six.
This is a large number, and reduction of this number is desired.

An object of the present invention is to provide a flip-flop circuit which can operate with lower current consumption and lower voltage than a conventional circuit.

[0034]

SUMMARY OF THE INVENTION A flip-flop circuit according to the present invention has a data buffer for shaping a waveform of a data signal and differentially outputting the data signal, and when receiving a differential signal from the data buffer, temporarily holds the received signal. On the other hand, a latch / hold circuit for outputting a signal being held, and a pull-down circuit composed of two transistors each having a collector connected to the positive / negative-phase output of the data buffer and a base connected to each other to input a clock signal. And the emitters of two transistors forming the pull-down circuit are connected to the emitters of two transistors forming a differential pair of the data buffer.

In this configuration, the data buffer and the pull-down circuit are integrated, eliminating the forcing on the data side and sharing the constant current source.

One specific configuration is that each collector is connected to a high potential side power supply via a resistor, a differential data signal is input to each base, and the emitters are connected to the same constant current source. A data buffer forming a differential circuit with first and second transistors connected to the low potential side power supply via a resistor, each collector being connected to the high potential side power supply via a resistor, and having the same emitter as the constant current source And third and fourth transistors, and a collector and an emitter, respectively, which are connected to a low-potential-side power supply via a power supply, and connect and input the differential output of the data buffer to each of the bases, respectively. A fifth transistor having a base connected to the collector of the fourth transistor, and a collector and a collector. A latch and hold circuit comprising a sixth transistor having an emitter commonly connected to the collector and the emitter of the fourth transistor and a base connected to the collector of the third transistor, and a base connected to each other; The same clock signal is input, the emitter is connected to the mutually connected emitters of the first and second transistors, and one collector is connected to the collector of the first transistor, while the other is connected to the collector of the first transistor. A pull-down circuit including two seventh and eighth transistors connected to the collector of the second transistor.

[0037]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram showing an embodiment of the present invention. The flip-flop circuit shown in FIG. 1 includes the same two sets of circuits, a master circuit and a slave circuit, and the master circuit or the slave circuit includes a data buffer circuit, a latch-hold circuit, and a pull-down circuit.

The difference from the conventional FIG. 3 lies in the pull-down circuit.

The data buffer circuit of the master circuit is a circuit for forming a differential circuit and shaping the waveform of a data signal, as in the prior art, and includes transistors 17, 18 and a constant current source 42. In the transistors 17 and 18, the bases receive the data signals 61 and 62, respectively, and the collectors receive the high potential power supply 51 through the resistors 33 and 34, respectively.
, And the emitters are connected to each other via a constant current source 42 to a low potential power supply 52.

The latch and hold circuit of the master circuit is constituted by transistors 11 to 14 and receives a constant current from a constant current source 41 as in the conventional case.

In the transistors 11 and 12, the base of the transistor 11 is the collector of the transistor 18, the base of the transistor 12 is the base of the transistor 18,
Connect to each and input signals. In the transistors 11 and 12, the collectors are connected to the high potential power supply 51 via the resistors 31 and 32, respectively, and the emitters are connected to the low potential power supply 52 via the constant current source 41.

In the transistors 13 and 14, the collector and the emitter of the transistor 13 are connected to the collector and the emitter of the transistor 11, respectively. The collector and the emitter of the transistor 14 are connected to the collector and the emitter of the transistor 12, respectively. Each of the collector and base of transistor 13 is connected to the base and collector of transistor 14 respectively.

Next, when the transistors 15 and 16 are connected, the bases of the transistors 15 and 16 commonly receive the clock signal 63, and the collectors of the transistors 15 and 16 are connected to the collectors of the transistors 17 and 18, respectively. The points are the same as before, but the emitter is
It is connected to a low potential power supply 52 via a constant current source 42 in common with the emitters of the transistors 17 and 18 of the data buffer circuit.

Next, the operation of the flip-flop circuit in the master circuit will be described with reference to FIG.

When the clock signal 63 applied to the bases of the transistors 15 and 16 is at a low level (Lo), the transistors 15 and 16 are turned off, and the collector current becomes zero. In this state, the transistors 17 and 1
8 is in an ON state, and data signals 61 and 62 input to the bases of the transistors 17 and 18 are
The waveform is shaped by a data buffer circuit constituted by 7 and 18 and applied to the bases of the transistors 11 and 12. That is, the master circuit is in a latch state of a so-called flip-flop circuit.

On the other hand, when the clock signal 63 applied to the bases of the transistors 15 and 16 is at a high level (Hi), the transistors 15 and 16 are turned on and a current flows through the collector. Regardless of the state of the differential data signals 61 and 62 applied to the bases of the transistors 17 and 18, the potentials of the collectors of the transistors 17 and 18 decrease to low level (Lo).

Further, in this state, unlike the conventional case, the current of the constant current source 42 flows through the collectors of the transistors 15 and 16, so that the transistors 17 and 18 are stabilized in the off state. Therefore, both the transistors 11 and 12 are turned off and lose their forcing. That is, the master circuit enters a so-called flip-flop circuit hold state.

The operation of the slave circuit is the same as that of the above-described master circuit. That is, transistors 21 to
28 correspond to the transistors 11 to 18, respectively, and the resistors 35 to 38 correspond to the resistors 31 to 34, respectively. The input signal is applied to transistors 27 and 28.
And the constant current sources 43 and 44 correspond to the constant current sources 41 and 42, respectively.

The difference is that the transistors 25 and 26
The clock signal 64 is input to the base.

The clock signals 63 and 64 correspond to the positive phase clock /
It operates in the relation of the antiphase clock. Therefore, each of the master circuit and the slave circuit alternately takes a latch / hold state.

Further, as described above, when the transistor of the pull-down circuit is turned on by the clock, the current of the constant current source shared with the data buffer is supplied to forcibly turn off the transistor of the data buffer. Therefore, the hold operation of the flip-flop circuit is stabilized.

Also, as for the latch operation, since the latch-hold circuit has a positive feedback, once the output from the data buffer is inverted, the output is stabilized in that state.

Next, another embodiment different from FIG. 1 will be described with reference to FIG.

The difference from FIG. 1 is the load resistance portion of the latch and hold circuit. The resistances 31 and 32 are connected in common, and the resistance 39 is inserted between the resistance and the high potential power supply 51.
This means that the resistor 40 is inserted into the resistors 35 and 36.

In this configuration, the high level (Hi) output of the latch and hold circuit does not become the voltage value of the high potential power supply but the voltage value reduced by the voltage obtained by multiplying the commonly connected resistance value and constant current. Become.

Accordingly, the transistor of the data buffer which receives a higher voltage value than the transistor of the latch and hold circuit can have a compelling force. Therefore, the switching operation of the latch and hold circuit of the flip-flop circuit can be performed more reliably than the circuit of FIG.

The voltage drop of the common resistor according to this configuration is desirably as small as possible so that the data buffer can have a compelling force without sacrificing the power supply voltage characteristics as much as possible.

[0059]

As described above, according to the present invention, the following effects can be obtained.

The first effect is that current consumption can be reduced.

The reason is that the data buffer and the pull-down circuit can be collectively shared by one constant current source, and the number of conventional five or six can be reduced to four.

The second effect is that operation can be performed with a lower power supply voltage.

The reason is that the data buffer and the pull-down circuit are collectively shared by one constant current source, and the data buffer is provided with a forcing force, while the pull-down circuit eliminates the forcible force on the data side, so that the latch hold This is because the stability of the operation of the circuit can be ensured.

In addition, by using the common resistance to the high potential power supply of the latch and hold circuit according to the latter embodiment, the stability of the operation of the latch and hold circuit can be further secured and the current consumption can be reduced. Can be demonstrated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of the related art.

FIG. 4 is a circuit diagram showing another example different from FIG. 3 of the related art.

[Explanation of symbols]

 11-18, 21-28 Transistors 31-40 Resistance 41-44 Constant current source 51 High potential power supply 52 Low potential power supply

Claims (3)

[Claims] 1. A data buffer for shaping a waveform of a data signal and differentially outputting the data signal, and a latch / hold circuit for temporarily holding the received signal when receiving the differential signal from the data buffer and outputting the signal being held A flip-flop circuit comprising: a collector connected to a positive-phase / negative-phase output of the data buffer, a base connected to each other, and two transistors inputting a clock signal. Wherein the emitters of the two transistors constituting the flip-flop circuit are connected to the emitters of two transistors forming a differential pair of the data buffer. 2. A semiconductor device comprising: a collector connected to a high potential power supply via a resistor; a differential data signal input to each base; and an emitter connected to a low potential power supply via the same constant current source. A data buffer forming a differential circuit by the first and second transistors, and a collector connected to a high-potential power supply via a resistor, and an emitter connected to a low-potential power supply via the same constant current source. ,
And third and fourth transistors for connecting and inputting the differential output of the data buffer to the respective bases, collectors and emitters are commonly connected to the respective collectors and emitters of the third transistor, and the base is connected to the fourth transistor. Fifth connected to the collector of the transistor
And a latch-hold circuit comprising a sixth transistor having a collector and an emitter commonly connected to the collector and the emitter of the fourth transistor, respectively, and a base connected to the collector of the third transistor. , The bases are connected to each other to input the same clock signal, the emitters are connected to the mutually connected emitters of the first and second transistors, and one collector is connected to the collector of the first transistor. On the other hand, two seventh transistors connecting the other collector to the collector of the second transistor
And a pull-down circuit including an eighth transistor. 3. The latch and hold circuit according to claim 2, further comprising a resistor having one end commonly connected to a high potential side of the two resistors and the other end connected to a high potential side power supply. A flip-flop circuit.