JPH1050840A - Etching process for vertical side wall nitride - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an undesired short circuit. SOLUTION: An integrated circuit treating sequence is carried out as follows. An electrically conductive structure 66, together with a silicon nitride upper layer 68 and a silicon dioxide side wall, is formed on a semiconductor substrate. A silicon nitride insulating layer 70 is deposited on the whole substrate and on the side wall and top part of the electrically conductive structure. The silicon nitride layer is etched via the silicon nitride 70 to form an opening to the surface of the semiconductor substrate 56 without rounding the shoulder of the silicon nitride 70 covering the side wall of the electrically conductive structure 66. The shoulder increases the margin for the subsequent etching treatment because the shoulder is left in a relatively rectangular shape. Subsequently deposited conductor is in contact with the surface of the semiconductor substrate 56 without making a short circuit to the electrically conductive structure 66 on the semiconductor substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0002] This application is filed with application no. 60/017, 065 (TI-23
269). The present invention relates to a process for manufacturing an integrated circuit semiconductor device, and more particularly, to a process for etching a semiconductor device structure.

[0002]

BACKGROUND OF THE INVENTION In the manufacturing process for forming a 64 megabit DRAM device, an etching process of the sidewall nitride is silicon nitride which covers the conductive strip, such as a word line, Si ₃ N _4, a dielectric material layer on the Produces a round shoulder. The dielectric material is disposed there to provide sufficient electrical isolation to maintain isolation between the word lines and other conductive materials, such as bit line contacts and storage node contacts. Due to the rounded shoulders of the silicon nitride, the shortest distance from the word line corner to the bit line contact or storage node contact is a minimum to maintain the desired electrical isolation of the two conductors. .

[0003]

However, the manufacturing process
Process, for example, etching of storage node contacts
Continue the process. Silicon nitride round shoulder shape
For oxide / nitride (nitride) selectivity
Such a storage node contact etch
Reduced at the shoulder. As a result,
The thickness of the gate is reduced below the desired minimum,
Short circuit between word line and bit line contacts
Or may occur between storage node contacts
No. Current literature etches silicon nitride
There are several chemical actions to make. Inactive
In the mixture, carbon fluoride (carbon fluoride) CF _Four,
Sulfur fluoride (sulfur fluoride) SF₆Or na
Use any of itras fluoride (nitrogen fluoride)
Characteristics and properties of etching recon nitride
The quality is stated. The information provided will determine the etch speed and selection.
Including selectivity. Regarding the profile of sidewall silicon nitride
There is no information detailing the effect of the etching. But
However, this contour is useful for self-aligned storage node
Contact etch or bit line contact etch
It is very important in developing.

[0004]

These problems are solved by a novel integrated circuit processing sequence that includes the following steps. A conductive structure having sidewalls and an upper layer of silicon nitride is formed on a semiconductor substrate. During this fabrication, an insulating layer of silicon nitride is deposited on the entire structure, including the sidewalls and top of the conductive structure. The silicon nitride layer is etched to form an opening through the silicon nitride to the surface of the semiconductor substrate without substantially rounding the shoulder of the silicon nitride covering the sidewalls of the conductive structure. The following effects are understood by the novel processing sequence.
A single photomask operation accomplishes etching of the self-aligned silicon nitride layer without substantially rounding the shoulders of the sidewalls isolating the conductive regions. At least one photomask operation, including several processing steps, is eliminated from the conventional processing sequence used to create a similar non-rounded shoulder of the sidewall insulator.

[0005]

Referring to FIG. 1, there is shown a cross section of a semiconductor integrated circuit device 50 partially formed.
The n-type deep well 52 is implanted into the semiconductor substrate according to the arrangement of the memory array to be manufactured. A p-type well 54 is also implanted into the substrate according to the memory array. Further, there is a boron-phosphorus (BP) region 56 formed between the p-type well 54 and the surface 57 of the semiconductor substrate. Other doped regions can be implanted in the substrate to form the desired electrical circuit device. Surface 57 of semiconductor substrate 52
Can include ion implanted regions used as contacts for other interconnect elements of the integrated circuit. On the surface of the substrate, a thin layer of insulating material 62, such as silicon dioxide or silicon nitride, is deposited. Relatively thick regions 63 of insulating material, for example silicon dioxide, are formed like the regions referred to as LOCOS.

On the thin layer 62 and the thick region 63, further elements of the integrated circuit are formed. There are several stacks of conductors 66 that are used for transistor gate structures and other conductive paths or strips. An insulating layer of silicon nitride 68 is disposed on top of each conductor stack. A thin insulating layer 69 of silicon dioxide is placed on the stack of conductors 66 or on the sidewalls of the conductive strips. As shown in FIG. 2, silicon nitride 7 as an insulating material layer
Zero is deposited on the entire device 50. FIG. 3 shows that the silicon nitride layer 70 has been entirely etched back so that bit line contact holes or storage node contact holes eventually form channels 72 connecting another conductor to the surface of the semiconductor substrate. A later cross section is shown. This channel 72 is
6 and etched through the silicon nitride layer at the location between the two stacks. New etching techniques are used for this part of the processing sequence. This etching is a dry etch of silicon nitride and is performed in two separate steps in the LAM model 4400 etcher.

This two step, the silicon nitride etch process, achieves the desired square shoulder or vertical sidewall profile of silicon nitride around the conductor strip. In the first step, chlorine (chlorine) Cl ₂ , sulfur fluoride (sulfur fluoride) SF ₆ , freon 23, CHF ₃ and helium H
e is used to provide an anisotropic etch to achieve a silicon nitride profile with square shoulders or vertical sidewalls. The sidewall silicon nitride etching process uses both physical and chemical etching. The etching mechanism used was ion bombardment and polymerization from Freon 23, CHF ₃ and Cl ₂ .
(polymerization). The combination of these two mechanisms can perform an anisotropic etch of silicon nitride. Silicon nitride is preferentially removed vertically, leaving a square shoulder profile.

The conditions for the first step of etching through silicon nitride are as follows.

TABLE 1 Pressure 255 +/- 20% m torr gap 1.3 +/- 10% cm power 205 +/- 20% watts _{Cl 2 25 +/- 20% sccm SF} 6 155 +/- 20% sccm He _{64 +/- 20% sccm CHF 3 11} +/- 20% sccm time endpoint +/- 30% sec

[0009] The base electrode is maintained at about 20 ° C. As a result of the first step, a substantial portion of the final layer of silicon nitride is removed from the top of the stack of conductors and from the bottom of channel 72 to the surface of moat region 56. Since this is an anisotropic etch, the silicon nitride on the sidewalls is etched on a vertically oriented surface. A polymer forms on the surface of the silicon nitride, which delays the removal of the silicon nitride at the shoulder, leaving a relatively square shoulder. The remainder of the silicon nitride may remain at the bottom of the moat area. As an alternative etching mixture of the above, argon Ar can be used instead of helium He. Argon is 80 +/- 20
% Sccm will replace helium. Otherwise, the etching conditions are as described above. A mixture of Freon 23, CHF ₃ , and helium He is used in the second etching step, the result of the first step maintaining the square shoulder or vertical profile of the sidewall silicon nitride, while silicon nitride by topography. To remove the residue. This step occurs with minimal physical action to prevent holes from being formed in the moat area.

The conditions for the second step of etching through silicon nitride are as follows.

TABLE 2 Pressure 200 +/- 20% m torr gap 1.5 +/- 10% cm power 130 +/- 20% watts _{Cl 2 0 +/- 20% sccm SF} 6 0 +/- 20% sccm He _{130 +/- 20% sccm CHF 3 45} +/- 20% sccm time endpoint +/- 30% sec

The base electrode is maintained at about 20 degrees C. As a result of the second step, the contact channel 72
Is etched through the remaining silicon nitride to the surface 57 of the semiconductor substrate. Again, a polymer forms, protecting the square shoulder of the sidewall silicon nitride. Here, it should be noted that helium He is an inert gas. Other inert gases, such as argon Ar
Something like or nitrogen N ₂ can be replaced by helium. Argon will be replaced by helium in an amount of 130 +/− 20% sccm. otherwise,
The etching conditions should be as described above for the second step. FIG. 3 shows the contour of the channel 72 in cross section of the device 50 after the above-described sidewall silicon nitride etching step. Channel 72 provides space for connecting source / drain regions to a bit line node or storage node to be subsequently formed, as described below.

Referring to FIG. 4, there is shown a state in which an insulating material layer 80, for example, silicon dioxide or silicon oxide SiOx, is deposited on the entire surface of the integrated circuit device 50. This process step involves low pressure chemical vapor deposition (LP
By CVD, TEOS, ie, tetraethyl orthosilicate, Si (O
C ₂ H ₅ ) ₄ . As shown in FIG. 5, after the TEOS has been deposited, the entire device 50 is covered by boron-phosphorus-silicon glass (BPSG) 82 to form a horizontal surface 84. This is an insulating material.

FIG. 6 shows that a hard mask material 86 of polysilicon has been deposited on top of the BPSG 82. A photoresist 88 is deposited and this is patterned to form contact channels down to the substrate surface 57 through the hard mask 86, BPSG material 82 and silicon oxide (SiOx) material 80. Channels are positioned to provide storage node contacts or other desired conductors. These exemplary contact channels are to be created between stacks of conductors 66 forming gate electrodes or other conductive lines. FIG.
Shows a cross-section of the device 50 after the polysilicon hardmask material 86 has been etched away in the areas left exposed by the photoresist material 88. This dry etch operation is started through the polysilicon hard mask and stopped at the surface of the BPSG 82. As shown in FIG. 8, the photoresist material is removed and the BP
The patterned hard mask material 86 is left on the surface of the SG material 82. The opening through the hard mask,
Patterned to form a channel at the bottom of device 50 with a standard cross section.

FIG. 9 shows an integrated circuit structure 5 in which oxide etching is performed to the surface of a semiconductor substrate through BPSG and TEOS.
0 shows a cross section. This oxide etch is an anisotropic dry etch that removes the BPSG leaving behind vertical walls 90, and removes the silicon oxide deposited from TEOS to remove the underlying silicon nitride. The vertical wall 92 is left. The silicon oxide deposited from TEOS is selectively etched from the underlying silicon nitride 70, maintaining a relatively square shoulder on the silicon nitride sidewall 70. As a result, the thickness of the silicon nitride sidewalls 70 and top 68 covering the stacked conductor layer 66 is the desired insulation to prevent shorts between the stacks of conductive material 66 from the contact plugs to be formed in the channel 96. I will provide a.
This oxide etch is achieved in two etching steps.

The conditions for the first step of this oxide etch are as follows.

TABLE 3 Pressure 100 +/- 20% m torr gap 11 +/- 10% cm power 0 +/- 20% w CO 0 +/- 20% sccm Ar 600 +/- 20% sccm C 4 F 8 2 _{+/- 20% sccm CF 4 5 +/-} 20% sccm rear pressure (center) 20 torr (end) 7.5 torr

The base electrode is maintained at about 20 degrees C. As a result of this first step, a substantial portion of the silicon oxide is removed for the storage node contact hole. The conditions for the second step etching through the oxide are as follows.

Table 4 Pressure 100 +/- 20% m torr gap 11 +/- 10% cm power 1500 +/- 20% w CO 150 +/- 20% sccm Ar 600 +/- 20% sccm C 4 F 8 2 _{+/- 20% sccm CF 4 5 +/-} 20% sccm rear pressure (center) 20 torr (end) 7.5 torr

The base electrode is held at about 20 degrees C. As a result of the second step, the storage node contact hole is etched down to the surface of the semiconductor substrate. Any silicon oxide residues are removed. It should be noted here that argon is an inert gas and therefore helium or nitrogen is replaced by it. afterwards,
As shown in FIG. 10, polysilicon 100 is deposited on the entire top of the semiconductor structure, completely filling channel 96 to form a storage node contact plug to be subsequently formed. The surface of the polysilicon 100
Finish as a relatively flat surface. Please refer to FIG. FIG. 2 shows a cross section of the integrated circuit structure 50 after polysilicon is etched back. This etching is
The part of the polysilicon layer 100 and the layer 86 shown in FIG. 10 are removed. Here, in FIG.
Should remain in the storage node plug contact region 96 to be subsequently formed in the plug. The etching of the polysilicon is stopped by the BPSG material 82.

FIG. 12 shows a cross section of integrated circuit device 50 after the deposition of oxide 104 on BPSG material 82 and remaining polysilicon 102. Oxide deposition 1
Since both 04 and the BPSG material are oxides, these layers are hereafter treated as one layer in both the figures and the description that follows. One such layer is BPSG
Quoted as material layer 82. FIG. 13 shows a cross section of the device 50 after the polysilicon layer 106 has been deposited on the BPSG material layer 82. FIG. 14 shows polysilicon 1
Shown is a photoresist mask 110 deposited on 06 and patterned to open holes for bit line contact with surface 57 of substrate 52. Referring to FIG. 15, the mask 110 is made of B
This is used in a step of performing polysilicon dry etching up to the surface of the PSG material 82 via the polysilicon layer 106.

FIG. 16 shows a cross section of the integrated circuit device 50 with the removal of the photoresist mask 110 of FIG. Thus, the hard mask of the polysilicon 106 is left in the integrated circuit device 50. The hole through the hard mask creates a pattern for etching the hole where the next bit line contact is to be formed.

FIG. 17 shows a cross section of the device 50 after the anisotropic silicon oxide dry etching step has been performed.
The silicon oxide 82 is etched away down to the surface 57 of the semiconductor substrate 52 so that the bit lines are connected to the substrate. When the resulting bit line contact hole 112 is opened, a bit line can be formed. Here, it should be noted that the silicon nitride sidewall of the bit line contact hole 112 is maintained at a substantially square shoulder. Therefore, the silicon nitride 70 is made of the conductive material 6
Maintain a desired thickness that provides sufficient insulation to prevent short circuits between 6 and the bit line to be formed. This silicon oxide dry etch is similar to the two steps described with respect to the process of FIG. Referring to FIG. 18, the cross section of the integrated circuit device 50 is a hard mask 10
6 including two additional layers of material placed on the surface. First, a polysilicon layer 114 is deposited entirely.
In particular, the polysilicon layer 114 is deposited at the bottom of the bit line contact hole 112 that contacts the surface 57 of the semiconductor substrate 52. On the surface of the polysilicon layer 114 is a tungsten silicide layer 116 that is entirely deposited. The tungsten silicide layer 116
The polysilicon is deposited on the polysilicon up to the lower portion in the bit line contact hole.

FIG. 19 shows the tungsten silicide layer 11.
6 and tungsten silicide 1
Shown is a photoresist 120 that has been patterned to form a bit line structure that includes 16 and two polysilicon layers 114,106. The resulting bit lines connect to the source / drain regions at the surface 57 of the substrate. Referring to FIG. 20, a cross section of an apparatus 50 with dry etching of tungsten and polysilicon is shown. Tungsten silicide layer 116, polysilicon 1
Only the 14 and polysilicon hard mask 106 are etched away, leaving the bit line structure under the photoresist 120.

As shown in FIG. 21 after the bit lines have been formed, the next step is to remove the photoresist 120 of FIG. 20 from the surface of the bit line structure. FIG. 22 shows the result after the next two processing steps. In two steps, insulating material is deposited on the entire upper surface. In a first step, a silicon oxide layer 122 about 1000 Å thick is deposited from TEOS over the entire surface of device 50. Next, a silicon nitride layer 124 having a thickness of about 250 Å is provided.
Deposited on the surface of silicon oxide layer 122.
These two material layers together form an insulating material covering the entire bit line structure. FIG. 23 shows the result after another 5000 Angstrom thick silicon oxide 126 has been deposited over the entire device 50. The device is then annealed at about 850 ° C. for about 20 minutes. The silicon oxide layer 126 is etched back,
Leave a layer of about 500 Å on a relatively flat surface. A silicon oxide layer 128 is then deposited from TEOS to a total thickness of about 500 Angstroms.

Thereafter, a polysilicon layer 130 is deposited over the entire device 50 to a thickness of about 2000 angstroms, as shown in FIG. As shown in FIG. 25, a photoresist mask 132 is deposited, and openings 134 for storage capacitor contacts to storage node contacts 102 are formed.
FIG. 26 shows a cross section of a device 50 with a polysilicon dry etch opening a hole 136 through a polysilicon layer 130 for processing and forming a storage capacitor contact that contacts the next storage node contact 102. I have. Referring to FIG. 27, there is shown a cross section of the device 50 after the photoresist mask 132 of FIG. 26 has been removed. The polysilicon layer maintains a hard mask configuration with openings or holes 136 for forming holes through oxide to connect the storage capacitors to storage node plugs 102 below.

FIG. 28 shows a cross section of the device 50 with a dry etch of silicon dioxide. This etch creates a hole 138 below the hole in the hard mask 130 that is all the way to the upper surface of the storage node plug 102.
This etch is similar to the two-stage etch described with respect to the process of FIG. FIG. 29 shows a polysilicon layer 140 deposited to a thickness of about 700 angstroms on the entire top of the device 50 of FIG. Referring to FIG. 30, a silicon oxide layer 142
Has been deposited from TEOS to a thickness of about 5000 Angstroms.

A photoresist mask 144 is deposited, as shown in FIG.
42 are formed at the top. FIG. 32 shows a cross section of the device 50 with a dry etch of the silicon oxide layer 142 leaving the photoresist material 144 on top of the silicon oxide mesa 150. Referring to FIG. 33, this cross section shows the device 50 after the photoresist mask has been removed from the top of the silicon oxide mesa 150. As shown in FIG. 34, a conductive polysilicon layer 152 is deposited on the entire top surface of the device 50 of FIG. Thus,
The polysilicon layer covers the sidewalls and top of mesa 150.
Between mesa 150 and the other region, polysilicon 152 contacts polysilicon layer 140 connected to storage node contact plug 102.

FIG. 35 is a partial cross-sectional view of FIG. 34 with etchback of polysilicon layer 152. FIG. Note that the polysilicon is etched away from the top of the mesas 150 as well as from the horizontal plane between the mesas. The etchback process leaves a polysilicon sidewall coverage on each of the mesas 150. These polysilicon sidewalls 152 are connected to storage node contact plugs 102 via polysilicon layer 140. Referring to FIG. 36, this cross section is shown in FIG. 35 after the silicon oxide etch.
Part is shown. This etch removes all the silicon oxide in the mesa 150, all the silicon oxide below in the depression surrounded by the polysilicon layer 140 and the polysilicon 1
Remove any silicon oxide between the 52 sidewalls. When the silicon oxide is removed, the remaining polysilicon 1
40, 152 form a conductive storage node having a cross-section shaped like the cross-section of a torch.

FIG. 37 shows a partial cross section of FIG. 36 with a deposit of an insulating layer 154 made of silicon nitride. After the silicon nitride layer 154 has been deposited, the device 50 is subjected to an oxidation process to form a silicon oxide 156 on top of the silicon nitride layer 154. As shown in FIG. 38, the partial cross section of FIG. 37 has a conductive polysilicon layer 160 deposited on the entire top. At this point in the sequence of process steps, there is a conductive polysilicon layer 160 separated from the conductive storage node polysilicon 140, 152 by an insulating layer of silicon nitride 154 and silicon oxide 156. Then, the polysilicon layer 1
60 is formed on the field plate.

The advantage is that the above-described processing steps can
Bit line structures 106, 114, 116 connected to
Has been completed. The bit line structure is separated from the conductive word line structure 66 by insulating silicon nitride sidewalls 70. Storage capacitor structures 102, 140, 152, 154, 156, 1
The formation of 60 has also been completed, with conductive contact plugs 102 connected to substrate surface 57. The bit line layer 114 and the storage node contact plug 102
All are separated from the conductive word line structures 66 by sidewall silicon nitride layers 70. Sidewall silicon nitride 70 has a thickness and a relatively square top corner sufficient to effectively isolate the bit line and storage node contact plug from the word line structure without undesired shorts during operation. ing.

The process of manufacturing a complete integrated circuit memory device continues from the last mentioned step. The above described process produces very good results in the integrated circuit device being manufactured. Also, alternative exemplary manufacturing sequences can be used to create the desired integrated circuit device. An alternative exemplary sequence can be viewed as a manufacturing sequence for making storage node contacts in a single step. That is, a single mask, etch, and conductor deposit for the storage node contact. This alternative sequence is described directly below.

The first steps of the process are performed in a manner similar to the steps disclosed above in FIGS. The advantages of silicon nitride etch, which leaves a square shoulder and vertical sidewalls in silicon nitride, are included in these first steps. This process continues after the step of FIG. Referring to FIG. 39, there is shown a cross section of the device 50 after a thin polysilicon layer 86 has been placed over the oxide 82. FIG. Then, the photoresist layer 200
A photomask is formed to etch holes for bit line contacts. FIG. 40 shows a cross section of a semiconductor device in which a pattern determined by the photoresist 200 is etched through the polysilicon 86. This etch forms a polysilicon hard mask 86 located over the oxide layer 82.

FIG. 41 shows a cross section of the integrated circuit formed after the photoresist mask is removed. Hard mask 86 is left and patterned to form the desired bit line contacts. Although a mask opening for one bit line contact is shown, it is clear that many other bit line contact openings, not shown, may be formed in other parts of the device. Referring to FIG. 42, the upper surface 5 of the semiconductor substrate
A cross section of a device 50 fabricated with bit line contacts self-aligned oxide etched through BPSG and TEOS up to 7 is shown. This oxide etch is an anisotropic dry etch that removes the BPSG leaving a vertical wall 90, and removes the silicon oxide deposited from TEOS to remove the vertical silicon nitride underneath. Leave wall 92. Silicon oxide deposited from TEOS is selectively etched from the underlying silicon nitride 70 to maintain a relatively square shoulder on the sidewall of silicon nitride 70. As a result, the thickness of the silicon nitride sidewall 70 and top 68 over the stacked conductive layer 66 provides the desired insulation to prevent a short circuit between the stack 66 of conductive material from the bit line contact to be formed. This oxide etching is accomplished in two etching steps.

The conditions for the first step of the oxide etch are as follows.

TABLE 5 Pressure 100 +/- 20% m torr gap 11 +/- 10% cm power 0 +/- 20% w CO 150 +/- 20% sccm Ar 600 +/- 20% sccm C 4 F 8 2 _{+/- 20% sccm CF 4 5 +/-} 20% sccm rear pressure (center) 20 torr (end) 7.5 torr

The base electrode is maintained at about 20 degrees C. As a result of the first step, a substantial portion of the silicon oxide is removed for bit line contact holes. The conditions for the second step of etching through the oxide are as follows.

[Table 6] Pressure 100 +/- 20% m torr gap 11 +/- 10% cm power 1500 +/- 20% w CO 150 +/- 20% sccm Ar 600 +/- 20% sccm C 4 F 8 2 _{+/- 20% sccm CF 4 5 +/-} 20% sccm rear pressure (center) 20 torr (end) 7.5 torr

The base electrode is maintained at about 20 degrees C. As a result of the second step, the contact holes are etched down to the upper surface of the semiconductor substrate. Any silicon oxide residue is removed. It should be noted here that argon is an inert gas and therefore helium or nitrogen is replaced by it. Such an etch may include regions of oxide layer 82 and portions of oxide layer 80,
That is, the process is continued to etch away the region of the hard mask 86 exposed by the bit line contact opening. It should be noted here that layers 80 and 82 are etched down at right angles to expose the upper surface of the silicon substrate. Thus, the bit line contact to be formed can be directly connected to the upper surface of the silicon substrate. An important advantage of the square sidewall nitride provides a great deal for the bit line contact etch, as is evident in FIG.
With these square shoulders, the silicon nitride 70
The desired minimum thickness ensures that the conductive layer 66 is desirably electrically isolated from the conductive bit line contacts to be formed in the bit line contact holes.

In FIG. 43, the hard mask material 8 of FIG.
A cross section of the device 50 is shown after 6 has been removed. Thereafter, as shown in FIG. 44, a 700 Å polysilicon layer 202 is disposed on the oxide and also in a bit line contact hole that forms an electrical connection with the upper surface of the substrate. Then 800
Angstroms tungsten silicide 204
Deposited on the entire upper surface of polysilicon layer 202. This tungsten silicide layer also fills a part of the bit line contact hole. As shown in FIG. 45, a photoresist material layer 208 is deposited on top of the tungsten silicide 204 and is formed in a mask to open a storage node contact hole. Thereafter, as shown in FIG. 46, the exposed polysilicon layer 2 is exposed.
02 and portions of the tungsten silicide layer 204 are etched away, which is where the storage node contacts should be formed. Upon completion of the etching process, the photoresist mask material 208 is removed.

FIG. 47 shows a cross section of the device 50 after the two layers of insulating material have been fully deposited. First, 10
An oxide layer 212 deposited entirely from 00 Å of TEOS is formed. Next, a 250 Å silicon nitride layer 214 is deposited on top of the oxide layer 212. Thereafter, as shown in FIG. 48, two additional insulating layers are deposited entirely. The first insulating layer is 5000 angstrom BP
SG deposit layer 216. Another insulating layer 21
8 is deposited on top of the BPSG deposit layer. Insulating layer 218 can be an HLD deposit 218 from TEOS. FIG. 49 shows a cross section of an apparatus 50 having a photoresist layer 220 formed on a photomask to open a storage node contact hole through an insulating layer to the upper surface of the silicon substrate. The silicon oxide etch is performed in two steps.

The conditions for the first step of this oxide etch are as follows.

Table 7 Pressure 100 +/- 20% m torr gap 11 +/- 10% cm power 0 +/- 20% w CO 150 +/- 20% sccm Ar 600 +/- 20% sccm C 4 F 8 2 _{+/- 20% sccm CF 4 5 +/-} 20% sccm rear pressure (center) 20 torr (end) 7.5 torr

The base electrode is maintained at about 20 degrees C. As a result of the first step, a substantial portion of the oxide is removed from the storage node contact hole. The conditions for the second step of etching through the oxide are as follows.

Table 8 Pressure 100 +/- 20% m torr gap 11 +/- 10% cm power 1500 +/- 20% w CO 150 +/- 20% sccm Ar 600 +/- 20% sccm C 4 F 8 2 _{+/- 20% sccm CF 4 5 +/-} 20% sccm rear pressure (center) 20 torr (end) 7.5 torr

The base electrode is maintained at about 20 degrees C. As a result of the second step, the storage node contact hole is etched down to the substrate surface. Here, it should be noted that argon is an inert gas and helium or nitrogen can replace it. Referring to FIG. 50, there is shown a cross-section of the integrated circuit device of FIG. 49 after self-aligned anisotropic etching of the storage node contact hole through several oxide layers to the upper surface of the silicon substrate material. I have. The oxide etch for this storage node contact is accomplished in one mask step. Subsequently, a contact material is deposited to form a direct contact with the semiconductor substrate material. Here, it should be noted that the oxide etch preserves the insulation 70 on the silicon nitride sidewall adjacent to the conductive layer 66. The silicon nitride sidewall insulation 70 retains their square shoulders and the desired insulation thickness.

FIG. 51 shows a cross section of the device in which the polysilicon layer 222 has been deposited over the entire surface after the self-aligned etching step shown in FIG. Polysilicon layer 222
Is formed, a thick silicon oxide layer 226 is deposited entirely. Depositing silicon oxide 226 covers the entire surface of polysilicon layer 222 and includes filling the remainder of the storage node contact hole. FIG. 52 shows a cross section of the device of FIG. 51 after a layer of photoresist material has been deposited and patterned to form conductors in the storage plate portions for the storage cell capacitors. FIG. 53 shows the silicon oxide layer 2
Anisotropic etch 26 and photoresist mask 2 of FIG.
53 shows a cross section of the apparatus of FIG. 52 with the removal of 28.

Referring to FIG. 54, polysilicon layer 23
Zero is deposited on the entire top of the device of FIG. Here, the polysilicon 230 is a silicon oxide mesa 226
Note that it covers the tops of the mesas and their mesa sidewalls. Polysilicon 230 contacts polysilicon layer 222 forming a storage node contact. FIG. 55 shows the device of FIG. 54 after anisotropic etching of the polysilicon layer 230 of FIG. In FIG. 55, the mesa 226
The polysilicon 230 located on the side wall of the polysilicon 230 remains in its place, while the horizontal portion of the polysilicon 230 has been etched away. Here, the sidewall polysilicon 230 is
Polysilicon layer 222 forming storage node contact
It should be noted that direct contact is maintained. The sidewall polysilicon 230 forms a major portion of the storage plate of the storage cell capacitor being formed.

Referring to FIG. 56, there is shown a cross section of the semiconductor device of FIG. 55 after the oxide 226 has been etched away. The remaining portions of the conductive polysilicon layers 230 and 222 are shaped to form a storage node plate having a torch-shaped cross section. Fig. 57
56 shows a cross section of the semiconductor device of FIG. 56 with deposits of an oxide insulating layer 234, an insulating layer 236, and a polysilicon conductive layer 240. Polysilicon layer 240 forms the field plate of the cell storage capacitor for the array of semiconductor devices 50. Referring to FIG. 58, the aforementioned 2
A cross section of a structure having advantages formed by two integrated circuit manufacturing processes is shown. The semiconductor substrate 300 has a thin insulating material layer 3 covering most of the upper main surface of the substrate 300.
04, for example, having silicon oxide. Conductive substance 31
0, 312, 314, 316 are made on the insulating material layer 304. The conductive materials 310 and 314 can be polysilicon. The conductive materials 312 and 316 are different and can be more conductive materials, for example, tungsten silicide. When these conductive materials are patterned, they are typically left in relatively sharp, approximately right-angled corners where the sidewall meets the top surface.

The coating of the silicon nitrides 320 and 322 is made of two conductive materials 310, 312, 314 and 316.
Cover each of the divided regions. Here, after the holes for the conductive contacts are etched between the two sidewalls 326 and 328, the silicon nitride 320,
It should be noted that the side walls 326, 328 of 322 are substantially vertical. Silicon nitride 3
Upper surfaces 332, 334 of 20, 322 are substantially flat surfaces. Therefore, the upper surface 33 of the silicon nitride
The intersection of each of the side walls 326, 328 with 2, 334 forms a relatively square shoulder. These shoulders provide sufficient insulating silicon nitride 320, 322 between conductive regions 310, 312 and 314, 316 and conductive contact material 340 that is subsequently used to fill the etched contact holes. Guaranteed to remain.

The dimensions of the contacts can be made very small with this structure. For example, the top of the contact material can be as narrow as about 0.3 MM. The bottom of the contact material that contacts the surface of the semiconductor substrate 200 may be as narrow as about 0.2 MM. Figure 59
Shows a cross section of an integrated circuit device formed according to a conventional process sequence. The semiconductor substrate 400 is a substrate 400
Thin silicon nitride layer 404 located on the surface of
Having. Conductive substances 410, 412, 414, 416
Is formed on the insulating material 404. Conductive materials have a relatively square shoulder formed by their sidewalls and upper surface.

A coating of silicon nitride 420, 422 covers each of the conductive material isolation regions. Due to the geometry of the silicon nitride prior to etching the contact holes, and because the etching process does not have the correct combination of process conditions and etch chemistry that can produce a true anisotropic etch, The shoulder formed by the side walls and the top is fairly rounded. Silicon nitride 420, 4
Since the rounding and etching techniques of 22 are so bad, little material is left to insulate the conductive materials 412, 416 from the contacts 440. The selectivity of the subsequent oxide etch is reduced due to the rounded shoulder. Insufficient insulation to prevent short circuits after oxide etch and conductive contact material deposition. An important advantage of the new sidewall etch process is that it allows for a storage node contact etch in one mask step. The above describes a novel manufacturing method and structure manufactured using the new method. These methods and structures, along with others made in obvious respect, are deemed to be within the scope of the following claims.

With respect to the above description, the following items are further disclosed. (1) A method for manufacturing an integrated circuit device, comprising:
(A) forming a conductive structure having an upper layer of silicon nitride and a silicon dioxide sidewall on a semiconductor substrate;
(B) depositing an insulating layer of silicon nitride on the entire substrate and on the sidewalls and top of the conductive structure, and (c) substantially rounding the shoulder of the silicon nitride covering the sidewalls of the conductive structure. A method of manufacturing an integrated circuit device, the method including etching the silicon nitride layer to form an opening to the surface of the semiconductor substrate through the silicon nitride. (2) The etching step includes Cl ₂ , SF ₆ and CH
2. The method according to claim 1, wherein a silicon nitride dry etch containing F ₃ and He is used.

(3) The etching step comprises forming a polymer on the surface of the silicon nitride, thereby reducing the etching rate at the shoulder of the silicon nitride covering the sidewalls of the conductive structure. The manufacturing method as described. (4) The silicon nitride etching process includes: 255 +/− 20% millitorr pressure, 1.3 +/− 10% cm gap, 205 +/− 20% watt power, 25 +/− 20% sccm Cl ₂ , using a primary dry etching containing CHF ₃ 155 +/- of _{20% sccm SF 6, 64 +/-} 20% sccm of He, and 11 +/- 20% sccm, the method according to paragraph 2.

(5) The silicon nitride etching process includes: 200 +/− 20% millitorr pressure, 1.5 +/− 10% gap, 130 +/− 20% watt power, 130 +/− 20% sccm 5. The method according to claim 4, wherein an overetch containing He and 45 +/− 20% sccm of CHF ₃ is used. 6. The method of claim 5, wherein the etching step forms a polymer on the surface of the silicon nitride, thereby reducing the etch rate at the shoulder of the silicon nitride covering the sidewalls of the conductive structure. Method.

(7) The method according to item 6, further comprising: (d) depositing a silicon dioxide layer on the exposed surface of the silicon nitride and the semiconductor substrate;
Depositing boron-phosphorus-silicon glass over the entire surface to create a flat surface, (f) forming a mask for the contact, and (g) forming the boron-phosphorus-silicon glass.
A manufacturing method comprising the steps of: etching to the surface of a semiconductor substrate through a glass and silicon dioxide layer; and (h) depositing a conductor entirely to connect to the surface of the semiconductor substrate. (8) The etching step is performed by using Cl ₂ , SF ₆ and CH
A silicon nitride dry etching containing the F ₃ and Ar, A process according to paragraph 1. 9. The method of claim 8, wherein the etching step forms a polymer on the surface of the silicon nitride, thereby reducing the etch rate at the shoulder of the silicon nitride covering the sidewalls of the conductive structure. Method.

(10) The silicon nitride etching process includes: a pressure of 255 +/− 20% mTorr, a gap of 1.3 +/− 10% cm, a power of 205 +/− 20% watt, and a 25 +/− 20% sccm. 9. The method of claim 8 using a main dry etch comprising: Cl ₂ , 155 +/− 20% sccm SF ₆ , 80 +/− 20% sccm Ar, and 11 +/− 20% sccm CHF ₃ . (11) The silicon nitride etching process includes: 200 +/− 20% millitorr pressure, 1.5 +/− 10% cm gap, 130 +/− 20% watt power, 130 +/− 20% sccm Ar, and using the overetch containing CHF ₃ of 45 +/- 20% sccm, the method according to paragraph 10.

(12) The etching step includes forming a polymer on the surface of the silicon nitride, thereby reducing an etching rate at a shoulder of the silicon nitride covering a sidewall of the conductive structure. The manufacturing method as described. (13) The method according to item 12, further comprising:
(D) depositing a silicon dioxide layer on the exposed surfaces of the silicon nitride and semiconductor substrate; and (e) boron-phosphorus-silicon.
Depositing glass, (f) forming a mask for contact, (g) etching to the surface of the semiconductor substrate through the boron-phosphorus-silicon glass and silicon dioxide layer, (h) surface of the semiconductor substrate A method of manufacturing further comprising depositing a conductor over the entire surface for connection with the conductor.

(14) The integrated circuit processing sequence is performed as follows. A conductive structure 66 is formed on the semiconductor substrate along with a top layer 68 of silicon nitride and sidewalls 69 of silicon dioxide. An insulating layer 70 of silicon nitride is deposited on the entire substrate and on the sidewalls and top of the conductive structure. The silicon nitride layer is etched to form an opening through the silicon nitride 70 to the surface of the semiconductor substrate 56 without rounding the shoulder of the silicon nitride 70 covering the sidewalls of the conductive structure 66. Since the shoulder is left relatively square, the shoulder increases the margin for subsequent etching processes. The next deposited conductor is the conductive structure 6 on the semiconductor substrate.
6 and makes contact with the surface of the semiconductor substrate 56 without short-circuiting.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a part of a memory cell array having a conductive structure formed on a semiconductor substrate and peripheral circuits.

FIG. 2 is a partial cross-sectional view of FIG. 1 after a silicon nitride layer has been entirely deposited.

FIG. 3 is a partial cross-sectional view of FIG. 2 after dry etching of silicon nitride leaving a relatively square shoulder on the silicon nitride covering the sidewalls of the conductive structure.

FIG. 4 is a partial cross-sectional view of FIG. 3 after a silicon dioxide layer has been entirely deposited.

FIG. 5 Boron phosphorus silicon glass (BPSG)
FIG. 5 is a partial cross-sectional view of FIG. 4 after the layers have been fully deposited.

FIG. 6 is a partial cross-sectional view of FIG. 5 after a photoresist mask has been formed on the surface of the polysilicon layer deposited on the boron, phosphorus, silicon, and glass layers.

FIG. 7 is a partial cross-sectional view of FIG. 6 after the polysilicon layer has been etched to form a hard mask.

FIG. 8 is a partial cross-sectional view of FIG. 7 after the photoresist mask has been removed.

FIG. 9 is a partial cross-sectional view of FIG. 8 with a silicon oxide etch to form a storage node contact plug.

FIG. 10 is a partial cross-sectional view of FIG. 9 with a polysilicon deposit in contact with the surface of the semiconductor substrate.

FIG. 11 is a partial cross-sectional view of FIG. 10 after the polysilicon layer and the hard mask polysilicon have been removed by etching;

FIG. 12 is a partial cross-sectional view of FIG. 11 with an overall deposit of a silicon oxide layer from TEOS.

FIG. 13 is a partial cross-sectional view of FIG. 12 after a polysilicon layer has been deposited over the oxide.

FIG. 14 is a partial cross-sectional view of FIG. 13 with a patterned photoresist mask on top of a polysilicon layer.

FIG. 15 is a partial cross-sectional view of FIG. 14 with a dry etch of polysilicon to form a hard mask.

FIG. 16 is a partial cross-sectional view of FIG. 15 after the photoresist mask has been removed and the polysilicon hard mask has been left.

FIG. 16 with anisotropic dry etch of silicon oxide to form bit line contact holes.
FIG.

FIG. 18 is a partial cross-sectional view of FIG. 17 after the conductive material has been entirely deposited.

FIG. 19 is a partial cross-sectional view of FIG. 18 with formation of a photoresist mask for shaping the bit lines.

FIG. 20 is a partial cross-sectional view of FIG. 19 after the tungsten silicide layer and the polysilicon layer have been etched away to leave a shaped bit line;

FIG. 21 is a partial cross-sectional view of FIG. 20 with the removal of the photoresist mask;

FIG. 22 is a partial cross-sectional view of FIG. 21 after deposition of TEOS and silicon nitride has been entirely performed;

FIG. 23: BPSG deposition and etch back and T
FIG. 23 is a partial cross-sectional view of FIG. 22 with EOS deposition.

FIG. 24 is a partial cross-sectional view of FIG. 23 after the polysilicon has been entirely deposited.

FIG. 25 is a partial cross-sectional view of FIG. 24 accompanied by formation of a photoresist mask for opening a hole for connection to a storage node contact plug.

FIG. 26 is a partial cross-sectional view of FIG. 25 continuing dry etching of polysilicon for forming a hard mask under a photoresist mask;

FIG. 27 is a partial cross-sectional view of FIG. 26 after removal of the photoresist mask.

FIG. 28 is a partial cross-sectional view of FIG. 27 with dry etching through a silicon oxide layer to open a hole to the upper surface of the storage node contact plug.

FIG. 29 is a partial cross-sectional view of FIG. 28 after a polysilicon conductive layer has been entirely deposited.

FIG. 30 is a partial cross-sectional view of FIG. 29 with a deposit of a silicon oxide layer from TEOS.

FIG. 31 is a partial cross-sectional view of FIG. 30 after the photoresist has been deposited and formed into a mask.

FIG. 32 is a partial cross-sectional view of FIG. 31 with etching removal of silicon oxide excluding mesas under a photoresist mask;

FIG. 33 is a partial cross-sectional view of FIG. 32 with removal of the photoresist mask;

FIG. 34 after the metal layer has been fully deposited
FIG.

FIG. 35 is a partial cross-sectional view of FIG. 34 with a step of etching the metal layer to leave metal sidewalls on the remaining oxide mesas.

FIG. 36 is a partial cross-sectional view of FIG. 35 after the oxide mesas and other exposed oxide have been etched away.

FIG. 37 is a partial cross-sectional view of FIG. 36 with an overall deposit of a silicon oxide layer and a silicon nitride layer.

FIG. 38 is a partial cross-sectional view of FIG. 37 after, for example, polysilicon or metal is entirely deposited as a conductor layer.

FIG. 39 is a partial cross-sectional view of FIG. 38 after a photoresist mask has been formed on top of the boron-phosphorus-silicon glass layer to shape the bit line contact holes.

FIG. 40 is a partial cross-sectional view of FIG. 39 with a step of etching through a boron-phosphorus-silicon glass layer to create a hard mask for a bit line contact hole.

FIG. 41 is a partial cross-sectional view of FIG. 40 after removal of the photoresist;

FIG. 42 is a partial cross-sectional view of FIG. 41 with an oxide etch for a bit line contact hole.

FIG. 43 is a partial cross-sectional view of FIG. 42 with an etch to remove the boron phosphorus silicon glass layer.

FIG. 44 with deposit of two conductive material layers
3 is a partial sectional view.

FIG. 45 is a partial cross-sectional view of FIG. 44 after a photoresist layer formed on a bit line mask is deposited.

FIG. 46 is a partial cross-sectional view of FIG. 45 with etching of the conductive material layer and removal of the photoresist mask;

FIG. 47 is a partial cross-sectional view of FIG. 46 after two layers of insulating material have been deposited.

FIG. 48 is a partial cross-sectional view of FIG. 47 with the deposition of two additional layers of insulating material.

FIG. 49 is a partial cross-sectional view of FIG. 48 after a photoresist layer has been deposited and formed into a mask for forming a storage node contact hole.

FIG. 50 is a partial cross-sectional view of FIG. 49 with an oxide etch of a storage node contact hole.

FIG. 51 is a partial cross-sectional view of FIG. 50 after the photoresist mask has been removed, a layer of conductive material has been deposited, and silicon dioxide has been deposited on the conductor.

FIG. 52 is a partial cross-sectional view of FIG. 51 showing a photoresist masked on top of silicon dioxide.

FIG. 53 is a partial cross-sectional view of FIG. 52 with oxide etch and photoresist mask removal.

FIG. 54 is a partial cross-sectional view of FIG. 53 after a conductive material layer has been entirely deposited;

FIG. 55 is a partial cross-sectional view of FIG. 54 with an anisotropic etch of the conductive material layer.

FIG. 56 is a partial cross-sectional view of FIG. 55 after oxide dry etch to clarify the torch shaped storage node contact region.

FIG. 57 with the deposition of an insulating material layer and the deposition of a conductive material layer as a field plate.
FIG.

FIG. 58 is an exemplary cross-sectional view of a device having a conductive layer that is properly insulated from the conductive contact area.

FIG. 59 is a cross-sectional view of a conventional device having a conductive layer improperly insulated from a conductive contact area.

[Explanation of symbols]

 57 Semiconductor substrate surface 62 Silicon dioxide layer 66 Laminated conductor 68 Silicon nitride 69 Silicon dioxide 70 Silicon nitride

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 29/78

Claims (1)

[Claims] 1. A method for manufacturing an integrated circuit device, comprising: (a) forming a conductive structure having an upper layer of silicon nitride and a silicon dioxide sidewall on a semiconductor substrate; Depositing an insulating layer on the entire substrate and on the sidewalls and top of the conductive structure;
(C) forming the opening through the silicon nitride to the surface of the semiconductor substrate without substantially rounding the shoulder of the silicon nitride covering the side wall of the conductive structure; A method for manufacturing an integrated circuit device, comprising the step of etching a substrate.