JPH1041604A - Wiring board - Google Patents
Wiring boardInfo
- Publication number
- JPH1041604A JPH1041604A JP8197615A JP19761596A JPH1041604A JP H1041604 A JPH1041604 A JP H1041604A JP 8197615 A JP8197615 A JP 8197615A JP 19761596 A JP19761596 A JP 19761596A JP H1041604 A JPH1041604 A JP H1041604A
- Authority
- JP
- Japan
- Prior art keywords
- bare chip
- pad
- wiring
- insulator
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、基板上に部品を実
装して配線する配線基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board for mounting and wiring components on a board.
【０００２】[0002]
【従来の技術】従来、プリント基板上にベアチップを実
装する場合、図４に示すように、ベアチップの表面から
ワイヤボンディングで基板上のパッド部に接続すると共
に、ベアチップの裏面に接地（あるいは電源電圧）を印
加するためにのダイボンディングを行っていた。2. Description of the Related Art Conventionally, when a bare chip is mounted on a printed circuit board, as shown in FIG. 4, the surface of the bare chip is connected to a pad portion on the board by wire bonding and the ground (or power supply voltage) is connected to the back surface of the bare chip. ) Was performed by die bonding.
【０００３】図４は、従来技術の説明図を示す。図４の
（ａ）は、平面図を示す。これは、プリント基板上にベ
アチップを図示のように配置し、当該ベアチップのパッ
ド部と、周辺のプリント基板上のパッド部とをワイヤで
ボンディングして接続する様子を示す。FIG. 4 shows an explanatory diagram of the prior art. FIG. 4A shows a plan view. This shows a state in which a bare chip is arranged on a printed board as shown in the figure, and a pad portion of the bare chip is connected to a pad section on a peripheral printed board by bonding with a wire.
【０００４】図４の（ｂ）は、断面図を示す。これは、
図示のように、プリント基板上にダイボンディングパッ
ドを設けその上にベアチップを配置し、当該ベアチップ
からワイヤでプリント基板上のパッド部にボンディング
して接続する様子を示す。FIG. 4B shows a sectional view. this is,
As shown, a die bonding pad is provided on a printed circuit board, a bare chip is arranged thereon, and the bare chip is bonded to a pad portion on the printed circuit board with a wire to connect.
【０００５】[0005]
【発明が解決しようとする課題】上述した図４に示すよ
うに、ベアチッチをプリント基板上に実装する場合に当
該ベアチップの裏面はダイボンディングパットがあるた
めに、ベアチップの真下のプリント基板上には配線がで
きなく、ベアチップの周りのプリント基板上に多くのス
ペースが必要になってしまう問題があった。As shown in FIG. 4 described above, when a bare chip is mounted on a printed circuit board, the back surface of the bare chip has a die bonding pad. There was a problem that wiring could not be performed and a lot of space was required on the printed circuit board around the bare chip.
【０００６】本発明は、これらの問題を解決するため、
部品実装する真下の部分に絶縁層を設けてこの部分にス
ルーホールを設けて部品からのワイヤボンディングでき
る配線数を増加などさせ、実装部品の狭い周辺に多数の
配線を実現およびスペースの有効活用を図ることを目的
としている。[0006] The present invention solves these problems,
An insulation layer is provided directly below the component mounting area, and a through hole is provided in this area to increase the number of wires that can be wire-bonded from the component. It is intended for planning.
【０００７】[0007]
【課題を解決するための手段】図１を参照して課題を解
決するための手段を説明する。図１において、プリント
基板１は、実装部品を実装する基板である。Means for solving the problem will be described with reference to FIG. In FIG. 1, a printed board 1 is a board on which mounted components are mounted.
【０００８】絶縁物３は、プリント基板１と実装部品で
あるベアチップ４などとを絶縁するものである。ベアチ
ップ４は、実装部品の１例である。The insulator 3 insulates the printed board 1 from the mounted components such as the bare chip 4 and the like. The bare chip 4 is an example of a mounting component.
【０００９】次に、構造を説明する。実装部品であるベ
アチップ４の裏面と当該ベアチップ４を搭載するプリン
ト基板１上との間に絶縁物３を配置し、絶縁物３を配置
したプリント基板１の部分にベアチップ４とワイヤボン
ディングで接続する第１のパッド部２５あるいは／およ
び実装部品のグランドに接続する第１のパッド部２６を
設け、このパッド部をスルーホール２１でプリント基板
１の反対側の配線に接続あるいはプリント基板１の配線
に接続すると共に、絶縁物３を配置しない周辺にベアチ
ップ４とワイヤボンディグする第２のパッド部２３を設
け、絶縁物３のある部分を有効利用するようにしてい
る。Next, the structure will be described. The insulator 3 is arranged between the back surface of the bare chip 4 as a mounting component and the printed board 1 on which the bare chip 4 is mounted, and the bare chip 4 is connected to the portion of the printed board 1 on which the insulator 3 is arranged by wire bonding. A first pad portion 26 is provided for connecting to the first pad portion 25 and / or the ground of the mounted component, and this pad portion is connected to the wiring on the opposite side of the printed board 1 through the through hole 21 or to the wiring of the printed board 1. In addition to the connection, a second pad portion 23 for wire bonding with the bare chip 4 is provided around the periphery where the insulator 3 is not arranged, so that a portion of the insulator 3 is effectively used.
【００１０】この際、絶縁物３のある部分から外に向か
った配線の先端の第１のパッド部２５および絶縁物３の
方に向かう第２のパッド部２３を相対向して千鳥状に設
け、ワイヤボンディグや配線で接続しやすいようにして
いる。At this time, a first pad portion 25 at the tip of the wiring extending outward from a portion of the insulator 3 and a second pad portion 23 facing the insulator 3 are provided in a staggered manner so as to face each other. , So that it can be easily connected by wire bonding or wiring.
【００１１】また、実装部品としてベアチップ４あるい
はトランジスタとするようにしている。従って、部品実
装するベアチップ４などの真下の部分に絶縁物３を設け
てこの部分にスルーホール２１などを設けてベアチップ
４などからのワイヤボンディングできる配線数を増加さ
せるなどすることにより、実装部品であるベアチップ４
やパワートランジスタ５などの狭い周辺に多数の配線を
実現およびスペースの有効活用を図ることが可能とな
る。Further, a bare chip 4 or a transistor is used as a mounting component. Therefore, the insulator 3 is provided in a portion directly below the bare chip 4 or the like on which components are mounted, and a through hole 21 or the like is provided in this portion to increase the number of wires that can be wire-bonded from the bare chip 4 or the like. A certain bare chip 4
A large number of wirings can be realized in a narrow periphery such as the power transistor 5 and the power transistor 5, and the space can be effectively used.
【００１２】[0012]
【発明の実施の形態】次に、図１から図３を用いて本発
明の実施の形態および動作を順次詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment and operation of the present invention will be sequentially described in detail with reference to FIGS.
【００１３】図１は、本発明の１実施例構成図を示す。
図１の（ａ）は、平面図を示す。これは、点線で示す部
分にベアチップ４を搭載するプリント基板１の上から見
た図であって、外側から点線の部分に向かった配線の先
のパッド部２３と、点線の部分の内のスルーホール２１
から外方向に向かった配線の先のパッド部２５とを設
け、点線の部分の内の部分を有効利用したものである。FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 1A shows a plan view. This is a top view of the printed circuit board 1 on which the bare chip 4 is mounted on the portion indicated by the dotted line, and the pad portion 23 of the wiring from the outside toward the dotted line portion and the through portion in the dotted line portion Hall 21
And a pad portion 25 at the end of the wiring which is directed outward from, and the portion within the dotted line portion is effectively used.
【００１４】図１の（ｂ）は、断面図を示す。図１の
（ｂ）において、プリント基板１は、ベアチップ４など
の部品を実装する基板であって、ここでは、図１の
（ａ）に示すように、ベアチップ４を実装する部分の外
から点線の部分に向かう配線の先にパッド部２３を設け
ると共に、ベアチップ４を実装する部分の点線の内のス
ルーホール２１に接続した、外方向に向かう配線の先に
パッド部２５とを設け、これら両者のパッド部２３およ
び２５にベアチップ４からのワイヤをボンディングして
接続するようにしている。FIG. 1B is a sectional view. In FIG. 1B, a printed circuit board 1 is a substrate on which components such as a bare chip 4 are mounted, and here, as shown in FIG. The pad 23 is provided at the end of the wiring toward the part, and the pad part 25 is provided at the end of the wiring toward the outside, which is connected to the through hole 21 in the dotted line of the part where the bare chip 4 is mounted. The wires from the bare chip 4 are bonded to the pad portions 23 and 25 by bonding.
【００１５】スルーホール２１は、プリント基板１のベ
アチップ４を実装する点線の内側で反対側の配線に接続
するためのものである。導体２は、銅などの配線であ
る。The through hole 21 is for connecting to the wiring on the opposite side inside the dotted line for mounting the bare chip 4 of the printed circuit board 1. The conductor 2 is a wiring such as copper.
【００１６】導電性樹脂２２は、プリント基板１上の導
体２と、ベアチップ４とを電気的に接続するものであ
る。絶縁物３は、プリント基板１とベアチップ４との間
に配置し、両者を電気的に絶縁するためのものである。The conductive resin 22 electrically connects the conductor 2 on the printed circuit board 1 and the bare chip 4. The insulator 3 is arranged between the printed circuit board 1 and the bare chip 4 to electrically insulate them.
【００１７】ベアチップ４は、プリント基板１上に搭載
しようとするＩＣやトランジスタなどの部品であって、
図示のように、ワイヤによってプリント基板１上に設け
た、外側から点線の部分に向かった配線の先のパッド部
２３と点線の部分の内のスルーホール２１から外方向に
向かった配線の先のパッド部２５とにボンディングなど
して接続するものである。The bare chip 4 is a component such as an IC or a transistor to be mounted on the printed circuit board 1,
As shown in the drawing, a pad portion 23 provided on the printed circuit board 1 with a wire and extending from the outside toward the dotted line portion and a wire portion extending outward from the through hole 21 in the dotted line portion. It is connected to the pad section 25 by bonding or the like.
【００１８】次に、構造を説明する。プリント基板１の
ベアチップ４を実装する側の面には、図１の（ａ）に示
すように、外側から点線の部分（ベアチップ４を実装す
る部分）に向かって配線（導体２）を設けてその先端部
分をパッド部２３とすると共に、点線の部分の内側でス
ルーホール２１によってプリント基板１の裏面から表面
に接続して当該スルーホール２１の部分から外方向に向
かって配線を設けてその先端をパッド部２５とする。こ
の構造を持つプリント基板１の上に絶縁物３を配置し、
その上にベアチップ４を搭載し接着する。そして、ベア
チップ４上の図示外のパッド部と、プリント基板１上の
パッド部との間を細いワイヤでボンディングして接続す
る。この際、ベアチップ４の裏面は、プリント基板１上
の配線（導体２）と導電性樹脂で電気的な接続（ＧＮＤ
あるいは電源Ｖｃｃの接続）を行う。Next, the structure will be described. As shown in FIG. 1A, wiring (conductor 2) is provided on the surface of the printed circuit board 1 on the side where the bare chip 4 is mounted, as shown in FIG. The front end portion is used as a pad portion 23, and a connection is made from the back surface to the front surface of the printed circuit board 1 by a through hole 21 inside the dotted line portion, and wiring is provided outward from the through hole 21 portion. Is the pad section 25. An insulator 3 is arranged on a printed circuit board 1 having this structure,
The bare chip 4 is mounted thereon and bonded. Then, a pad portion (not shown) on the bare chip 4 and a pad portion on the printed circuit board 1 are connected by bonding with a thin wire. At this time, the back surface of the bare chip 4 is electrically connected to the wiring (conductor 2) on the printed circuit board 1 with a conductive resin (GND).
Alternatively, the power supply Vcc is connected).
【００１９】以上の図１の構成により、ベアチップ４を
実装する点線の部分について、本発明ではスルーホール
２１を設けてプリント基板１の裏面の配線と接続するな
どに有効利用することが可能となる。According to the configuration of FIG. 1 described above, the dotted line portion on which the bare chip 4 is mounted can be effectively used in the present invention, for example, by providing a through hole 21 and connecting to the wiring on the back surface of the printed circuit board 1. .
【００２０】図２は、本発明の他の実施例構成図を示
す。これは、プリント基板１上の配線、スルーホール、
およびパッド部の様子を示したものであって、図示のよ
うに、点線のベアチップ４を実装する部分の外側からの
パッド部２３と、点線の部分の内側のスルーホール２４
からのパッド部２５とを千鳥状に配置し、非常に多くの
パッド部の配置を実現した他の実施例の構成、例えば従
来の約２倍のパッド部を設けることができる構成であ
る。FIG. 2 is a block diagram showing another embodiment of the present invention. This is the wiring on the printed circuit board 1, through holes,
And the state of the pad portion, as shown in the drawing, the pad portion 23 from the outside of the portion where the bare chip 4 is mounted in the dotted line, and the through hole 24 inside the portion in the dotted line as shown in the figure.
And the pad portions 25 are arranged in a staggered manner, and a configuration of another embodiment in which a very large number of pad portions are realized, for example, a configuration in which a pad portion approximately twice as large as the conventional one can be provided.
【００２１】図３は、本発明の他の実施例構成図を示
す。これは、図１および図２のベアチップ４の代わりに
パワートランジスタ５をプリント基板１上に実装する場
合の構成である。FIG. 3 shows another embodiment of the present invention. This is a configuration in which a power transistor 5 is mounted on the printed circuit board 1 instead of the bare chip 4 in FIGS. 1 and 2.
【００２２】図３において、パワートランジスタ５は、
この例ではコレクタ５１、エミッタ５２、およびベース
５３をそれぞれ図示のような配置となるものである。パ
ッド部５４、５６は、プリント基板１とパワートランジ
スタ５のコレクタ５１、エミッタ５２、およびベース５
３とそれぞれ接続するためのものである。In FIG. 3, a power transistor 5 is
In this example, the collector 51, the emitter 52, and the base 53 are arranged as shown in the figure. The pad portions 54 and 56 include the printed board 1, the collector 51 of the power transistor 5, the emitter 52, and the base 5.
3 are connected to each other.
【００２３】絶縁体３は、パワートランジスタ５とプリ
ント基板１との間を絶縁し、プリント基板１上に別のパ
ターン（配線）５５を設けるためのものである。このよ
うに、パワートランジスタ５とプリント基板１との間に
絶縁体３を設け、当該絶縁体３の部分に別のパターン５
５を設けて有効利用することが可能となる。The insulator 3 insulates between the power transistor 5 and the printed board 1 and provides another pattern (wiring) 55 on the printed board 1. Thus, the insulator 3 is provided between the power transistor 5 and the printed circuit board 1, and another pattern 5 is provided on the insulator 3.
5 can be used effectively.
【００２４】[0024]
【発明の効果】以上説明したように、本発明によれば、
ベアチップ４などの真下の部分に絶縁物３を設けてこの
部分にスルーホール２１や別のパターンなどを設けてベ
アチップ４などからのワイヤボンディングできる配線数
を増加させたり、実装部品とは接続しない別のパターン
を設けたりする構成を採用しているため、実装部品であ
るベアチップ４などの狭い周辺に多数の配線を実現およ
びスペースの有効活用を図ることができる。As described above, according to the present invention,
An insulator 3 is provided directly below the bare chip 4 or the like, and a through hole 21 or another pattern is provided in this portion to increase the number of wires that can be wire-bonded from the bare chip 4 or the like. Is adopted, a large number of wirings can be realized in a narrow area such as the bare chip 4 as a mounting component, and the space can be effectively used.
【図１】本発明の１実施例構成図である。FIG. 1 is a configuration diagram of one embodiment of the present invention.
【図２】本発明の他の実施例構成図である。FIG. 2 is a configuration diagram of another embodiment of the present invention.
【図３】本発明の他の実施例構成図である。FIG. 3 is a configuration diagram of another embodiment of the present invention.
【図４】従来技術の説明図である。FIG. 4 is an explanatory diagram of a conventional technique.
１：プリント基板 ２：導体 ２１、２４：スルーホール ２２：導電性樹脂 ２３、２５、２６、５４、５６：パッド部 ３：絶縁物（絶縁体） ４：ベアチップ ５：パワートランジスタ ５１：コレクタ ５２：エミッタ ５３：ベース ５５：別のパターン 1: Printed circuit board 2: Conductor 21, 24: Through hole 22: Conductive resin 23, 25, 26, 54, 56: Pad portion 3: Insulator (insulator) 4: Bare chip 5: Power transistor 51: Collector 52: Emitter 53: Base 55: Another pattern
Claims (3)
において、 上記実装部品と当該実装部品を搭載する基板上との間に
配置する絶縁層と、 当該絶縁層を配置する上記基板の部分に設け、上記実装
部品とワイヤボンディングで接続する第１のパッド部あ
るいは／および実装部品のグランドに接続する第１のパ
ッド部につながったスルーホールあるいは配線と、 上記実装部品の上記絶縁層を配置しない周辺に設け、上
記実装部品とワイヤボンディグあるいは接続する第２の
パッド部とを備えたことを特徴とする配線基板。1. A wiring board for mounting and wiring components on a substrate, comprising: an insulating layer disposed between the mounted component and a substrate on which the mounted component is mounted; A first pad portion connected to the mounting component by wire bonding and / or a through hole or a wiring connected to the first pad portion connected to the ground of the mounting component; and the insulating layer of the mounting component. A wiring board, which is provided around a non-arranged portion, and includes the above-mentioned mounting component and a wire bonding or a second pad portion for connection.
ド部を相対向して千鳥状に設けたことを特徴とする請求
項１記載の配線基板。2. The wiring board according to claim 1, wherein said first pad portion and said second pad portion are provided in a staggered manner so as to face each other.
面に端子が露出している半導体素子部品であることを特
徴とする請求項１あるいは請求項２記載の配線基板。3. The wiring board according to claim 1, wherein the mounting component is a bare chip or a semiconductor device component having terminals exposed on the back surface of the component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8197615A JPH1041604A (en) | 1996-07-26 | 1996-07-26 | Wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8197615A JPH1041604A (en) | 1996-07-26 | 1996-07-26 | Wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1041604A true JPH1041604A (en) | 1998-02-13 |
Family
ID=16377427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8197615A Pending JPH1041604A (en) | 1996-07-26 | 1996-07-26 | Wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1041604A (en) |
-
1996
- 1996-07-26 JP JP8197615A patent/JPH1041604A/en active Pending
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