JPH1041500A - Semiconductor device and production of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively prevent a threshold voltage from being fluctuated because of the shortening of a gate length by canceling the short channel effect while utilizing the reverse short channel effect. SOLUTION: This device has a semiconductor wafer 20, source and drain regions 24a and 24b, which are formed on the surface of the wafer at a distance from each other, and a gate electrode 30 formed through a gate insulating film 28 on a channel region 26 sandwiched between the regions 24a and 24b, and local insulating regions 30a and 30b are formed at the lower end part of the gate electrode 30 confronted through the gate insulating film 28 to both terminal parts of the channel region 26 in contact with either of both the areas 24a and 24b. In order to form the local insulating parts 30a and 30b, it is better to locally perform thermal oxidation from the outside of the gate electrode 30 to the upside of both terminal parts of the channel region 26. It is preferable the heating conditions of local thermal oxidation are set within the range not to rearrange impurities in the source region 24a and the drain region 24b on the surface side of the wafer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a threshold voltage of an insulated gate type field effect transistor constituting the semiconductor device, which becomes apparent as the gate length becomes shorter. The present invention relates to a technique for effectively preventing a decrease in the temperature.

[0002]

2. Description of the Related Art In recent years, MOS LSI (Metal Oxide Se
With the development of high integration and high density in the Large Scale Integrated Circuit (MOS), MOSFE
The element size of T (Field Effect Transistor) is becoming finer.

With the miniaturization of MOSFETs, the threshold voltage decreases as the gate length decreases.
A so-called roll-off effect occurs. In particular, M where MOSFETs with different gate lengths are mixedly mounted
In an OS LSI, the threshold voltage fluctuation of a MOSFET becomes more non-uniform as the number of mixed gate lengths increases, and the threshold voltage of a MOSFET having a short gate length that is frequently used in high integration is increased. Becomes larger. Therefore, in the circuit design of MOS LSI,
In order to achieve desired characteristics, it is extremely important to effectively suppress the occurrence of a roll-off effect (hereinafter, collectively referred to as a "short channel effect") accompanying a reduction in gate length.

[0004]

By the way, a certain M
In the OSFET, when the gate length is shortened, a phenomenon called a so-called inverse short channel effect occurs, in which the threshold voltage once rises, contrary to the normal short channel effect. The voltage may drop sharply (see “Semiconductor Process and Device Simulation Technology” Realize, pp. 297-301).

The following two are cited as causes of the inverse short channel effect. One of the reasons is that when the source / drain regions are formed, a pile-up of impurities occurs near the source / drain regions due to the effect of point defects generated by ion implantation. . That is, due to the impurity pile-up near the source / drain regions, the surface potential along the source / drain direction decreases at both ends of the channel, and as a result, a region having a high threshold voltage is formed at both ends of the channel. When the gate length becomes shorter, the contribution occupied by this region becomes remarkable, and the threshold voltage as a whole increases.

The other is to explain that it is caused by a shape effect due to fine gate bird's beak at the end of the gate electrode. FIG. 9 (a)
FIG. 3 is a schematic diagram of a MOSFET for explaining a shape effect by the gate bird's beak. This MOSFET
2, a source region 6 a and a drain region 6 b are formed facing each other on the surface of the semiconductor substrate 4, and a gate electrode 12 is formed on a channel region 8 interposed therebetween through a gate oxide film 10. The entire surface is covered with a surface protection film 14. In the MOSFET 2 having such a structure, a bird's beak-shaped silicon oxide film 1 is interposed between the lower surface of both ends of the gate electrode 12 and the source region 6a or the drain region 6b.
6, the dominant ability of the gate electrode 12 in the channel region 8 is reduced in this portion, so that the surface potential is lowered. As a result, the threshold voltage is increased as in the case of the impurity pile-up. I do.

FIG. 9B is a simulation result of the dependence of the threshold voltage on the gate length using the bird's beak silicon oxide film thickness as a parameter. In the figure, each graph line shows a bird's beak-shaped silicon oxide film 16 on the gate insulating film 10 above the gate electrode 1.
2 Approximate with a model whose wall thickness increases linearly outward,
The case where the thickness Δy at the end of the gate electrode 12 is changed is shown. Here, the lateral dimension △ x of the approximate area is described in O.D. The width of the overlap portion between the gate electrode 12 and the drain region 6b (or the source region 6a) is set to 0.16 μm.

When the bird's beak-shaped silicon oxide film 16 does not exist (Δy = 0), the threshold voltage decreases as the gate length becomes shorter due to the usual short channel effect. On the other hand, the bird's beak-shaped silicon oxide film 16 is interposed, and the thickness is set to Δy = 0.05 to 0.2.
When the thickness is increased in the range of 15 μm, first, Δy = 0.05 μ
m, the degree of decrease in the threshold voltage decreases, and when the silicon oxide film 16 is further thickened, the threshold value tends to increase (Δy = 0.1 to 0.15 μm). This increase in the threshold voltage indicates the occurrence of the above-described inverse short channel effect. Then, if the gate length is further reduced, the punch-through tends to occur, so that the threshold voltage rapidly decreases.

As described above, by intentionally utilizing the reverse short channel effect, the short channel effect can be canceled out, and a fine MOSFET having a small variation in threshold voltage even when the gate length varies can be manufactured. It is considered to be. It was expected to some extent that this threshold voltage variation control was possible in principle,
There is no technology to accurately form a bird's beak-shaped silicon oxide film, and if this shape is not uniform, there is a strong possibility that the variation in threshold voltage will be rather large, so that it has not been realized as a specific device until now. .

SUMMARY OF THE INVENTION The present invention has been made in consideration of a demand for effectively and practically embodying the above-described threshold voltage variation control method, and has been made by intentionally utilizing the inverse short channel effect. It is an object of the present invention to provide a semiconductor device which balances with a short channel effect and has a small variation in threshold voltage even when the gate length is shortened, and a method for manufacturing the same.

[0011]

In order to solve the above-mentioned problems of the prior art and to achieve the above object, the present invention provides an M
In an IS (Metal Insulator Semiconductor) FET, a local insulating portion in which the gate electrode is locally insulated is formed at the lower end of the gate electrode above both ends of the channel region in contact with the source region and the drain region. The purpose is to prevent the threshold voltage from lowering. That is, in the semiconductor device of the present invention, a semiconductor substrate, a source region and a drain region (a low-concentration impurity region in the case of an LDD structure) formed at a distance from each other on the semiconductor substrate;
A gate electrode formed on a channel region interposed between the source region and the drain region, with a gate electrode formed therebetween with a gate insulating film interposed therebetween; A local insulating portion is formed at a lower end of the gate electrode facing through a film.

Near the center of the channel region, a gate electrode is formed via a gate insulating film, whereas at both ends of the channel, a gate electrode is formed via a local insulating portion in addition to the gate insulating film. Have been. Therefore, the distance of the gate electrode from the channel region is relatively longer at both ends than at the center of the channel region, and the dominant ability of the gate electrode at both ends is reduced. The surface potential decreases at both ends of the channel region, and as a result, a portion having a high threshold voltage is formed at both ends. Then, as the gate length becomes shorter, the contribution of the portion having a higher threshold voltage becomes remarkable, and the threshold voltage as a whole increases. Therefore, according to the present invention, the inverse short channel effect and the normal short channel effect based on the shortening of the gate length can be counterbalanced with each other. As a result, even if the gate length is reduced to some extent, The threshold voltage does not decrease.

In the method of manufacturing a semiconductor device according to the present invention, a gate electrode is formed on a semiconductor substrate via a gate insulating film, and impurity ions are implanted using the gate electrode as a mask to form a source region and a source region in the semiconductor substrate. A drain region is formed at a distance from each other, and both ends of a channel region sandwiched between the source region and the drain region (in the case of the LDD structure, two low-concentration impurity regions) via the gate insulating film. A local insulating portion is formed at a lower end of the facing gate electrode by partially insulating the gate electrode.

The local insulating portion is formed, for example, by laminating a gate oxide film and a gate electrode on a semiconductor substrate and, with their end faces exposed, lowering the lower end of the gate electrode from outside the gate electrode. This is performed by locally performing thermal oxidation (or thermal nitridation) over both ends of the channel region. Specifically, for example, a gate electrode is formed of a material such as polysilicon, and a narrowly focused laser beam is irradiated at a predetermined power for a predetermined time in an oxygen (or nitrogen) atmosphere toward the lower end surface of the polysilicon. As a result, the local insulating portion is formed at least on both ends of the channel region where the surface potential needs to be reduced. At this time, it is preferable to set the heating condition of the local thermal oxidation to a range in which the impurities in the source region and the drain region on the substrate surface side do not rearrange. This is to prevent the source / drain resistance of the MISFET from increasing or the characteristic fluctuation due to the increase.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to the present invention and a method for manufacturing the same will be described in detail with reference to the drawings. First Embodiment FIG. 1 shows a schematic configuration of an n-channel MOSFET constituting a semiconductor device according to the present embodiment. FIG. 1A is a schematic sectional view, FIG. 1B is a partially enlarged view thereof, and FIG. Is a main part dimensional diagram. In FIG. 1A, reference numeral 20 denotes a semiconductor substrate composed of, for example, a p-type silicon substrate, and its substrate 2
A field oxide film 22 is formed on the surface 0 to perform element isolation.

On the surface of the active region surrounded by the field oxide film 22, a source region 24a and a drain region 24b, which are heavily doped with n-type impurities such as As (arsenic), are formed facing each other. Have been. As a result, these sources /
A channel region 26 is formed between the drain regions 24a and 24b. When the device structure is a target as in the illustrated example, the source region 24a and the drain region 24b may be interchanged. And
On this channel region 26, a gate electrode 30 made of a polysilicon film doped with an n-type impurity such as P (phosphorus) is formed via a gate oxide film 28.

In the semiconductor device of the present invention, FIG.
As shown in (c) in an enlarged manner, the insulating film portion interposed between the end of the channel region 26 in contact with the source region 24a and one lower end of the gate electrode 30 forms the channel region 26.
Is formed thicker than the vicinity of the center. Similarly, the insulating film portion interposed between the end of the channel region 26 in contact with the drain region 24b and the other lower end of the gate electrode 30 is
The channel region 26 is formed thicker than near the center.
More specifically, as shown in FIG. 1C, in the thick insulating film portion, the gate oxide film 28 and the lower end corner portion of the gate electrode 30 in contact with the upper surface are locally insulated. The resulting local insulation portions 30a, 30b;
It is composed of These local insulating portions 30a, 30b
The method of forming will be described later in detail.

On the entire surface of the gate electrode 30, an interlayer insulating film 32 is formed. Then, the source electrode 34a and the drain electrode 34b made of a metal film such as Al are electrically connected to either the source region 24a or the drain region 24b via the contact hole 32a opened in the interlayer insulating film 32. Wired.

Next, a method of manufacturing a semiconductor device according to the present invention will be described with reference to the drawings, using the n-channel MOSFET shown in FIG. 1 as an example. Here, FIGS. 2 to 5 are schematic cross-sectional views showing respective manufacturing steps of the n-channel MOSFET shown in FIG. First, a semiconductor substrate 20 such as a p-type Si substrate is prepared.
The field oxide film 22 is selectively formed by using an OS (Local Oxidation of Silicon) method. In order to form the field oxide film 22, first, an oxidation prevention film such as a pad oxide film and a silicon nitride film are laminated in this order, and these are processed into a predetermined pattern by dry etching.
Perform OCOS oxidation. Thereby, isolation between elements is achieved.

Next, if necessary, ion implantation for a channel stopper is performed. After the annealing, the oxidation preventing film is removed, and a gate oxide film 28 is formed thereon by using a thermal oxidation method or the like. . Thereby, the field oxide film 2
The active region surrounded by 2 is covered with a gate oxide film 28. The thickness of the gate oxide film 28 is not particularly limited, but is set to, for example, about 7 to 15 nm, here, 14 nm.

Next, for example, CVD (Chemical Vapor D)
After a polysilicon film is deposited on the entire surface by using an eposition method, the polysilicon layer is doped with, for example, P (phosphorus) to reduce the resistance. Then, using a photolithography technique and an etching technique, the polysilicon film is patterned into a predetermined shape, and a gate electrode 30 made of a conductive polysilicon film is formed on the gate oxide film 28. In the present invention, the material of the gate electrode 30 needs to be selected from materials that can be insulated later.

Using the gate electrode 30 and the field oxide film 22 as a mask and the gate oxide film 28 as a through film, the source region 2 is formed on the active region surface by ion implantation.
4a and the drain region 24b are formed. Specifically, for example, after As ions are implanted at a high concentration, a heat treatment for electrically activating the implanted ions is performed. As a result, the opposite source region 24a is formed on the surface of the semiconductor substrate 20.
And drain region 24b are formed in self-alignment with gate electrode 30. Note that, mainly due to heat treatment, the source region 24a and the drain region 24b are
It wraps around below 0 to form a slightly overlapped portion. Then, a channel region 26 is formed in the active region sandwiched between the source region 24a and the drain region 24b.

The steps up to here are the same as those of a normal n-channel MO.
This is the same as the standard manufacturing process of the SFET, but in the present invention, a local insulating step of the gate electrode 30 is newly inserted. That is, as shown in FIG. 3, the vicinity of both lower ends of the gate electrode 30 in contact with the gate oxide film 28 is locally thermally oxidized by, for example, irradiation with a laser beam or the like in an oxygen atmosphere. Thereby, local insulated portions 30a and 30b in which both lower ends of the gate electrode 30 are insulated in a wedge shape are formed.

The irradiation conditions of the laser beam (beam spot diameter, energy density, irradiation time, etc.)
6, the gate oxide film 28 and the local insulating portion 30
It is determined by what value the total thickness of a and 30b is set to. First, as shown in FIG. 1, the local insulating portions 30a and 30b have a width Δ in the gate length direction.
The boundary profile between x, the maximum thickness Δy, and the gate electrode 30 is determined in relation to the gate length of the MOSFET. For example, based on the simulation result shown in FIG. 9B or the measured data, the sizes of the local insulating portions 30a and 30b are determined according to the gate length and in consideration of the width W of the overlap portion in FIG. Is determined, and based on this, the optimum laser beam irradiation conditions are selected.

In determining the laser beam irradiation conditions, it is necessary to consider that the impurities in the source region 24a and the drain region 24b are not rearranged. This is because, if the rearrangement of the impurities occurs, there is a strong possibility that the source / drain resistance of the MOSFET is increased or the characteristics are degraded due to the increase. In this sense, it is preferable to use an excimer laser beam which has a high energy density and can be annealed at high temperature for a short time by pulse application as a laser light source.

As described above, the same effect as when the thickness of the silicon oxide film 18 interposed between the lower ends of the gate electrode 30 and the surface of the active region is apparently increased at both ends. This effect will be described at the end of this embodiment. The local insulating portions 30a and 30b are not limited to oxide films, and may be, for example, a nitride film obtained by laser irradiation in a nitrogen atmosphere, an oxynitride film, or another type of insulating film.

In the next step of FIG. 4, the upper and side surfaces of the gate electrode 30 and the silicon oxide film 28 on the active region are removed by anisotropic etching.
Only under the silicon oxide film 28 and the local insulating portion 30.
a and 30b are left. Next, in the step of FIG.
After depositing the interlayer insulating film 32 on the entire surface by using, for example, the CVD method, a contact hole 32a is opened on the source region 24a and the drain region 24b.

After that, a metal film such as Al is formed on the entire surface by, for example, a sputtering method, and then the metal film is patterned into a predetermined shape by using a photolithography technique and an etching technique. Thereby, as shown in FIG. 1, the source region 24 is formed through the contact hole 32a.
The source electrode 34a and the drain electrode 34b connected to the a and drain regions 24b, respectively, are formed, and the fabrication process of the n-channel MOSFET shown in FIG. 1 is completed.

As described above, in the n-channel MOSFET according to the present embodiment, the lower end of the gate electrode 30 on the gate electrode film 28 is located above both ends of the channel region 26 in contact with the source region 24a and the drain region 24b. ,
Local insulating portions 30a and 30b are formed. Therefore, the distance of the gate electrode 30 from the channel region 26 is
Both ends are relatively farther than the center of the channel region, and the ability of the gate electrode 30 to be controlled at both ends of the channel region 26 is reduced. As a result,
The surface potential along the drain direction decreases at both ends of the channel region 26, and a region having a high threshold voltage is formed at both ends. Then, as the length of the gate electrode 30, that is, the gate length becomes shorter, the contribution occupied by this region becomes remarkable, and an inverse short channel effect occurs in which the threshold voltage increases as a whole.

Therefore, the reverse short channel effect and the normal short channel effect based on the shortening of the gate length can be balanced and cancel each other. As a result, even if the gate length becomes short to some extent, The threshold voltage is prevented from lowering.

The n-channel MOS according to the present embodiment
According to the method of manufacturing the FET, the normal n-channel MOSF
Since only a local insulating process of the gate electrode 30 shown in FIG. 3 is added to the ET manufacturing process, it is not necessary to add a photolithography process or the like using a new photomask process. In addition to the local insulating process, the time and cost required for the manufacturing are almost the same as those of the conventional case, and the short channel effect is canceled by using the inverse short channel effect, and the fluctuation of the threshold voltage is small. Channel M
OSFETs can be manufactured.

Items other than those mentioned in the above description are not particularly limited, and can be variously modified within the scope of the present invention. For example, the etch-off step of the gate oxide film 28 in FIG. 4 is not always necessary, and the gate oxide film 28 may be left on the entire surface and may be opened simultaneously with the opening of the contact hole 32a in FIG.

Second Embodiment This embodiment is a case where the present invention is applied to an n-channel MOSFET having an LDD structure. Here, FIG. 6A is a sectional view showing an n-channel MOSFET having an LDD structure according to the present embodiment, FIG. 6B is a partially enlarged view thereof, and FIG. is there. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

An n-channel MOSFET shown in FIG.
Is basically an n-channel MOS shown in FIG.
It has the same structure as the FET, except that the source / drain region has an LDD structure. In the first embodiment, the gate electrode 30 is formed in a self-aligned manner by using the source region 24a doped with a high concentration of impurities.
And the drain region 24b. On the other hand, in the present embodiment, the low concentration impurity regions 25a,
25b (herein, referred to as “LDD region”) are self-aligned with the gate electrode 30 and are formed opposite to each other. Further, a predetermined distance from the LDD regions 25a and 25b to the outside of the gate electrode 30 is provided, and the high concentration impurity region 2
3a and 23b are arranged. Then, these high-concentration impurity regions 23a, 23b and LDD regions 25a, 25
b, the source region 24a and the drain region 24b
Are respectively constituted.

Therefore, as shown in FIGS. 6B and 6C, the lower end of the gate electrode 30 is partially insulated above both ends of the channel region 26 in contact with both LDD regions 25a and 25b. Localized insulation parts 30a, 3 formed
0b is formed. The local insulating portions 30a, 30
The details of b and the method of forming it are the same as those in the first embodiment.

An n-channel MOS having such an LDD structure
As in the first embodiment, a field oxide film 22 is formed on a semiconductor substrate 20, a gate oxide film 28 is formed, and a gate electrode 30 is formed thereon. Then, as shown in FIG. 7, the formed gate electrode 3
Using 0 as a mask, LDD regions 25a and 25b are formed by ion implantation.

Next, in the present embodiment, the gate electrode 30
A side wall spacer layer (side wall 40) is formed on the side wall. To form the side wall 40, first, a side wall constituent material made of a silicon nitride film or the like is formed,
Anisotropic etching such as RIE (Reactive Ion Etching) is performed from this surface. By this anisotropic etching, a silicon nitride film or the like is left only on the side wall of the gate electrode 30, thereby forming a sidewall.
Is formed.

Then, as shown in FIG. 7, the high-concentration impurity regions 23a and 23b are self-aligned by ion implantation using the formed sidewall 40, field oxide film 22, and gate electrode 30 as a mask. Formed relative to As a source for ion implantation, for example, As
Ions can be used, and then heat treatment for electrically activating the implanted ions is performed in the same manner as in the first embodiment. As a result, the source region 24a and the drain region 24b respectively formed from the high-concentration impurity regions 23a and 23b and the LDD regions 25a and 25b as low-concentration impurity regions are formed to face each other. Of the source region 24a and the drain region 24b, the surface of the active region sandwiched between the LDD regions 25a and 25b becomes the channel region 26, particularly in the present embodiment.

Next, as shown in FIG. 8, only the side wall 40 is selectively removed with respect to the gate oxide film 28, and both lower ends of the gate electrode 30 exposed on the surface are removed by the first step.
Insulation is locally performed in the same manner as in the embodiment. Thereafter, although not particularly shown, as in the first embodiment, a gate oxide film etch-off step (see FIG. 4), an interlayer insulating film 3
After the deposition of the second electrode 2 and the step of opening the contact hole 32a (see FIG. 5), as shown in FIG.
Then, the wiring of the drain electrode 34b is completed, and the manufacturing process of the MOSFET having the LDD structure ends.

According to the LDD structure n-channel MOSFET according to the second embodiment described above, the same effects as those of the first embodiment can be obtained. In particular, in the present embodiment, it is desirable to set the heating condition in the local insulating step, which is a feature of the present invention, to a range in which the rearrangement does not occur in the impurities in the lower impurity region. This is because, in the case of the present embodiment, the impurity regions on the lower layer side, which are locally heated by laser light or the like for local insulation, have low impurity concentrations and are relatively shallow LDD regions 25a, 25b.
Therefore, it is considered that the rearrangement of the impurities is more likely to occur than in the first embodiment.

The matters other than those mentioned in the description of the present embodiment are not particularly limited, and can be variously changed within the scope of the present invention. For example, as described above, when the heating conditions in the local insulating step can be set within a range that does not cause rearrangement of impurities, before the formation of the sidewalls 40 and the high-concentration impurity regions 23a and 23b in FIG.
After the LDD regions 25a and 25b are formed using the mask as a mask and before the activation annealing, laser beam irradiation for local insulation may be performed to form the local insulating portions 30a and 30b. In this case, it is not necessary to remove the sidewall 40 to the end, and it is not necessary to provide the constituent film material with selectivity to the gate oxide film 28.
Can be constituted by a silicon oxide film or the like, and there is an advantage that a material selection range is wide.

In the first and second embodiments, the case where the n-channel MOSFET is used has been described. However, it goes without saying that the present invention can be applied to the p-channel MOSFET. The present invention also provides various MISFETs using other gate insulating films instead of the gate oxide films 28.
Also applicable to

[0043]

As described above in detail, according to the semiconductor device of the present invention, in the MISFET, the gate insulation is provided between both ends of the channel region in contact with the source region and the drain region and the gate electrode. The formation of the local insulating portion in which the lower end portion of the gate electrode on the film is locally insulated causes the reverse short channel effect to occur intentionally. Therefore, the short-channel effect and the inverse short-channel effect based on the shortened gate length can be counterbalanced with each other, and as a result, the MISFE having a small variation in the threshold voltage with the shortened gate length.
T can be realized.

Further, in an LSI in which MISFETs having different gate lengths are mixedly mounted, it is possible to suppress fluctuations in the threshold voltage of each transistor having a different gate length and to achieve desired characteristics in circuit design. . Further, between both ends of the channel region and both lower ends of the gate electrode,
Since an insulating film having a thickness greater than that of the gate insulating film intervenes, the concentration of the electric field on the lower surface of the end of the gate electrode is reduced, so that the reliability of the MISFET can be improved.

On the other hand, according to the method of manufacturing a semiconductor device according to the present invention, only a step of locally insulating the lower end of the gate electrode is added to the normal MISFET manufacturing process. Since there is no need for an additional photolithography process using a photomask, the time and cost required for manufacture are almost the same as in the conventional case, except for this local insulating process. An MISFET having an LDD structure with little voltage fluctuation can be easily manufactured at low cost.

As described above, according to the present invention, MISFE can be realized without deteriorating characteristics and reliability and significantly increasing costs.
The gate length of T can be further reduced, and this is expected to greatly contribute to higher integration and higher performance of a semiconductor device having a MISFET.

[Brief description of the drawings]

FIG. 1 is an n-channel MO according to a first embodiment of the present invention.
1A is a cross-sectional view, FIG. 1B is a partially enlarged view, and FIG. 1C is a main part dimensional diagram.

FIG. 2 is a schematic cross-sectional view showing a manufacturing process of the MOSFET of FIG. 1, particularly showing a stage after formation of source / drain regions.

FIG. 3 is a schematic cross-sectional view, particularly showing a laser beam irradiation stage in a local insulating process.

FIG. 4 is a schematic cross-sectional view, particularly showing a stage after etching off a gate insulating film around a gate electrode.

FIG. 5 is a schematic cross-sectional view, particularly showing a stage after opening a contact hole in an interlayer insulating film.

FIG. 6 schematically shows an n-channel MOSFET having an LDD structure according to a second embodiment of the present invention, and FIG.
1 is a sectional view, FIG. 1B is a partially enlarged view, and FIG. 1C is a main part dimensional view.

FIG. 7 is a schematic cross-sectional view showing a manufacturing process of the MOSFET of FIG. 6, particularly showing a stage after formation of source / drain regions.

FIG. 8 is a schematic sectional view, particularly showing a laser beam irradiation step in a local insulating step.

FIG. 9 is a diagram for explaining the inverse short channel effect, and FIG.
Is a schematic diagram, and FIG. 4B is a diagram showing a simulation result.

[Explanation of symbols]

20: semiconductor substrate, 22: field oxide film, 23a,
23b: high concentration impurity region, 24a: source region, 24
b: drain region, 25a, 25b: LDD region (low concentration impurity region), 26: channel region, 28: gate oxide film (gate insulating film), 30: gate electrode, 30a, 3
0b: Local insulating portion, 32: interlayer insulating film, 32a: contact hole, 34a: source electrode, 34b: drain electrode, 40: sidewall (insulating spacer), Δx:
Width in the gate length direction of the local insulating portion, Δy: maximum thickness of the local insulating portion, t: thickness of the gate oxide film (gate insulating film), W: width of the overlapping portion between the source / drain region and the gate electrode width.

Claims (6)

[Claims] A semiconductor substrate, a source region and a drain region formed on the semiconductor substrate at a distance from each other, and a channel region formed between the source region and the drain region via a gate insulating film. A semiconductor device comprising: a gate electrode; and a local insulating portion at a lower end of the gate electrode facing the source region or the drain region through the gate insulating film with respect to both ends of the channel region. A semiconductor device in which is formed. 2. The source region and the drain region each include a high-concentration impurity region and a low-concentration impurity region, and at both ends of the channel region facing the local insulating portion,
2. The semiconductor device according to claim 1, wherein the low-concentration impurity regions of the source region and the drain region are provided adjacent to each other. 3. A gate electrode is formed on a semiconductor substrate with a gate insulating film interposed therebetween, and impurities are introduced into the semiconductor substrate using the gate electrode as a mask to form a source region and a drain region at a distance from each other. A local insulating portion is formed by partially insulating the gate electrode at the lower end of the gate electrode facing the both ends of the channel region sandwiched between the source region and the drain region via the gate insulating film. Semiconductor device manufacturing method. 4. When forming the source region and the drain region, an impurity is introduced into a semiconductor substrate using the gate electrode as a mask to form low-concentration impurity regions at a distance from each other. 4. The method of manufacturing a semiconductor device according to claim 3, wherein after forming insulating spacers on both side walls on the side of the impurity region, impurities are introduced into the semiconductor substrate using the insulating spacer as a mask to form a high-concentration impurity region. 5. The method according to claim 1, wherein, when forming the local insulating portion, a lower end of the gate electrode on the gate insulating film is locally thermally oxidized from outside the gate electrode to above both ends of the channel region. Item 4. The method for manufacturing a semiconductor device according to Item 3. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the heating condition of the local thermal oxidation is set within a range in which rearrangement of impurities in the source region and the drain region does not occur.