JPH10341239A - Multi-bit rate serial atm channel reception circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To configure the circuit such that a selector is automatically selected by forming two kinds of subscriber packages for 155 Mbps and 622 Mbps as one subscriber package. SOLUTION: The circuit has two ATM reception circuits for 155 Mbps and 622 Mbps, two clock extract circuits F01, F04 for 155 MHz and 622 MHz clock signals extract received serial data, data re-timing circuits F02, F05 apply data re-timing to the data. Then header error control HEC detection circuits F03, F06 extract HEC data to check and correct a header error included in a cell header respectively and a 155 MHz/622 MHz discrimination circuit F08 selects a selector F09 so that the received serial data detecting continuously the HEC data are sent to post-stage circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving ATM (A
synchronous transfer mode) ATM serial data communication system that extracts data and clock from serial data line, especially multi-bit rate serial AT
It relates to an M line receiving circuit.

[0002]

2. Description of the Related Art There are multi-bit rate serial ATM line receiving circuits for 155 Mbps and 622 Mbps. Conventional ATM line receiving circuits are designed exclusively for each line speed, and each individual ATM line receiving circuit is individually designed. It is configured as a circuit.

[0003]

Therefore, the conventional AT
M line receiving circuit is 155Mbps line and 622Mbps
When changing the line speed because the lines cannot be accommodated in a mixed manner, it was necessary to replace the ATM line receiving circuit.

[0004] The present invention is for 155 Mbps and 622 Mbps
By combining two types of subscriber packages for ps into one subscriber package and automatically changing the line speed based on received data, 155
It is an object of the present invention to distinguish between the Mbps and 622 Mbps ATM serial data lines, and to eliminate the need to replace the ATM line receiving circuit when changing the line speed.

[0005]

According to the multi-bit rate serial ATM line receiving circuit of the present invention, 155 Mbps is used.
And two ATM receiver circuits for 622 Mbps,
155MHz and 622MHz received serial data
After extracting with the two clock extraction circuits, perform data retiming, and use the HEC detection circuit to detect and correct errors in the header included in the cell header, `` Header Error Control (Header Error Control) '' (Hereinafter referred to as HEC) is provided with a switching means for transmitting received serial data on the side where data is continuously detected to a subsequent circuit.

More specifically, a 155 MHz clock extraction circuit for extracting a 155 MHz clock from the reception serial data line, a 155 MHz data retiming circuit for retiming the reception serial data with the 155 MHz clock extracted from the 155 MHz clock extraction circuit, An HEC detection circuit (155M) for searching for HEC data from the serial data string retimed by the 155MHz data retiming circuit, and a 622M clock for extracting a 622MHz clock from the reception serial data line.
Hz clock extraction circuit, a 622 MHz data retiming circuit for retiming the received serial data with the 622 MHz clock extracted from the 622 MHz clock extraction circuit, and HEC data from the serial data sequence retimed by the 622 MHz data retiming circuit. A HEC detection circuit (622M) for searching for the data and a HEC detection circuit (155M) and a HEC detection result from the HEC detection circuit (622M) determine whether the received serial data line is 155 Mbps or 622 Mbps. It has a 155M / 622M discriminating circuit and a selector for switching data / clock to be sent to a subsequent circuit according to the discrimination result from the 155M / 622M discriminating circuit.

[0007]

FIG. 1 is a block diagram showing a multi-bit-rate serial ATM line receiving circuit according to the present invention.

[0008] The present invention provides a method for receiving 1
155 MHz clock extraction circuit F01 for extracting the 55 MHz clock, and 155 MHz clock extraction circuit F01
A 155 MHz data retiming circuit F02 for retiming the received serial data S01 with a 155 MHz clock extracted from the HEC detection circuit (155M) that searches for the HEC data S05 from the serial data string retimed by the 155 MHz data retiming circuit F02. ) F03 and 6 from received serial data line
A 622 MHz clock extraction circuit F04 for extracting a 22 MHz clock, and a 622 MHz clock extraction circuit F04
622 MHz data retiming circuit F05 for retiming the received serial data S01 with the 622 MHz clock extracted from the 622 MHz clock, and an HEC detection circuit (622M ) F06 and HEC detection circuit (155M) F
03 and HE from the HEC detection circuit (622M) F06
Based on the C detection result, the received serial data line
A 155M / 622M discriminating circuit F08 for discriminating between Mbps and 622Mbps, and 155M / 62
It is configured by a selector F09 that switches data / clock to be sent to a subsequent circuit according to the determination result from the 2M determination circuit F08.

Next, the operation of the present invention will be described with reference to FIG. 155 MHz clock extraction circuit F01
Performs a 155 MHz clock extraction process from the received ATM serial data line, and extracts the 155 MHz clock S0.
2 is output. The method of clock extraction is the same as that of a general DPL circuit. Here, the received ATM serial data S0
If 1 is 622 MHz, the 155 MHz clock extraction circuit F01 may malfunction or operate erratically, but it does not matter.

155 MHz data retiming circuit F0
2 is the reception ATM at the extraction 155 MHz clock S02
ATM serial data S received from serial data line
01 is retimed and a 155 MHz clock S03 and data S04 are output. HEC detection circuit (155M)
F03 is a 155 MHz clock S03 and data S04
The HEC data of the ATM cell is searched from the above, and if it is detected, the fact is detected as a detection signal (155M) S05.
It notifies the 5M / 622M discriminating circuit F08.

At this time, if the received ATM serial data line is 155M, HEC data is detected for each ATM cell length, but if the received ATM serial data line is 622M, a coincidence occurs. , The HEC data may be detected sporadically, but the HEC data is not detected for each ATM cell length.

The 622 MHz clock extraction circuit F04 is
A 622 MHz clock extraction process is performed from the received ATM serial data line, and an extracted 622 MHz clock S06 is output. The method of clock extraction is the same as that of a general DPL circuit. If the received ATM serial data S01 is 155 MHz, the 622 MHz clock extraction circuit F04 may malfunction or operate erratically, but this is not a problem.

622 MHz data retiming circuit F0
5 is a reception ATM at the extraction 622 MHz clock S06.
ATM serial data S received from serial data line
01 is retimed to output a 622 MHz clock S07 and data S08. HEC detection circuit (622M)
F06 is composed of a 622 MHz clock S07 and data S08.
The HEC data of the ATM cell is searched from the above.
It notifies the 5M / 622M discriminating circuit F08.

At this time, if the received ATM serial data line is 622M, HEC data is detected for each ATM cell length, but if the received ATM serial data line is 155M, an accidental match is detected. , The HEC data may be detected sporadically, but the HEC data is not detected for each ATM cell length.

The 155M / 622M discriminating circuit F08 is
The detection signal (15M) from the EC detection circuit (155M) F03
5M) S05 and the detection signal (622M) S09 from the HEC detection circuit (622M) F06 are monitored.
A select signal S10 validating the side to which the C data is continuously input is input to the selector F09.

The selector F09 outputs a signal 155M based on the select signal from the 155M / 622M discriminating circuit F08.
Hz clock S03 and data S04 or 622 MHz
One of the clock S07 and the data S08 is switched so as to be transmitted to a subsequent circuit as the clock S11 and the data S12.

As an embodiment of the present invention, 155
Although the multi-bit rate serial ATM line receiving circuits for Mbps and 622 Mbps have been described, the present invention generally relates to a multi-bit rate serial A in which serial ATM signals of a plurality of bit rates different from each other are mixed.
It can be applied to a TM line receiving circuit.

[0018]

According to the present invention, for 155 Mbps and 6
Since two types of subscriber packages for 22 Mbps are shared by one, the subscribers can change from 155 Mbps to 622 Mbps.
bps, or 622Mbps to 155Mbps
There is no need to change the subscriber package even if the service is changed.

Also, when a spare package is stored in a station building or the like in case of a failure or the like, it can be used for 155 Mbps and 622 Mbps.
There is no need to prepare two types of subscriber packages for ps, and only one type is required, so that there is an advantage that management is easy.

[0020]

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 F01 155 MHz clock extraction circuit F02 155 MHz data retiming circuit F03 HEC detection circuit (155M) F04 622 MHz clock extraction circuit F05 622 MHz data retiming circuit F06 HEC detection circuit (622M) F08 155M / 622M discrimination circuit F09 selector S01 ATM extracted data S02 155 MHz clock S03 155 MHz clock S04 data S05 detection signal (155M) S06 extraction 622 MHz clock S07 622 MHz clock S08 data S09 detection signal (622M) S10 select signal S11 clock S12 data

Claims (3)

[Claims] 1. A receiving circuit for an ATM serial data line, comprising: a plurality of clock extracting circuits for respectively extracting clocks having different bit rates from the receiving serial data line; and a clock of each frequency extracted from each of the clock extracting circuits. A plurality of data retiming circuits for respectively retiming the received serial data; a plurality of HEC detection circuits for respectively searching for HEC data from each serial data sequence retimed by the data retiming circuits; A bit rate discriminating circuit for receiving the HEC detection result from the circuit and discriminating which bit rate the received serial data line is; Having a selector to switch between Characteristic multi-bit rate serial ATM line receiving circuit. 2. The method according to claim 2, wherein the bit rate determination circuit is configured to control the HE.
2. The multi-bit rate serial ATM line receiving circuit according to claim 1, wherein said selector is switched so as to transmit received serial data on the side where C data is continuously detected to a subsequent circuit. 3. A receiving circuit for an ATM serial data line, comprising: a 155 MHz clock extracting circuit for extracting a 155 MHz clock from the receiving serial data line;
155MH extracted from 55MHz clock extraction circuit
Retiming of received serial data with z clock 1
55MHz data retiming circuit and 155MHz
First HEC for searching for HEC data from a serial data string retimed by a data retiming circuit
622MHz from detection circuit and reception serial data line
A 622 MHz clock extraction circuit for extracting a clock,
622 extracted from the 622 MHz clock extraction circuit
A 622 MHz data retiming circuit for retiming received serial data with a MHz clock;
The second H that searches for HEC data from the serial data sequence retimed by the Hz data retiming circuit
An EC detection circuit; a 155M / 622M discrimination circuit that receives the HEC detection results from the first and second HEC detection circuits and discriminates whether the received serial data line is 155 Mbps or 622 Mbps;
A selector for switching data / clock to be sent to a subsequent circuit according to a result of the determination from the 622M determination circuit.