JPH103409A - Microcomputer monitor system and semiconductor integrated circuit device used for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide technology for constituting a microcomputer monitor system whose constitution is made simple, which outputs a rest signal to a microcomputer and outputs a mask signal for masking the output of the microcomputer. SOLUTION: Monitor IC 4 provided with a function for judging whether the output of the microcomputer 2 is normal or abnormal, outputting the reset signal to the microcomputer 2 and outputting the mask signal SM when it is judged to be abnormal is connected to the microcomputer 2. When monitor IC 4 judges the output of the microcomputer 2 to be abnormal, it outputs the reset signal SR to the microcomputer 2, masks the output of the microcomputer 2 with the mask signal and stops the output of the microcomputer 2. Since the reset signal SR and the mask signal SM can be outputted by using one monitor IC 4, cost can be reduced at the time of constituting the microcomputer monitor system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer monitoring system and a semiconductor integrated circuit device used for the same, and more particularly to a technique which is effective when applied to a system for stopping the output of the microcomputer when the microcomputer is abnormal.

[0002]

2. Description of the Related Art Microcomputers having various functions (hereinafter simply referred to as microcomputers) are widely used as control elements for controlling a desired load. As an example, it is used for an electronic device for engine control in a car.

[0003] Since such a microcomputer is an ultra-high performance electronic component, it has a property of easily malfunctioning according to the use environment. For example, a phenomenon that a malfunction occurs due to sudden runaway due to radio wave interference rarely occurs. If such a runaway occurs in, for example, a microcomputer used in an engine control electronic device, the car may suddenly start or accelerate rapidly against the driver's will, which may lead to a major accident. Very dangerous. Therefore, care must be taken to minimize malfunctions of the microcomputer.

[0004] From such a viewpoint, the operation of the microcomputer is constantly monitored, and when the output is determined to be abnormal, the microcomputer is regarded as malfunctioning and a reset signal is output to the microcomputer to normalize the microcomputer. IC that works to return to the state, so-called Watch Dog Timer
(Watch Dog Timer; hereinafter simply referred to as WDT) ICs have been developed. Such a WDT is, for example, sold by Hitachi, Ltd. under the product name HA16103. Such a WDT is connected to a microcomputer to form a microcomputer monitoring system.

[0005] By the way, such a WDT has a function of detecting a malfunction of the microcomputer due to runaway and outputting a reset signal to the microcomputer, but the output becomes undefined when the microcomputer runs away. So that alone is not enough. Therefore, it is necessary not only to output a reset signal to the microcomputer but also to output a mask signal for masking the output of the microcomputer and completely stopping the output of the microcomputer.

Conventionally, a function of outputting a mask signal is provided by using another IC such as a gate array in addition to the WDT, or by using a sub-microcomputer.

[0007]

In order to output a mask signal for masking the output of the microcomputer as well as to output the reset signal to the microcomputer,
The use of another IC such as a gate array in addition to the DT or the configuration of a microcomputer monitoring system using a sub-microcomputer complicates the configuration of the system, resulting in an increase in cost.

Further, the use of extra components such as another IC or sub-microcomputer also causes a disadvantage that the potential for failure increases.

An object of the present invention is to provide a microcomputer monitoring system which simplifies the system configuration, outputs a reset signal to the microcomputer, and outputs a mask signal for masking the output of the microcomputer. It is to provide a possible technology.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows.

(1) The microcomputer monitoring system of the present invention constantly monitors the operation of the microcomputer for controlling a desired load, and stops the output of the microcomputer when an abnormality is detected. A system, comprising: determining whether the output of the microcomputer is normal or abnormal; connecting the semiconductor integrated circuit device having a function of outputting a mask signal together with a reset signal to the microcomputer when the output is determined to be abnormal; When the semiconductor integrated circuit device determines that the output of the microcomputer is abnormal, the reset signal is output to the microcomputer, and the output of the microcomputer is stopped by masking the output of the microcomputer with the mask signal.

(2) The semiconductor integrated circuit device used in the microcomputer monitoring system of the present invention is a semiconductor integrated circuit device which is connected to a microcomputer and which constantly monitors its operation by inputting its output. When it is determined that the output of the microcomputer is abnormal, the microcomputer has a function of outputting a reset signal to the microcomputer and outputting a mask signal for masking the output of the microcomputer.

(3) The semiconductor integrated circuit device used in the microcomputer monitoring system of the present invention is a semiconductor integrated circuit device which is connected to a microcomputer and constantly monitors its operation by inputting its output. Inputs the output of the computer and generates a regular or irregular triangular wave signal according to the pulse width, and outputs a signal of a predetermined level only when the level of the triangular wave signal is within two reference potential ranges. A watch dog timer unit, which receives the output of the watch dog timer unit and generates a triangular wave signal whose peak rises or falls according to the duration of the signal of the predetermined level,
A reset unit that outputs a reset signal that alternates between HL and L in accordance with the level of the triangular wave signal; and a mask signal output unit that receives an output of the reset unit and outputs a mask signal at the output timing of the reset signal. And

According to the above-mentioned means (1), the microcomputer monitoring system of the present invention determines whether the output of the microcomputer is normal or abnormal, and outputs a mask signal together with a reset signal when it is determined that the output is abnormal. When a semiconductor integrated circuit device having a function is connected to the microcomputer, and the semiconductor integrated circuit device determines that the output of the microcomputer is abnormal, the semiconductor integrated circuit device outputs the reset signal to the microcomputer, and outputs the reset signal to the microcomputer. A microcomputer that stops the output of the microcomputer by masking the output of the computer, thereby simplifying the system configuration, outputting a reset signal to the microcomputer, and outputting a mask signal that masks the output of the microcomputer. Monitoring system It is possible to configure the Temu.

According to the above-mentioned means (2), the semiconductor integrated circuit device used in the microcomputer monitoring system of the present invention is a semiconductor integrated circuit device which is connected to a microcomputer and inputs its output to constantly monitor its operation. The integrated circuit device has a function of outputting a mask signal together with a reset signal to the microcomputer when it is determined that the output of the microcomputer is abnormal. A microcomputer monitoring system is configured to output a reset signal to the microcomputer and output a mask signal for masking the output of the microcomputer by configuring the microcomputer monitoring system by using the microcomputer monitoring system. It is possible to It made.

According to the above-mentioned means (3), in the semiconductor integrated circuit device used in the microcomputer monitoring system of the present invention, the watch dog timer section inputs the output of the microcomputer and adjusts the pulse width thereof. A regular or irregular triangular wave signal is generated in response to the signal, and a signal is output according to the level of the triangular wave signal. The reset unit receives an output of the watch dog timer unit, generates a triangular wave signal whose peak rises or falls according to the duration of the signal of the predetermined level, and outputs HL in accordance with the level of this triangular wave. The reset signal which changes alternately is output. The mask signal output unit receives the output of the reset unit and outputs a mask signal at the output timing of the reset signal. Therefore, by configuring a microcomputer monitoring system using such a semiconductor integrated circuit device, the configuration of the system is simplified, a reset signal is output to the microcomputer, and a mask for masking the output of the microcomputer is provided. It is possible to configure a microcomputer monitoring system that outputs a signal.

Hereinafter, the present invention will be described in detail with embodiments with reference to the drawings.

In all the drawings for describing the embodiments, parts having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment) FIG. 1 is a block diagram showing a configuration of a microcomputer (microcomputer) monitoring system according to the present embodiment. The microcomputer monitoring system 1 according to the present embodiment includes:
Basically, the microcomputer 2 and a load 3 controlled by the microcomputer 2 such as an electronic device for engine control.
And a monitoring semiconductor integrated circuit device (hereinafter, simply referred to as a monitoring IC) 4 that constantly monitors the operation of the microcomputer 2. Q is a driving transistor for driving the load 3, and 5 is an AND gate for controlling the driving transistor Q.

The monitoring IC 4 constantly monitors the operation of the microcomputer 2 by inputting the output of the microcomputer 2. The monitoring IC 4 determines whether the output of the microcomputer 2 is normal or abnormal, and when it determines that the output is abnormal, outputs a reset signal SR to the microcomputer 2 and a mask signal SM for stopping the output of the microcomputer 2. Output function. To determine whether the output of the microcomputer 2 is normal or abnormal, the pulse width of the output is monitored, and if the fluctuation is out of the normal range due to severe fluctuation, it is determined that the microcomputer is abnormal.

FIG. 2 shows a specific circuit configuration of the monitoring IC 4. The monitoring IC 4 includes a WDT unit 6 that monitors the output of the microcomputer 2, a reset unit 7 that outputs a reset signal SR to the microcomputer 2 when the output of the microcomputer 2 is abnormal based on the output of the WDT unit 6, When the output is abnormal, the mask signal output section 8 outputs a mask signal SM. The WDT unit 6 and the reset unit 7 are connected by an OR gate 12. V
cc is a power supply, and R1 to R4 are resistors. This monitoring IC
4 is a conventional WDT comprising a WDT unit 6 and a reset unit 7
A new mask signal output unit 8
Has been added.

The WDT section 6 receives the output of the microcomputer 2 from the terminal T1 and controls the first transistor Q1 controlled by this signal, the second transistor Q2 connected in series to the first transistor Q1, and the first constant current A source I1, a first comparator 9 and a second comparator 10, and an AND gate 1 for inputting both outputs of the first and second comparators 9 and 10;
And 1. Further, a first capacitor CW is externally connected to the first constant current source I1.

When the output of the microcomputer 2 input from the terminal T1 is at a high level, the first capacitor CW is charged by the constant current source I1, and the output of the first capacitor CW is low. ) Level, it is discharged by the transistor Q2 and acts to oscillate a triangular wave signal.

The minus terminal of the first comparator 9 and the plus terminal of the second comparator 10 are both connected to the first capacitor C.
W to receive the triangular wave signal. On the other hand, the + terminal of the first comparator 9 is connected to the reference potential V1 ′, and the − terminal of the second comparator 10 is connected to the reference potential V1 (V1 ′> V1). These first and second comparators 9 and 10 constitute a so-called window comparator, and only when the magnitude of the triangular wave signal input from the first capacitor CW is between V1 and V1 ', is the AND gate. 11 outputs an H level. The output from this AND gate 11 is OR gate 12
The switch SW is turned off (closed) through.

The reset unit 7 includes a switch SW whose opening and closing operation is controlled by the output of the AND gate 11 of the WDT unit 6 input through the OR gate 12, a second constant current source I2 connected in series through the switch SW, It comprises a third constant current source I3 (I2 <I3), a third comparator 13, and a third transistor Q3. Part of the output of the third comparator 13 is connected to the input of the OR gate 12 through the first inverter IV1. A second capacitor CW is externally connected to the second constant current source I2.

The second capacitor CR is charged by the second constant current source I2, and when the switch SW is turned on, the current I by the second and third constant current sources I2 and I3 is charged.
It is discharged by 2 to I3 and works to oscillate a triangular wave signal.

The + terminal of the third comparator 13 is connected to the second capacitor CR, and the-terminal of the third comparator 13 is connected to the third transistor Q3 through the resistor R4. The resistor R4 is connected in parallel with the resistor R3. Thereby, the third comparator 13
Are reference potentials V2, V2 '(V2 <
V2 ') to form a hysteresis comparator which takes two values. That is, when the transistor Q3 is off, V2 'is taken, and when the transistor Q3 is on, the resistors R3 and R4 are connected in parallel to take V2.

When there is no input from the microcomputer 2 to the terminal T1, the second capacitor CR oscillates a regular triangular wave signal.
And a reset signal SR is output from the terminal T2 to the microcomputer 2.

Here, when a normal output is input from the microcomputer 2 to the terminal T1, the time during which the output from the WDT unit 6 becomes H level becomes longer (the OFF time of the switch SW becomes longer). The potential of the second capacitor CR is charged and rises. Therefore, the output of the third comparator 13 is kept at the H level.

When the microcomputer 2 runs away and an abnormal output is input from the microcomputer 2 to the terminal T1, the off time of the switch SW of the reset unit 7 is shortened.
Is discharged and the potential of the capacitor CR is lowered, so that the reset signal SR is output from the terminal T2.

The mask signal output section 8 comprises a fourth comparator 14 and a latch circuit 15 connected thereto.

The + terminal of the fourth comparator 14 is connected to the second capacitor CR, and the-terminal is connected to the reference potential V3 (V3> V2 ').

The R (reset) terminal of the latch circuit 15 is connected to the output side of the fourth comparator 14,
The S (set) terminal is connected to the output side of the third comparator 13 of the reset unit 7 through the second inverter IV2.

The latch circuit 15 functions so as to hold the input signal for a desired time, so that when the output of the microcomputer 2 becomes abnormal, it can be detected accurately.

When the reset signal input to the R terminal of the latch circuit 15 is at L level, the latch circuit 15 is latched and outputs an L level signal from the inverted Q terminal. On the other hand, when the potential of the second capacitor CW becomes higher than the reference potential V3, the latch circuit 15 is reset and outputs an H level signal from the inverted Q terminal. The output from the inverted Q terminal of the latch circuit 15 is used as a mask signal SM at the terminal T3.
Is output to the AND gate 5 in FIG.
Mask the output of

Next, the operation of the microcomputer monitoring system 1 according to the present embodiment will be described with reference to the timing charts of FIGS. Microcomputer 2 to be monitored
However, (1) at the time of non-operation, (2) at the time of normal operation, and (3) at the time of abnormal operation will be sequentially described in three ways.

(1) When the microcomputer is not operating As shown in FIG. 3, since there is no output SP of the microcomputer of (a), there is no input to the terminal T1 of the monitoring IC 4, so that WD
The transistor Q1 of the T section 6 turns off and the transistor Q2 turns on. As a result, the output of the first capacitor CW in FIG.

Further, the switch SW of the reset unit 8 is turned on, and the second capacitor CR is connected to V
Since a regular triangular wave signal of 2'-V2 is oscillated, the third
The comparator 13 generates a regular HL pulse and outputs a regular reset signal SR as shown in (d) to the microcomputer 2 from the terminal T2.

Further, since the potential of the second capacitor CR is kept below the reference potential V3, the mask signal portion 8
Latch circuit 15 outputs an L-level reset signal S to the R terminal.
Since R is input, it is latched and outputs an L level mask signal SM as shown in (e).

(2) When the microcomputer operates normally As shown in FIG. 4, the output of the microcomputer shown in (a) becomes regular HL pulses and is inputted to the terminal T1 of the monitoring IC 4. As a result, the transistor Q1 of the WDT unit 6
Turns on and off, and the transistor Q2 turns off and on.
The first capacitor CW outputs a regular triangular wave signal having a peak at the reference potential V1 'as shown in FIG.

The second capacitor C of the reset unit 7
The potential of R rises because it takes a long time to be at the H level in the output from the WDT unit 6, so that the second capacitor CR is charged as shown in (c).
A triangular wave signal whose peak gradually rises is output. As a result, the third comparator 13 sets the second capacitor C
At the timing when the output (c) of R rises to the reference potential V2 ', a reset signal SR as shown in (d) in which the L level has risen to the H level is generated, and the terminal T2
To the microcomputer 2.

Further, at the timing when the output (c) of the second capacitor CR rises to the reference potential V3, the latch circuit 15 of the mask signal output section 8 changes the L level up to that time to H.
A mask signal SM as shown in (e) rising to the level is generated and output from the terminal T3.

(3) Abnormal operation of the microcomputer As shown in FIG. 5, the output of the microcomputer in (a) is an irregular HL pulse, that is, a pulse whose width fluctuates with time. Then, it is inputted to the terminal T1 of the monitoring IC4. As a result, the transistors Q1 and Q
2 is turned on and off at irregular intervals, and the first capacitor CW outputs a triangular wave signal as shown in (b), which has a peak proportional to the pulse width in the output SP of the microcomputer 2 in (a). .

The first capacitor CW shown in FIG.
The triangular wave signal sequence does not have a regular waveform like the triangular wave signal shown in FIG. 4B, and the output S shown in FIG.
The frequency changes according to the pulse width of P. That is, assuming that the section A of the pulse train in FIG. 4A is normal, the triangular wave signal S1 corresponding to the pulse P1 in this section A has a frequency corresponding to the triangular wave signal in FIG. 4B. Next, assuming that section B of the pulse train in (a) is an output having a large pulse width, the pulse P in this section B is output.
2, the triangular wave signals S2 and S3 corresponding to P3 are signals having large peaks and signals having low frequencies. continue,
Assuming that the section C of the pulse train in (a) is an output having a small pulse width, the triangular wave signals S4, S5, S6... Corresponding to the pulses P4, P5, P6. Becomes

That is, by monitoring the frequency of the triangular wave signal corresponding to the pulse train output from the microcomputer 2, if the signal has a pulse width larger or smaller than that of the normal pulse train, the signal of the microcomputer 2 The output can be determined to be abnormal, and the microcomputer 2 can be considered to have run away.

The second capacitor C of the reset unit 7
Since the time during which the potential of R becomes the H level in the output from the WDT unit 6 is shortened, the potential of R is reduced by discharging, so that the second capacitor CR is set as shown in (c).
The peak gradually decreases, and a stable triangular wave signal is output at a level having the peak at the reference potential V2 '. This allows
At the timing when the output (c) of the second capacitor CR drops to the reference potential V2, the third comparator 13 generates a reset signal SR as shown in (d) in which the previous H level has dropped to the L level. Then, the signal is output from the terminal T2 to the microcomputer 2.

Further, at the same time, the latch circuit 15 of the mask signal output section 8 outputs the reset signal SR of (d) which is the output of the third comparator 13 first to the H level.
At the timing when the level falls to the L level, a mask signal SM as shown in (e) in which the H level has risen to the L level up to that time is generated and output from the terminal T3 to the AND gate 5.

As described above, while the reset signal SR shown in FIG. 5D is output from the terminal T2 to the microcomputer 2,
When the mask signal SM shown in FIG. 5E is output from the terminal T3 to the AND gate 5, the operation of the microcomputer 2 is stopped by the function of the AND gate 5. As a result, in order to output the mask signal as well as the reset signal to the microcomputer as in the conventional case, another IC such as a gate array is used in addition to the WDT, or the microcomputer monitoring system is configured using a sub-microcomputer. It becomes unnecessary to do. Accordingly, the configuration of the system is simplified, and an increase in cost can be avoided. Another I
By not using extra components such as C and sub-microcomputer, there is no inconvenience that the potential for failure increases.

According to the microcomputer monitoring system 1 of the present embodiment as described above, the following effects can be obtained.

(1) It is determined whether the output of the microcomputer 2 is normal or abnormal. If the output is determined to be abnormal, a monitoring signal having a function of outputting a reset signal SR to the microcomputer 2 and outputting a mask signal SM is provided. When the IC 4 is connected to the microcomputer 2 and the monitoring IC 4 determines that the output of the microcomputer 2 is abnormal, the microcomputer 4 outputs the reset signal SR to the microcomputer 2 and masks the output of the microcomputer 2 with the mask signal SM. Since the output of the microcomputer 2 is stopped, the configuration of the system can be simplified, and a microcomputer monitoring system that outputs a reset signal to the microcomputer and outputs a mask signal for masking the output of the microcomputer can be configured.

(2) When the output of the microcomputer 2 is determined to be abnormal, a function of outputting a reset signal SR to the microcomputer 2 and outputting a mask signal SM for masking the output of the microcomputer 2 is provided. Since the microcomputer monitoring system 1 is configured by using the monitoring IC 4, the configuration of the system can be simplified, so that the cost can be reduced.

As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

For example, in the above-described embodiment, the logic levels of various signals are shown by way of example. However, the present invention is not limited to this, and can be set to any logic level. For example, although the mask signal for stopping the operation of the microcomputer has been described as being set at the L level, the mask signal may be set at the H level.

In the above description, the case where the invention made by the present inventor is mainly applied to a microcomputer monitoring system, which is the field of application as the background, has been described, but the invention is not limited to this. The present invention can be applied to an apparatus that is conditioned on stopping the operation of at least a control element that controls a load when an abnormality is detected.

[0056]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

It is determined whether the output of the microcomputer is normal or abnormal. If the output is determined to be abnormal, a semiconductor integrated circuit device having a function of outputting a reset signal and a mask signal to the microcomputer is connected to the microcomputer. When the semiconductor integrated circuit device determines that the output of the microcomputer is abnormal, the reset signal is output to the microcomputer, and the output of the microcomputer is stopped by masking the output of the microcomputer with a mask signal. By simplifying the configuration, it is possible to configure a microcomputer monitoring system that outputs a reset signal to the microcomputer and outputs a mask signal for masking the output of the microcomputer.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a microcomputer monitoring system according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a monitoring IC used in the microcomputer monitoring system according to the embodiment of the present invention.

FIG. 3 is a timing chart illustrating the operation of the microcomputer monitoring system according to the embodiment of the present invention when the microcomputer is not operating.

FIG. 4 is a timing chart illustrating the operation of the microcomputer monitoring system according to the embodiment of the present invention when the microcomputer operates normally.

FIG. 5 is a timing chart illustrating the operation of the microcomputer monitoring system according to the embodiment of the present invention when the microcomputer operates abnormally.

[Explanation of symbols]

1 ... microcomputer (microcomputer) monitoring system,
2 ... microcomputer (microcomputer), 3 ... load, 4
... Monitoring IC (semiconductor integrated circuit device), 5, 11 AND gate, 6 WDT (Watch Dog Time)
r) part, 7 ... reset part, 8 ... mask signal output part, 9 ...
First comparator, 10... Second comparator, 12
... OR gate, 13 ... third comparator, 14 ... fourth
Latch circuit, SR reset signal, SM mask signal, Q, Q1, Q2, Q3 transistor, I1, I2, I3 constant current source, CW first capacitor, CR second Capacitor, SW ... Switch,
V1, V1 ', V2, V2', V3... Reference potential, IV1
... first inverter, IV2 ... second inverter, Vc
c: power supply, R1 to R4: resistance.

Claims (6)

[Claims] 1. A microcomputer monitoring system which constantly monitors the operation of a microcomputer for controlling a desired load and stops an output of the microcomputer when an abnormality is detected. Is determined to be normal or abnormal, and when determined to be abnormal, a semiconductor integrated circuit device having a function of outputting a mask signal together with a reset signal is connected to the microcomputer, and the semiconductor integrated circuit device outputs the output of the microcomputer. A microcomputer monitoring system that outputs the reset signal to the microcomputer when the abnormality is determined, and stops the microcomputer output by masking the microcomputer output with the mask signal; 2. The microcomputer monitoring system according to claim 1, wherein the semiconductor integrated circuit device monitors a pulse width of an output of the microcomputer to determine whether the output is normal or abnormal. 3. The microcomputer monitoring system according to claim 2, wherein the semiconductor integrated circuit device judges that the output is abnormal when the pulse width of the output of the microcomputer fluctuates greatly. 4. A semiconductor integrated circuit device connected to a microcomputer and constantly monitoring its operation by inputting its output. When it is determined that the output of said microcomputer is abnormal, the microcomputer is connected to the microcomputer. A semiconductor integrated circuit device having a function of outputting a reset signal and a mask signal for masking an output of a microcomputer. 5. The semiconductor integrated circuit device according to claim 4, wherein the output is judged to be abnormal when the pulse width of the output of the microcomputer is large. 6. A semiconductor integrated circuit device which is connected to a microcomputer and constantly monitors its operation by inputting its output. The semiconductor integrated circuit device receives an output of the microcomputer and regularly or in accordance with a pulse width thereof. A watch dog timer unit that generates an irregular triangular wave signal and outputs a signal of a predetermined level only when the level of the triangular wave signal is within two reference potential ranges, and an output of the watch dog timer unit And a reset unit for generating a triangular wave signal whose peak rises or falls according to the duration of the signal of the predetermined level, and outputs a reset signal which alternates between HL according to the level of the triangular wave signal And a mask signal output unit that receives an output of the reset unit and outputs a mask signal at the timing of outputting the reset signal. A semiconductor integrated circuit device characterized by the above-mentioned.